mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-30 22:26:55 +00:00
Merge branch 'for-joerg/arm-smmu/fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into iommu/fixes
This commit is contained in:
commit
4df36185bb
3 changed files with 15 additions and 30 deletions
|
@ -879,7 +879,7 @@ static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu)
|
||||||
* We may have concurrent producers, so we need to be careful
|
* We may have concurrent producers, so we need to be careful
|
||||||
* not to touch any of the shadow cmdq state.
|
* not to touch any of the shadow cmdq state.
|
||||||
*/
|
*/
|
||||||
queue_read(cmd, Q_ENT(q, idx), q->ent_dwords);
|
queue_read(cmd, Q_ENT(q, cons), q->ent_dwords);
|
||||||
dev_err(smmu->dev, "skipping command in error state:\n");
|
dev_err(smmu->dev, "skipping command in error state:\n");
|
||||||
for (i = 0; i < ARRAY_SIZE(cmd); ++i)
|
for (i = 0; i < ARRAY_SIZE(cmd); ++i)
|
||||||
dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]);
|
dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]);
|
||||||
|
@ -890,7 +890,7 @@ static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
queue_write(cmd, Q_ENT(q, idx), q->ent_dwords);
|
queue_write(Q_ENT(q, cons), cmd, q->ent_dwords);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,
|
static void arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,
|
||||||
|
@ -1034,6 +1034,9 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
|
||||||
case STRTAB_STE_0_CFG_S2_TRANS:
|
case STRTAB_STE_0_CFG_S2_TRANS:
|
||||||
ste_live = true;
|
ste_live = true;
|
||||||
break;
|
break;
|
||||||
|
case STRTAB_STE_0_CFG_ABORT:
|
||||||
|
if (disable_bypass)
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
BUG(); /* STE corruption */
|
BUG(); /* STE corruption */
|
||||||
}
|
}
|
||||||
|
|
|
@ -686,8 +686,7 @@ static struct iommu_gather_ops arm_smmu_gather_ops = {
|
||||||
|
|
||||||
static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
|
static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
|
||||||
{
|
{
|
||||||
int flags, ret;
|
u32 fsr, fsynr;
|
||||||
u32 fsr, fsynr, resume;
|
|
||||||
unsigned long iova;
|
unsigned long iova;
|
||||||
struct iommu_domain *domain = dev;
|
struct iommu_domain *domain = dev;
|
||||||
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
|
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
|
||||||
|
@ -701,34 +700,15 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
|
||||||
if (!(fsr & FSR_FAULT))
|
if (!(fsr & FSR_FAULT))
|
||||||
return IRQ_NONE;
|
return IRQ_NONE;
|
||||||
|
|
||||||
if (fsr & FSR_IGN)
|
|
||||||
dev_err_ratelimited(smmu->dev,
|
|
||||||
"Unexpected context fault (fsr 0x%x)\n",
|
|
||||||
fsr);
|
|
||||||
|
|
||||||
fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
|
fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
|
||||||
flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
|
|
||||||
|
|
||||||
iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);
|
iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);
|
||||||
if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
|
|
||||||
ret = IRQ_HANDLED;
|
|
||||||
resume = RESUME_RETRY;
|
|
||||||
} else {
|
|
||||||
dev_err_ratelimited(smmu->dev,
|
|
||||||
"Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
|
|
||||||
iova, fsynr, cfg->cbndx);
|
|
||||||
ret = IRQ_NONE;
|
|
||||||
resume = RESUME_TERMINATE;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Clear the faulting FSR */
|
dev_err_ratelimited(smmu->dev,
|
||||||
|
"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cb=%d\n",
|
||||||
|
fsr, iova, fsynr, cfg->cbndx);
|
||||||
|
|
||||||
writel(fsr, cb_base + ARM_SMMU_CB_FSR);
|
writel(fsr, cb_base + ARM_SMMU_CB_FSR);
|
||||||
|
return IRQ_HANDLED;
|
||||||
/* Retry or terminate any stalled transactions */
|
|
||||||
if (fsr & FSR_SS)
|
|
||||||
writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
|
static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
|
||||||
|
@ -837,7 +817,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
|
||||||
}
|
}
|
||||||
|
|
||||||
/* SCTLR */
|
/* SCTLR */
|
||||||
reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
|
reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
|
||||||
if (stage1)
|
if (stage1)
|
||||||
reg |= SCTLR_S1_ASIDPNE;
|
reg |= SCTLR_S1_ASIDPNE;
|
||||||
#ifdef __BIG_ENDIAN
|
#ifdef __BIG_ENDIAN
|
||||||
|
|
|
@ -286,12 +286,14 @@ static int arm_v7s_pte_to_prot(arm_v7s_iopte pte, int lvl)
|
||||||
int prot = IOMMU_READ;
|
int prot = IOMMU_READ;
|
||||||
arm_v7s_iopte attr = pte >> ARM_V7S_ATTR_SHIFT(lvl);
|
arm_v7s_iopte attr = pte >> ARM_V7S_ATTR_SHIFT(lvl);
|
||||||
|
|
||||||
if (attr & ARM_V7S_PTE_AP_RDONLY)
|
if (!(attr & ARM_V7S_PTE_AP_RDONLY))
|
||||||
prot |= IOMMU_WRITE;
|
prot |= IOMMU_WRITE;
|
||||||
if ((attr & (ARM_V7S_TEX_MASK << ARM_V7S_TEX_SHIFT)) == 0)
|
if ((attr & (ARM_V7S_TEX_MASK << ARM_V7S_TEX_SHIFT)) == 0)
|
||||||
prot |= IOMMU_MMIO;
|
prot |= IOMMU_MMIO;
|
||||||
else if (pte & ARM_V7S_ATTR_C)
|
else if (pte & ARM_V7S_ATTR_C)
|
||||||
prot |= IOMMU_CACHE;
|
prot |= IOMMU_CACHE;
|
||||||
|
if (pte & ARM_V7S_ATTR_XN(lvl))
|
||||||
|
prot |= IOMMU_NOEXEC;
|
||||||
|
|
||||||
return prot;
|
return prot;
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in a new issue