mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 09:19:51 +00:00
drm/i915: Move gmbus definitions out of i915_reg.h
They're not related to registers, so move them to the more appropriate intel_gmbus.h Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190816012343.36433-4-daniele.ceraolospurio@intel.com
This commit is contained in:
parent
3d7b303974
commit
4e3f12d866
3 changed files with 23 additions and 20 deletions
|
@ -11,6 +11,28 @@
|
|||
struct drm_i915_private;
|
||||
struct i2c_adapter;
|
||||
|
||||
#define GMBUS_PIN_DISABLED 0
|
||||
#define GMBUS_PIN_SSC 1
|
||||
#define GMBUS_PIN_VGADDC 2
|
||||
#define GMBUS_PIN_PANEL 3
|
||||
#define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
|
||||
#define GMBUS_PIN_DPC 4 /* HDMIC */
|
||||
#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
|
||||
#define GMBUS_PIN_DPD 6 /* HDMID */
|
||||
#define GMBUS_PIN_RESERVED 7 /* 7 reserved */
|
||||
#define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */
|
||||
#define GMBUS_PIN_2_BXT 2
|
||||
#define GMBUS_PIN_3_BXT 3
|
||||
#define GMBUS_PIN_4_CNP 4
|
||||
#define GMBUS_PIN_9_TC1_ICP 9
|
||||
#define GMBUS_PIN_10_TC2_ICP 10
|
||||
#define GMBUS_PIN_11_TC3_ICP 11
|
||||
#define GMBUS_PIN_12_TC4_ICP 12
|
||||
#define GMBUS_PIN_13_TC5_TGP 13
|
||||
#define GMBUS_PIN_14_TC6_TGP 14
|
||||
|
||||
#define GMBUS_NUM_PINS 15 /* including 0 */
|
||||
|
||||
int intel_gmbus_setup(struct drm_i915_private *dev_priv);
|
||||
void intel_gmbus_teardown(struct drm_i915_private *dev_priv);
|
||||
bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
|
||||
|
|
|
@ -68,6 +68,7 @@
|
|||
#include "display/intel_display_power.h"
|
||||
#include "display/intel_dpll_mgr.h"
|
||||
#include "display/intel_frontbuffer.h"
|
||||
#include "display/intel_gmbus.h"
|
||||
#include "display/intel_opregion.h"
|
||||
|
||||
#include "gem/i915_gem_context_types.h"
|
||||
|
|
|
@ -3207,27 +3207,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
|
|||
#define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */
|
||||
#define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */
|
||||
#define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
|
||||
#define GMBUS_PIN_DISABLED 0
|
||||
#define GMBUS_PIN_SSC 1
|
||||
#define GMBUS_PIN_VGADDC 2
|
||||
#define GMBUS_PIN_PANEL 3
|
||||
#define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
|
||||
#define GMBUS_PIN_DPC 4 /* HDMIC */
|
||||
#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
|
||||
#define GMBUS_PIN_DPD 6 /* HDMID */
|
||||
#define GMBUS_PIN_RESERVED 7 /* 7 reserved */
|
||||
#define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */
|
||||
#define GMBUS_PIN_2_BXT 2
|
||||
#define GMBUS_PIN_3_BXT 3
|
||||
#define GMBUS_PIN_4_CNP 4
|
||||
#define GMBUS_PIN_9_TC1_ICP 9
|
||||
#define GMBUS_PIN_10_TC2_ICP 10
|
||||
#define GMBUS_PIN_11_TC3_ICP 11
|
||||
#define GMBUS_PIN_12_TC4_ICP 12
|
||||
#define GMBUS_PIN_13_TC5_TGP 13
|
||||
#define GMBUS_PIN_14_TC6_TGP 14
|
||||
|
||||
#define GMBUS_NUM_PINS 15 /* including 0 */
|
||||
#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
|
||||
#define GMBUS_SW_CLR_INT (1 << 31)
|
||||
#define GMBUS_SW_RDY (1 << 30)
|
||||
|
|
Loading…
Reference in a new issue