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drm/amdgpu/pm: document pp_od_clk_voltage
sysfs interface for fine grained clock and voltage control. Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -455,6 +455,29 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
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return count;
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return count;
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}
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}
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/**
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* DOC: pp_od_clk_voltage
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*
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* The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
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* in each power level within a power state. The pp_od_clk_voltage is used for
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* this.
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*
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* Reading the file will display:
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* - a list of engine clock levels and voltages labeled OD_SCLK
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* - a list of memory clock levels and voltages labeled OD_MCLK
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* - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
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*
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* To manually adjust these settings, first select manual using
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* power_dpm_force_performance_level. Enter a new value for each
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* level by writing a string that contains "s/m level clock voltage" to
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* the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
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* at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
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* 810 mV. When you have edited all of the states as needed, write
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* "c" (commit) to the file to commit your changes. If you want to reset to the
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* default power levels, write "r" (reset) to the file to reset them.
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*
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*/
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static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
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static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
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struct device_attribute *attr,
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struct device_attribute *attr,
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const char *buf,
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const char *buf,
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