LoongArch: Add some instruction opcodes and formats
According to the "Table of Instruction Encoding" in LoongArch Reference Manual [1], add some instruction opcodes and formats which are used in the BPF JIT for LoongArch. [1] https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#table-of-instruction-encoding Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
This commit is contained in:
Tiezhu Yang
Huacai Chen
parent
8a34228eb3
commit
4e59e5a469
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@ -8,6 +8,8 @@
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#include <linux/types.h>
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#include <asm/asm.h>
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#define INSN_BREAK 0x002a0000
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#define ADDR_IMMMASK_LU52ID 0xFFF0000000000000
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#define ADDR_IMMMASK_LU32ID 0x000FFFFF00000000
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#define ADDR_IMMMASK_ADDU16ID 0x00000000FFFF0000
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@ -18,9 +20,16 @@
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#define ADDR_IMM(addr, INSN) ((addr & ADDR_IMMMASK_##INSN) >> ADDR_IMMSHIFT_##INSN)
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enum reg0i26_op {
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b_op = 0x14,
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bl_op = 0x15,
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};
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enum reg1i20_op {
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lu12iw_op = 0x0a,
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lu32id_op = 0x0b,
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pcaddu12i_op = 0x0e,
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pcaddu18i_op = 0x0f,
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};
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enum reg1i21_op {
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@ -28,10 +37,34 @@ enum reg1i21_op {
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bnez_op = 0x11,
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};
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enum reg2_op {
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revb2h_op = 0x0c,
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revb4h_op = 0x0d,
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revb2w_op = 0x0e,
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revbd_op = 0x0f,
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revh2w_op = 0x10,
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revhd_op = 0x11,
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};
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enum reg2i5_op {
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slliw_op = 0x81,
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srliw_op = 0x89,
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sraiw_op = 0x91,
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};
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enum reg2i6_op {
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sllid_op = 0x41,
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srlid_op = 0x45,
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sraid_op = 0x49,
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};
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enum reg2i12_op {
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addiw_op = 0x0a,
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addid_op = 0x0b,
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lu52id_op = 0x0c,
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andi_op = 0x0d,
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ori_op = 0x0e,
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xori_op = 0x0f,
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ldb_op = 0xa0,
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ldh_op = 0xa1,
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ldw_op = 0xa2,
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@ -40,6 +73,20 @@ enum reg2i12_op {
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sth_op = 0xa5,
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stw_op = 0xa6,
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std_op = 0xa7,
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ldbu_op = 0xa8,
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ldhu_op = 0xa9,
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ldwu_op = 0xaa,
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};
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enum reg2i14_op {
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llw_op = 0x20,
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scw_op = 0x21,
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lld_op = 0x22,
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scd_op = 0x23,
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ldptrw_op = 0x24,
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stptrw_op = 0x25,
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ldptrd_op = 0x26,
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stptrd_op = 0x27,
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};
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enum reg2i16_op {
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@ -52,6 +99,71 @@ enum reg2i16_op {
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bgeu_op = 0x1b,
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};
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enum reg2bstrd_op {
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bstrinsd_op = 0x2,
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bstrpickd_op = 0x3,
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};
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enum reg3_op {
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addw_op = 0x20,
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addd_op = 0x21,
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subw_op = 0x22,
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subd_op = 0x23,
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nor_op = 0x28,
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and_op = 0x29,
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or_op = 0x2a,
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xor_op = 0x2b,
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orn_op = 0x2c,
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andn_op = 0x2d,
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sllw_op = 0x2e,
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srlw_op = 0x2f,
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sraw_op = 0x30,
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slld_op = 0x31,
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srld_op = 0x32,
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srad_op = 0x33,
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mulw_op = 0x38,
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mulhw_op = 0x39,
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mulhwu_op = 0x3a,
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muld_op = 0x3b,
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mulhd_op = 0x3c,
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mulhdu_op = 0x3d,
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divw_op = 0x40,
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modw_op = 0x41,
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divwu_op = 0x42,
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modwu_op = 0x43,
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divd_op = 0x44,
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modd_op = 0x45,
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divdu_op = 0x46,
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moddu_op = 0x47,
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ldxb_op = 0x7000,
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ldxh_op = 0x7008,
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ldxw_op = 0x7010,
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ldxd_op = 0x7018,
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stxb_op = 0x7020,
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stxh_op = 0x7028,
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stxw_op = 0x7030,
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stxd_op = 0x7038,
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ldxbu_op = 0x7040,
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ldxhu_op = 0x7048,
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ldxwu_op = 0x7050,
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amswapw_op = 0x70c0,
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amswapd_op = 0x70c1,
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amaddw_op = 0x70c2,
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amaddd_op = 0x70c3,
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amandw_op = 0x70c4,
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amandd_op = 0x70c5,
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amorw_op = 0x70c6,
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amord_op = 0x70c7,
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amxorw_op = 0x70c8,
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amxord_op = 0x70c9,
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};
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enum reg3sa2_op {
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alslw_op = 0x02,
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alslwu_op = 0x03,
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alsld_op = 0x16,
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};
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struct reg0i26_format {
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unsigned int immediate_h : 10;
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unsigned int immediate_l : 16;
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@ -71,6 +183,26 @@ struct reg1i21_format {
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unsigned int opcode : 6;
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};
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struct reg2_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int opcode : 22;
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};
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struct reg2i5_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int immediate : 5;
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unsigned int opcode : 17;
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};
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struct reg2i6_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int immediate : 6;
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unsigned int opcode : 16;
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};
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struct reg2i12_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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@ -78,6 +210,13 @@ struct reg2i12_format {
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unsigned int opcode : 10;
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};
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struct reg2i14_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int immediate : 14;
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unsigned int opcode : 8;
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};
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struct reg2i16_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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@ -85,13 +224,43 @@ struct reg2i16_format {
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unsigned int opcode : 6;
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};
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struct reg2bstrd_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int lsbd : 6;
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unsigned int msbd : 6;
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unsigned int opcode : 10;
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};
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struct reg3_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int rk : 5;
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unsigned int opcode : 17;
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};
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struct reg3sa2_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int rk : 5;
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unsigned int immediate : 2;
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unsigned int opcode : 15;
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};
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union loongarch_instruction {
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unsigned int word;
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struct reg0i26_format reg0i26_format;
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struct reg1i20_format reg1i20_format;
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struct reg1i21_format reg1i21_format;
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struct reg2i12_format reg2i12_format;
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struct reg2i16_format reg2i16_format;
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struct reg0i26_format reg0i26_format;
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struct reg1i20_format reg1i20_format;
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struct reg1i21_format reg1i21_format;
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struct reg2_format reg2_format;
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struct reg2i5_format reg2i5_format;
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struct reg2i6_format reg2i6_format;
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struct reg2i12_format reg2i12_format;
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struct reg2i14_format reg2i14_format;
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struct reg2i16_format reg2i16_format;
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struct reg2bstrd_format reg2bstrd_format;
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struct reg3_format reg3_format;
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struct reg3sa2_format reg3sa2_format;
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};
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#define LOONGARCH_INSN_SIZE sizeof(union loongarch_instruction)
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