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drm/radeon: consolidate redundant macros and constants
After refactoring the _cs logic, we ended up with many macros and constants that #define the same thing. Clean'em up. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
012e976d42
commit
4e872ae2bb
12 changed files with 35 additions and 104 deletions
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@ -2639,12 +2639,12 @@ int evergreen_cs_parse(struct radeon_cs_parser *p)
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}
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p->idx += pkt.count + 2;
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switch (pkt.type) {
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case PACKET_TYPE0:
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case RADEON_PACKET_TYPE0:
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r = evergreen_cs_parse_packet0(p, &pkt);
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break;
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case PACKET_TYPE2:
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case RADEON_PACKET_TYPE2:
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break;
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case PACKET_TYPE3:
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case RADEON_PACKET_TYPE3:
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r = evergreen_packet3_check(p, &pkt);
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break;
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default:
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@ -3395,19 +3395,19 @@ int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
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do {
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pkt.idx = idx;
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pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]);
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pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]);
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pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
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pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
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pkt.one_reg_wr = 0;
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switch (pkt.type) {
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case PACKET_TYPE0:
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case RADEON_PACKET_TYPE0:
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dev_err(rdev->dev, "Packet0 not allowed!\n");
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ret = -EINVAL;
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break;
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case PACKET_TYPE2:
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case RADEON_PACKET_TYPE2:
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idx += 1;
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break;
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case PACKET_TYPE3:
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pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
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case RADEON_PACKET_TYPE3:
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pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
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ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt);
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idx += pkt.count + 2;
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break;
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@ -980,16 +980,7 @@
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/*
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* PM4
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*/
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#define PACKET_TYPE0 0
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#define PACKET_TYPE1 1
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#define PACKET_TYPE2 2
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#define PACKET_TYPE3 3
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#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
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#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
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#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
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#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
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#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
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#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
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(((reg) >> 2) & 0xFFFF) | \
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((n) & 0x3FFF) << 16)
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#define CP_PACKET2 0x80000000
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@ -998,7 +989,7 @@
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#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
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#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
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(((op) & 0xFF) << 8) | \
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((n) & 0x3FFF) << 16)
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@ -474,16 +474,7 @@
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/*
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* PM4
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*/
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#define PACKET_TYPE0 0
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#define PACKET_TYPE1 1
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#define PACKET_TYPE2 2
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#define PACKET_TYPE3 3
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#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
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#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
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#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
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#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
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#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
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#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
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(((reg) >> 2) & 0xFFFF) | \
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((n) & 0x3FFF) << 16)
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#define CP_PACKET2 0x80000000
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@ -492,7 +483,7 @@
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#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
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#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
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(((op) & 0xFF) << 8) | \
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((n) & 0x3FFF) << 16)
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@ -1410,7 +1410,7 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
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header = radeon_get_ib_value(p, h_idx);
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crtc_id = radeon_get_ib_value(p, h_idx + 5);
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reg = CP_PACKET0_GET_REG(header);
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reg = R100_CP_PACKET0_GET_REG(header);
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obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
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if (!obj) {
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DRM_ERROR("cannot find crtc %d\n", crtc_id);
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@ -1997,7 +1997,7 @@ int r100_cs_parse(struct radeon_cs_parser *p)
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}
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p->idx += pkt.count + 2;
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switch (pkt.type) {
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case PACKET_TYPE0:
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case RADEON_PACKET_TYPE0:
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if (p->rdev->family >= CHIP_R200)
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r = r100_cs_parse_packet0(p, &pkt,
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p->rdev->config.r100.reg_safe_bm,
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@ -2009,9 +2009,9 @@ int r100_cs_parse(struct radeon_cs_parser *p)
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p->rdev->config.r100.reg_safe_bm_size,
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&r100_packet0_check);
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break;
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case PACKET_TYPE2:
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case RADEON_PACKET_TYPE2:
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break;
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case PACKET_TYPE3:
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case RADEON_PACKET_TYPE3:
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r = r100_packet3_check(p, &pkt);
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break;
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default:
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@ -64,17 +64,6 @@
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REG_SET(PACKET3_IT_OPCODE, (op)) | \
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REG_SET(PACKET3_COUNT, (n)))
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#define PACKET_TYPE0 0
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#define PACKET_TYPE1 1
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#define PACKET_TYPE2 2
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#define PACKET_TYPE3 3
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#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
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#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
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#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
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#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
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#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
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/* Registers */
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#define R_0000F0_RBBM_SOFT_RESET 0x0000F0
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#define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0)
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@ -1263,15 +1263,15 @@ int r300_cs_parse(struct radeon_cs_parser *p)
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}
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p->idx += pkt.count + 2;
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switch (pkt.type) {
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case PACKET_TYPE0:
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case RADEON_PACKET_TYPE0:
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r = r100_cs_parse_packet0(p, &pkt,
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p->rdev->config.r300.reg_safe_bm,
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p->rdev->config.r300.reg_safe_bm_size,
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&r300_packet0_check);
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break;
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case PACKET_TYPE2:
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case RADEON_PACKET_TYPE2:
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break;
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case PACKET_TYPE3:
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case RADEON_PACKET_TYPE3:
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r = r300_packet3_check(p, &pkt);
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break;
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default:
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@ -65,17 +65,6 @@
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REG_SET(PACKET3_IT_OPCODE, (op)) | \
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REG_SET(PACKET3_COUNT, (n)))
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#define PACKET_TYPE0 0
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#define PACKET_TYPE1 1
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#define PACKET_TYPE2 2
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#define PACKET_TYPE3 3
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#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
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#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
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#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
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#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
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#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
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/* Registers */
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#define R_000148_MC_FB_LOCATION 0x000148
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#define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0)
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@ -839,7 +839,7 @@ int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
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return r;
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/* check its a WAIT_REG_MEM */
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if (wait_reg_mem.type != PACKET_TYPE3 ||
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if (wait_reg_mem.type != RADEON_PACKET_TYPE3 ||
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wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
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DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
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return -EINVAL;
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@ -882,7 +882,7 @@ int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
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header = radeon_get_ib_value(p, h_idx);
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crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
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reg = CP_PACKET0_GET_REG(header);
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reg = R600_CP_PACKET0_GET_REG(header);
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obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
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if (!obj) {
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@ -2282,12 +2282,12 @@ int r600_cs_parse(struct radeon_cs_parser *p)
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}
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p->idx += pkt.count + 2;
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switch (pkt.type) {
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case PACKET_TYPE0:
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case RADEON_PACKET_TYPE0:
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r = r600_cs_parse_packet0(p, &pkt);
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break;
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case PACKET_TYPE2:
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case RADEON_PACKET_TYPE2:
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break;
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case PACKET_TYPE3:
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case RADEON_PACKET_TYPE3:
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r = r600_packet3_check(p, &pkt);
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break;
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default:
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@ -1143,19 +1143,10 @@
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/*
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* PM4
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*/
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#define PACKET_TYPE0 0
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#define PACKET_TYPE1 1
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#define PACKET_TYPE2 2
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#define PACKET_TYPE3 3
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#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
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#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
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#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
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#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
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#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
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#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
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(((reg) >> 2) & 0xFFFF) | \
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((n) & 0x3FFF) << 16)
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#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
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#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
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(((op) & 0xFF) << 8) | \
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((n) & 0x3FFF) << 16)
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@ -205,17 +205,6 @@
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REG_SET(PACKET3_IT_OPCODE, (op)) | \
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REG_SET(PACKET3_COUNT, (n)))
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#define PACKET_TYPE0 0
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#define PACKET_TYPE1 1
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#define PACKET_TYPE2 2
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#define PACKET_TYPE3 3
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#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
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#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
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#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
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#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
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#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
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/* Registers */
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#define R_0000F0_RBBM_SOFT_RESET 0x0000F0
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#define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0)
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@ -2855,19 +2855,19 @@ int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
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do {
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pkt.idx = idx;
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pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]);
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pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]);
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pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
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pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
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pkt.one_reg_wr = 0;
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switch (pkt.type) {
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case PACKET_TYPE0:
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case RADEON_PACKET_TYPE0:
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dev_err(rdev->dev, "Packet0 not allowed!\n");
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ret = -EINVAL;
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break;
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case PACKET_TYPE2:
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case RADEON_PACKET_TYPE2:
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idx += 1;
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break;
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case PACKET_TYPE3:
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pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
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case RADEON_PACKET_TYPE3:
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pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
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if (ib->is_const_ib)
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ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
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else {
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@ -783,16 +783,7 @@
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/*
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* PM4
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*/
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#define PACKET_TYPE0 0
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#define PACKET_TYPE1 1
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#define PACKET_TYPE2 2
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#define PACKET_TYPE3 3
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#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
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#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
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#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
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#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
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#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
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#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
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(((reg) >> 2) & 0xFFFF) | \
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((n) & 0x3FFF) << 16)
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#define CP_PACKET2 0x80000000
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@ -801,7 +792,7 @@
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#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
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#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
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(((op) & 0xFF) << 8) | \
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((n) & 0x3FFF) << 16)
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