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mtd: pxa3xx_nand: unify prepare command
Make the interface simpler which could make both debug and enhancement easier. Signed-off-by: Lei Wen <leiwen@marvell.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Lei Wen
David Woodhouse
parent
38caf7f68e
commit
4eb2da8994
1 changed files with 158 additions and 129 deletions
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@ -28,6 +28,7 @@
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#define CHIP_DELAY_TIMEOUT (2 * HZ/10)
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#define NAND_STOP_DELAY (2 * HZ/50)
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#define PAGE_CHUNK_SIZE (2048)
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/* registers and bit definitions */
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#define NDCR (0x00) /* Control register */
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@ -77,6 +78,7 @@
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#define NDSR_RDDREQ (0x1 << 1)
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#define NDSR_WRCMDREQ (0x1)
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#define NDCB0_ST_ROW_EN (0x1 << 26)
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#define NDCB0_AUTO_RS (0x1 << 25)
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#define NDCB0_CSEL (0x1 << 24)
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#define NDCB0_CMD_TYPE_MASK (0x7 << 21)
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@ -319,66 +321,6 @@ static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
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nand_writel(info, NDSR, NDSR_MASK);
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}
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static void prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
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uint16_t cmd, int column, int page_addr)
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{
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const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
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pxa3xx_set_datasize(info);
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/* generate values for NDCBx registers */
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info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
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info->ndcb1 = 0;
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info->ndcb2 = 0;
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info->ndcb0 |= NDCB0_ADDR_CYC(info->row_addr_cycles + info->col_addr_cycles);
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if (info->col_addr_cycles == 2) {
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/* large block, 2 cycles for column address
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* row address starts from 3rd cycle
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*/
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info->ndcb1 |= page_addr << 16;
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if (info->row_addr_cycles == 3)
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info->ndcb2 = (page_addr >> 16) & 0xff;
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} else
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/* small block, 1 cycles for column address
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* row address starts from 2nd cycle
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*/
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info->ndcb1 = page_addr << 8;
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if (cmd == cmdset->program)
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info->ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS;
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}
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static void prepare_erase_cmd(struct pxa3xx_nand_info *info,
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uint16_t cmd, int page_addr)
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{
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info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
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info->ndcb0 |= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS | NDCB0_ADDR_CYC(3);
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info->ndcb1 = page_addr;
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info->ndcb2 = 0;
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}
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static void prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
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{
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const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
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info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
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info->ndcb1 = 0;
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info->ndcb2 = 0;
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info->oob_size = 0;
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if (cmd == cmdset->read_id) {
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info->ndcb0 |= NDCB0_CMD_TYPE(3) | NDCB0_ADDR_CYC(1);
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info->data_size = 8;
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} else if (cmd == cmdset->read_status) {
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info->ndcb0 |= NDCB0_CMD_TYPE(4);
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info->data_size = 8;
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} else if (cmd == cmdset->reset || cmd == cmdset->lock ||
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cmd == cmdset->unlock) {
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info->ndcb0 |= NDCB0_CMD_TYPE(5);
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} else
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BUG();
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}
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static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
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{
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uint32_t ndcr;
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@ -529,81 +471,167 @@ static inline int is_buf_blank(uint8_t *buf, size_t len)
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return 1;
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}
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static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
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uint16_t column, int page_addr)
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{
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uint16_t cmd;
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int addr_cycle, exec_cmd, ndcb0;
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struct mtd_info *mtd = info->mtd;
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ndcb0 = 0;
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addr_cycle = 0;
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exec_cmd = 1;
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/* reset data and oob column point to handle data */
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info->buf_start = 0;
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info->buf_count = 0;
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info->oob_size = 0;
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info->use_ecc = 0;
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info->retcode = ERR_NONE;
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switch (command) {
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case NAND_CMD_READ0:
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case NAND_CMD_PAGEPROG:
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info->use_ecc = 1;
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case NAND_CMD_READOOB:
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pxa3xx_set_datasize(info);
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break;
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case NAND_CMD_SEQIN:
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exec_cmd = 0;
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break;
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default:
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info->ndcb1 = 0;
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info->ndcb2 = 0;
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break;
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}
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info->ndcb0 = ndcb0;
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addr_cycle = NDCB0_ADDR_CYC(info->row_addr_cycles
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+ info->col_addr_cycles);
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switch (command) {
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case NAND_CMD_READOOB:
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case NAND_CMD_READ0:
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cmd = info->cmdset->read1;
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if (command == NAND_CMD_READOOB)
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info->buf_start = mtd->writesize + column;
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else
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info->buf_start = column;
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if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
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info->ndcb0 |= NDCB0_CMD_TYPE(0)
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| addr_cycle
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| (cmd & NDCB0_CMD1_MASK);
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else
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info->ndcb0 |= NDCB0_CMD_TYPE(0)
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| NDCB0_DBC
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| addr_cycle
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| cmd;
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case NAND_CMD_SEQIN:
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/* small page addr setting */
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if (unlikely(info->page_size < PAGE_CHUNK_SIZE)) {
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info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
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| (column & 0xFF);
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info->ndcb2 = 0;
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} else {
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info->ndcb1 = ((page_addr & 0xFFFF) << 16)
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| (column & 0xFFFF);
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if (page_addr & 0xFF0000)
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info->ndcb2 = (page_addr & 0xFF0000) >> 16;
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else
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info->ndcb2 = 0;
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}
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info->buf_count = mtd->writesize + mtd->oobsize;
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memset(info->data_buff, 0xFF, info->buf_count);
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break;
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case NAND_CMD_PAGEPROG:
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if (is_buf_blank(info->data_buff,
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(mtd->writesize + mtd->oobsize))) {
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exec_cmd = 0;
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break;
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}
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cmd = info->cmdset->program;
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info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
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| NDCB0_AUTO_RS
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| NDCB0_ST_ROW_EN
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| NDCB0_DBC
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| cmd
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| addr_cycle;
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break;
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case NAND_CMD_READID:
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cmd = info->cmdset->read_id;
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info->buf_count = info->read_id_bytes;
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info->ndcb0 |= NDCB0_CMD_TYPE(3)
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| NDCB0_ADDR_CYC(1)
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| cmd;
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info->data_size = 8;
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break;
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case NAND_CMD_STATUS:
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cmd = info->cmdset->read_status;
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info->buf_count = 1;
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info->ndcb0 |= NDCB0_CMD_TYPE(4)
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| NDCB0_ADDR_CYC(1)
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| cmd;
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info->data_size = 8;
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break;
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case NAND_CMD_ERASE1:
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cmd = info->cmdset->erase;
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info->ndcb0 |= NDCB0_CMD_TYPE(2)
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| NDCB0_AUTO_RS
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| NDCB0_ADDR_CYC(3)
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| NDCB0_DBC
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| cmd;
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info->ndcb1 = page_addr;
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info->ndcb2 = 0;
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break;
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case NAND_CMD_RESET:
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cmd = info->cmdset->reset;
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info->ndcb0 |= NDCB0_CMD_TYPE(5)
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| cmd;
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break;
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case NAND_CMD_ERASE2:
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exec_cmd = 0;
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break;
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default:
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exec_cmd = 0;
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printk(KERN_ERR "pxa3xx-nand: non-supported"
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" command %x\n", command);
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break;
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}
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return exec_cmd;
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}
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static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
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int column, int page_addr)
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{
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struct pxa3xx_nand_info *info = mtd->priv;
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const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
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int ret, exec_cmd = 0;
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int ret, exec_cmd;
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info->use_dma = (use_dma) ? 1 : 0;
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info->use_ecc = 0;
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info->data_size = 0;
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info->state = 0;
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info->retcode = ERR_NONE;
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switch (command) {
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case NAND_CMD_READOOB:
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/* disable HW ECC to get all the OOB data */
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info->buf_count = mtd->writesize + mtd->oobsize;
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info->buf_start = mtd->writesize + column;
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memset(info->data_buff, 0xFF, info->buf_count);
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prepare_read_prog_cmd(info, cmdset->read1, column, page_addr);
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exec_cmd = 1;
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break;
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case NAND_CMD_READ0:
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info->use_ecc = 1;
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info->buf_start = column;
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info->buf_count = mtd->writesize + mtd->oobsize;
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memset(info->data_buff, 0xFF, info->buf_count);
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prepare_read_prog_cmd(info, cmdset->read1, column, page_addr);
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exec_cmd = 1;
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break;
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case NAND_CMD_SEQIN:
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info->buf_start = column;
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info->buf_count = mtd->writesize + mtd->oobsize;
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memset(info->data_buff, 0xff, info->buf_count);
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/* save column/page_addr for next CMD_PAGEPROG */
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info->seqin_column = column;
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info->seqin_page_addr = page_addr;
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break;
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case NAND_CMD_PAGEPROG:
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info->use_ecc = (info->seqin_column >= mtd->writesize) ? 0 : 1;
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prepare_read_prog_cmd(info, cmdset->program,
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info->seqin_column, info->seqin_page_addr);
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exec_cmd = 1;
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break;
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case NAND_CMD_ERASE1:
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prepare_erase_cmd(info, cmdset->erase, page_addr);
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exec_cmd = 1;
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break;
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case NAND_CMD_ERASE2:
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break;
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case NAND_CMD_READID:
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case NAND_CMD_STATUS:
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info->use_dma = 0; /* force PIO read */
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info->buf_start = 0;
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info->buf_count = (command == NAND_CMD_READID) ?
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info->read_id_bytes : 1;
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prepare_other_cmd(info, (command == NAND_CMD_READID) ?
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cmdset->read_id : cmdset->read_status);
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exec_cmd = 1;
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break;
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case NAND_CMD_RESET:
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prepare_other_cmd(info, cmdset->reset);
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exec_cmd = 1;
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break;
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default:
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printk(KERN_ERR "non-supported command.\n");
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break;
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}
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/*
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* if this is a x16 device ,then convert the input
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* "byte" address into a "word" address appropriate
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* for indexing a word-oriented device
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*/
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if (info->reg_ndcr & NDCR_DWIDTH_M)
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column /= 2;
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exec_cmd = prepare_command_pool(info, command, column, page_addr);
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if (exec_cmd) {
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init_completion(&info->cmd_complete);
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pxa3xx_nand_start(info);
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@ -919,6 +947,7 @@ static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
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struct nand_chip *this = &info->nand_chip;
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this->options = (info->reg_ndcr & NDCR_DWIDTH_C) ? NAND_BUSWIDTH_16: 0;
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this->options |= NAND_NO_AUTOINCR;
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this->waitfunc = pxa3xx_nand_waitfunc;
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this->select_chip = pxa3xx_nand_select_chip;
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