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ARM: OMAP4+: PRM: add support for passing status register/bit info to reset
AM43xx has slightly different reset register layout compared to OMAP4+, with varying status bit shifts and status register offsets. Current code assumes static offsets and identical status / reset control bit shifts, which is wrong. This patch adds PRM core support for passing the actual implementations from hwmod code. AM43xx mappings will be fixed in subsequent patch. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reported-by: Dave Gerlach <d-gerlach@ti.com> Reported-by: Suman Anna <s-anna@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
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9a55706221
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4ebf5b288c
2 changed files with 17 additions and 15 deletions
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@ -171,6 +171,12 @@
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*/
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#define LINKS_PER_OCP_IF 2
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/*
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* Address offset (in bytes) between the reset control and the reset
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* status registers: 4 bytes on OMAP4
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*/
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#define OMAP4_RST_CTRL_ST_OFFSET 4
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/**
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* struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations
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* @enable_module: function to enable a module (via MODULEMODE)
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@ -3016,10 +3022,12 @@ static int _omap4_deassert_hardreset(struct omap_hwmod *oh,
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if (ohri->st_shift)
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pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
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oh->name, ohri->name);
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return omap_prm_deassert_hardreset(ohri->rst_shift, 0,
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return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->rst_shift,
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oh->clkdm->pwrdm.ptr->prcm_partition,
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oh->clkdm->pwrdm.ptr->prcm_offs,
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oh->prcm.omap4.rstctrl_offs, 0);
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oh->prcm.omap4.rstctrl_offs,
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oh->prcm.omap4.rstctrl_offs +
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OMAP4_RST_CTRL_ST_OFFSET);
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}
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/**
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@ -87,12 +87,6 @@ u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
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return v;
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}
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/*
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* Address offset (in bytes) between the reset control and the reset
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* status registers: 4 bytes on OMAP4
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*/
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#define OMAP4_RST_CTRL_ST_OFFSET 4
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/**
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* omap4_prminst_is_hardreset_asserted - read the HW reset line state of
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* submodules contained in the hwmod module
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@ -141,11 +135,11 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
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* omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
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* wait
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* @shift: register bit shift corresponding to the reset line to deassert
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* @st_shift: status bit offset, not used for OMAP4+
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* @st_shift: status bit offset corresponding to the reset line
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* @part: PRM partition
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* @inst: PRM instance offset
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* @rstctrl_offs: reset register offset
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* @st_offs: reset status register offset, not used for OMAP4+
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* @rstst_offs: reset status register offset
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*
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* Some IPs like dsp, ipu or iva contain processors that require an HW
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* reset line to be asserted / deasserted in order to fully enable the
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@ -157,11 +151,11 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
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* of reset, or -EBUSY if the submodule did not exit reset promptly.
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*/
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int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
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u16 rstctrl_offs, u16 st_offs)
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u16 rstctrl_offs, u16 rstst_offs)
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{
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int c;
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u32 mask = 1 << shift;
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u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET;
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u32 st_mask = 1 << st_shift;
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/* Check the current status to avoid de-asserting the line twice */
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if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
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@ -169,13 +163,13 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
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return -EEXIST;
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/* Clear the reset status by writing 1 to the status bit */
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omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst,
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omap4_prminst_rmw_inst_reg_bits(0xffffffff, st_mask, part, inst,
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rstst_offs);
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/* de-assert the reset control line */
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omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
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/* wait the status to be set */
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omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst,
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rstst_offs),
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omap_test_timeout(omap4_prminst_is_hardreset_asserted(st_shift, part,
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inst, rstst_offs),
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MAX_MODULE_HARDRESET_WAIT, c);
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return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
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