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ARM: OMAP4+: PRM: add support for passing status register/bit info to reset

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AM43xx has slightly different reset register layout compared to OMAP4+,
with varying status bit shifts and status register offsets. Current
code assumes static offsets and identical status / reset control bit
shifts, which is wrong. This patch adds PRM core support for passing
the actual implementations from hwmod code. AM43xx mappings will be fixed
in subsequent patch.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reported-by: Dave Gerlach <d-gerlach@ti.com>
Reported-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
Tero Kristo 2015-05-05 16:33:04 +03:00 committed by Paul Walmsley
parent 9a55706221
commit 4ebf5b288c
2 changed files with 17 additions and 15 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
arch/arm/mach-omap2/omap_hwmod.c
View file

@ -171,6 +171,12 @@
*/ */
#define LINKS_PER_OCP_IF 2 #define LINKS_PER_OCP_IF 2
/*
* Address offset (in bytes) between the reset control and the reset
* status registers: 4 bytes on OMAP4
*/
#define OMAP4_RST_CTRL_ST_OFFSET 4
/** /**
* struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations
* @enable_module: function to enable a module (via MODULEMODE) * @enable_module: function to enable a module (via MODULEMODE)
@ -3016,10 +3022,12 @@ static int _omap4_deassert_hardreset(struct omap_hwmod *oh,
if (ohri->st_shift) if (ohri->st_shift)
pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
oh->name, ohri->name); oh->name, ohri->name);
return omap_prm_deassert_hardreset(ohri->rst_shift, 0, return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->rst_shift,
oh->clkdm->pwrdm.ptr->prcm_partition, oh->clkdm->pwrdm.ptr->prcm_partition,
oh->clkdm->pwrdm.ptr->prcm_offs, oh->clkdm->pwrdm.ptr->prcm_offs,
oh->prcm.omap4.rstctrl_offs, 0); oh->prcm.omap4.rstctrl_offs,
oh->prcm.omap4.rstctrl_offs +
OMAP4_RST_CTRL_ST_OFFSET);
} }
/** /**

20
arch/arm/mach-omap2/prminst44xx.c
View file

@ -87,12 +87,6 @@ u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
return v; return v;
} }
/*
* Address offset (in bytes) between the reset control and the reset
* status registers: 4 bytes on OMAP4
*/
#define OMAP4_RST_CTRL_ST_OFFSET 4
/** /**
* omap4_prminst_is_hardreset_asserted - read the HW reset line state of * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
* submodules contained in the hwmod module * submodules contained in the hwmod module
@ -141,11 +135,11 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
* omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
* wait * wait
* @shift: register bit shift corresponding to the reset line to deassert * @shift: register bit shift corresponding to the reset line to deassert
* @st_shift: status bit offset, not used for OMAP4+ * @st_shift: status bit offset corresponding to the reset line
* @part: PRM partition * @part: PRM partition
* @inst: PRM instance offset * @inst: PRM instance offset
* @rstctrl_offs: reset register offset * @rstctrl_offs: reset register offset
* @st_offs: reset status register offset, not used for OMAP4+ * @rstst_offs: reset status register offset
* *
* Some IPs like dsp, ipu or iva contain processors that require an HW * Some IPs like dsp, ipu or iva contain processors that require an HW
* reset line to be asserted / deasserted in order to fully enable the * reset line to be asserted / deasserted in order to fully enable the
@ -157,11 +151,11 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
* of reset, or -EBUSY if the submodule did not exit reset promptly. * of reset, or -EBUSY if the submodule did not exit reset promptly.
*/ */
int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst, int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
u16 rstctrl_offs, u16 st_offs) u16 rstctrl_offs, u16 rstst_offs)
{ {
int c; int c;
u32 mask = 1 << shift; u32 mask = 1 << shift;
u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET; u32 st_mask = 1 << st_shift;
/* Check the current status to avoid de-asserting the line twice */ /* Check the current status to avoid de-asserting the line twice */
if (omap4_prminst_is_hardreset_asserted(shift, part, inst, if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
@ -169,13 +163,13 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
return -EEXIST; return -EEXIST;
/* Clear the reset status by writing 1 to the status bit */ /* Clear the reset status by writing 1 to the status bit */
omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst, omap4_prminst_rmw_inst_reg_bits(0xffffffff, st_mask, part, inst,
rstst_offs); rstst_offs);
/* de-assert the reset control line */ /* de-assert the reset control line */
omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs); omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
/* wait the status to be set */ /* wait the status to be set */
omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst, omap_test_timeout(omap4_prminst_is_hardreset_asserted(st_shift, part,
rstst_offs), inst, rstst_offs),
MAX_MODULE_HARDRESET_WAIT, c); MAX_MODULE_HARDRESET_WAIT, c);
return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;