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irqchip: spear_shirq: Precalculate status mask
Calculate the status mask at compile time, not at runtime. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20140619212713.496614337@linutronix.de Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
parent
e3c871ab23
commit
4ecc832f4e
1 changed files with 12 additions and 1 deletions
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@ -49,6 +49,7 @@ struct shirq_regs {
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*
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*
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* base: Base register address
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* base: Base register address
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* regs: Register configuration for shared irq block
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* regs: Register configuration for shared irq block
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* mask: Mask to apply to the status register
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* virq_base: Base virtual interrupt number
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* virq_base: Base virtual interrupt number
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* nr_irqs: Number of interrupts handled by this block
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* nr_irqs: Number of interrupts handled by this block
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* offset: Bit offset of the first interrupt
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* offset: Bit offset of the first interrupt
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@ -57,6 +58,7 @@ struct shirq_regs {
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struct spear_shirq {
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struct spear_shirq {
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void __iomem *base;
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void __iomem *base;
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struct shirq_regs regs;
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struct shirq_regs regs;
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u32 mask;
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u32 virq_base;
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u32 virq_base;
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u32 nr_irqs;
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u32 nr_irqs;
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u32 offset;
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u32 offset;
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@ -72,6 +74,7 @@ static DEFINE_SPINLOCK(lock);
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static struct spear_shirq spear300_shirq_ras1 = {
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static struct spear_shirq spear300_shirq_ras1 = {
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.offset = 0,
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.offset = 0,
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.nr_irqs = 9,
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.nr_irqs = 9,
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.mask = ((0x1 << 9) - 1) << 0,
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.regs = {
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.regs = {
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.enb_reg = SPEAR300_INT_ENB_MASK_REG,
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.enb_reg = SPEAR300_INT_ENB_MASK_REG,
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.status_reg = SPEAR300_INT_STS_MASK_REG,
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.status_reg = SPEAR300_INT_STS_MASK_REG,
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@ -89,6 +92,7 @@ static struct spear_shirq *spear300_shirq_blocks[] = {
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static struct spear_shirq spear310_shirq_ras1 = {
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static struct spear_shirq spear310_shirq_ras1 = {
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.offset = 0,
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.offset = 0,
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.nr_irqs = 8,
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.nr_irqs = 8,
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.mask = ((0x1 << 8) - 1) << 0,
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.regs = {
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.regs = {
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.enb_reg = -1,
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.enb_reg = -1,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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@ -99,6 +103,7 @@ static struct spear_shirq spear310_shirq_ras1 = {
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static struct spear_shirq spear310_shirq_ras2 = {
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static struct spear_shirq spear310_shirq_ras2 = {
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.offset = 8,
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.offset = 8,
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.nr_irqs = 5,
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.nr_irqs = 5,
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.mask = ((0x1 << 5) - 1) << 8,
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.regs = {
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.regs = {
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.enb_reg = -1,
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.enb_reg = -1,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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@ -109,6 +114,7 @@ static struct spear_shirq spear310_shirq_ras2 = {
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static struct spear_shirq spear310_shirq_ras3 = {
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static struct spear_shirq spear310_shirq_ras3 = {
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.offset = 13,
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.offset = 13,
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.nr_irqs = 1,
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.nr_irqs = 1,
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.mask = ((0x1 << 1) - 1) << 13,
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.regs = {
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.regs = {
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.enb_reg = -1,
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.enb_reg = -1,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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@ -119,6 +125,7 @@ static struct spear_shirq spear310_shirq_ras3 = {
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static struct spear_shirq spear310_shirq_intrcomm_ras = {
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static struct spear_shirq spear310_shirq_intrcomm_ras = {
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.offset = 14,
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.offset = 14,
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.nr_irqs = 3,
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.nr_irqs = 3,
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.mask = ((0x1 << 3) - 1) << 14,
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.regs = {
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.regs = {
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.enb_reg = -1,
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.enb_reg = -1,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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@ -141,6 +148,7 @@ static struct spear_shirq *spear310_shirq_blocks[] = {
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static struct spear_shirq spear320_shirq_ras3 = {
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static struct spear_shirq spear320_shirq_ras3 = {
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.offset = 0,
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.offset = 0,
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.nr_irqs = 7,
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.nr_irqs = 7,
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.mask = ((0x1 << 7) - 1) << 0,
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.disabled = 1,
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.disabled = 1,
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.regs = {
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.regs = {
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.enb_reg = SPEAR320_INT_ENB_MASK_REG,
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.enb_reg = SPEAR320_INT_ENB_MASK_REG,
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@ -154,6 +162,7 @@ static struct spear_shirq spear320_shirq_ras3 = {
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static struct spear_shirq spear320_shirq_ras1 = {
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static struct spear_shirq spear320_shirq_ras1 = {
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.offset = 7,
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.offset = 7,
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.nr_irqs = 3,
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.nr_irqs = 3,
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.mask = ((0x1 << 3) - 1) << 7,
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.regs = {
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.regs = {
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.enb_reg = -1,
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.enb_reg = -1,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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@ -165,6 +174,7 @@ static struct spear_shirq spear320_shirq_ras1 = {
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static struct spear_shirq spear320_shirq_ras2 = {
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static struct spear_shirq spear320_shirq_ras2 = {
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.offset = 10,
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.offset = 10,
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.nr_irqs = 1,
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.nr_irqs = 1,
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.mask = ((0x1 << 1) - 1) << 10,
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.regs = {
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.regs = {
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.enb_reg = -1,
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.enb_reg = -1,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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@ -176,6 +186,7 @@ static struct spear_shirq spear320_shirq_ras2 = {
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static struct spear_shirq spear320_shirq_intrcomm_ras = {
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static struct spear_shirq spear320_shirq_intrcomm_ras = {
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.offset = 11,
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.offset = 11,
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.nr_irqs = 11,
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.nr_irqs = 11,
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.mask = ((0x1 << 11) - 1) << 11,
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.regs = {
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.regs = {
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.enb_reg = -1,
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.enb_reg = -1,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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@ -239,7 +250,7 @@ static void shirq_handler(unsigned irq, struct irq_desc *desc)
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chip->irq_ack(idata);
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chip->irq_ack(idata);
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mask = ((0x1 << shirq->nr_irqs) - 1) << shirq->offset;
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mask = shirq->mask;
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while ((val = readl(shirq->base + shirq->regs.status_reg) &
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while ((val = readl(shirq->base + shirq->regs.status_reg) &
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mask)) {
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mask)) {
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