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ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi'
The clock which was named as 'pll_clk' is actually not the clock source of PLL in MIPI DSI. This patch fixes this disagreement. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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@ -167,7 +167,7 @@ dsi_0: dsi@11C80000 {
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phys = <&mipi_phy 1>;
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phy-names = "dsim";
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clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
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clock-names = "bus_clk", "pll_clk";
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clock-names = "bus_clk", "sclk_mipi";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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