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Revert "mtd: rawnand: sunxi: Add A23/A33 DMA support"
This reverts commitc49836f05a
. The commit is wrong and its approach actually does not work. Let's revert it in order to add the feature with a clean patch. Fixes:c49836f05a
("mtd: rawnand: sunxi: Add A23/A33 DMA support") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This commit is contained in:
parent
c403ec33b6
commit
4f032640bf
1 changed files with 2 additions and 36 deletions
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@ -43,7 +43,6 @@
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#define NFC_REG_RCMD_SET 0x0028
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#define NFC_REG_WCMD_SET 0x002C
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#define NFC_REG_A10_IO_DATA 0x0030
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#define NFC_REG_A23_IO_DATA 0x0300
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#define NFC_REG_ECC_CTL 0x0034
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#define NFC_REG_ECC_ST 0x0038
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#define NFC_REG_DEBUG 0x003C
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@ -205,14 +204,10 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
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* NAND Controller capabilities structure: stores NAND controller capabilities
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* for distinction between compatible strings.
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*
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* @sram_through_ahb: On A23, we choose to access the internal RAM through AHB
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* instead of MBUS (less configuration). A10, A10s, A13 and
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* A20 use the MBUS but no extra configuration is needed.
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* @reg_io_data: I/O data register
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* @dma_maxburst: DMA maxburst
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*/
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struct sunxi_nfc_caps {
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bool sram_through_ahb;
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unsigned int reg_io_data;
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unsigned int dma_maxburst;
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};
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@ -368,29 +363,10 @@ static int sunxi_nfc_dma_op_prepare(struct sunxi_nfc *nfc, const void *buf,
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goto err_unmap_buf;
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}
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/*
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* On A23, we suppose the "internal RAM" (p.12 of the NFC user manual)
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* refers to the NAND controller's internal SRAM. This memory is mapped
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* and so is accessible from the AHB. It seems that it can also be
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* accessed by the MBUS. MBUS accesses are mandatory when using the
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* internal DMA instead of the external DMA engine.
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*
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* During DMA I/O operation, either we access this memory from the AHB
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* by clearing the NFC_RAM_METHOD bit, or we set the bit and use the
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* MBUS. In this case, we should also configure the MBUS DMA length
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* NFC_REG_MDMA_CNT(0xC4) to be chunksize * nchunks. NAND I/O over MBUS
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* are also limited to 32kiB pages.
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*/
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if (nfc->caps->sram_through_ahb)
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writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
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nfc->regs + NFC_REG_CTL);
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else
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writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD,
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nfc->regs + NFC_REG_CTL);
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writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD,
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nfc->regs + NFC_REG_CTL);
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writel(nchunks, nfc->regs + NFC_REG_SECTOR_NUM);
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writel(chunksize, nfc->regs + NFC_REG_CNT);
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dmat = dmaengine_submit(dmad);
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ret = dma_submit_error(dmat);
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@ -2199,21 +2175,11 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps = {
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.dma_maxburst = 4,
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};
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static const struct sunxi_nfc_caps sunxi_nfc_a23_caps = {
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.sram_through_ahb = true,
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.reg_io_data = NFC_REG_A23_IO_DATA,
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.dma_maxburst = 8,
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};
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static const struct of_device_id sunxi_nfc_ids[] = {
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{
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.compatible = "allwinner,sun4i-a10-nand",
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.data = &sunxi_nfc_a10_caps,
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},
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{
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.compatible = "allwinner,sun8i-a23-nand-controller",
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.data = &sunxi_nfc_a23_caps,
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},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
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