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riscv,entry: fix misaligned base for excp_vect_table
[ Upstream commit ac8d0b901f
]
In RV64, the size of each entry in excp_vect_table is 8 bytes. If the
base of the table is not 8-byte aligned, loading an entry in the table
will raise a misaligned exception. Although such exception will be
handled by opensbi/bbl, this still causes performance degradation.
Signed-off-by: Zihao Yu <yuzihao@ict.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -449,6 +449,7 @@ ENDPROC(__fstate_restore)
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.section ".rodata"
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.align LGREG
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/* Exception vector table */
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ENTRY(excp_vect_table)
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RISCV_PTR do_trap_insn_misaligned
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