mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 11:19:37 +00:00
Merge branch 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel into drm-core-next
Daniel prepared this branch with a back-merge as git was getting very confused about changes in intel_display.c
This commit is contained in:
commit
4f256e8aa3
687 changed files with 6559 additions and 4098 deletions
19
Documentation/ABI/testing/sysfs-bus-hsi
Normal file
19
Documentation/ABI/testing/sysfs-bus-hsi
Normal file
|
@ -0,0 +1,19 @@
|
|||
What: /sys/bus/hsi
|
||||
Date: April 2012
|
||||
KernelVersion: 3.4
|
||||
Contact: Carlos Chinea <carlos.chinea@nokia.com>
|
||||
Description:
|
||||
High Speed Synchronous Serial Interface (HSI) is a
|
||||
serial interface mainly used for connecting application
|
||||
engines (APE) with cellular modem engines (CMT) in cellular
|
||||
handsets.
|
||||
The bus will be populated with devices (hsi_clients) representing
|
||||
the protocols available in the system. Bus drivers implement
|
||||
those protocols.
|
||||
|
||||
What: /sys/bus/hsi/devices/.../modalias
|
||||
Date: April 2012
|
||||
KernelVersion: 3.4
|
||||
Contact: Carlos Chinea <carlos.chinea@nokia.com>
|
||||
Description: Stores the same MODALIAS value emitted by uevent
|
||||
Format: hsi:<hsi_client device name>
|
|
@ -1,6 +1,6 @@
|
|||
<refentry id="V4L2-PIX-FMT-NV12M">
|
||||
<refmeta>
|
||||
<refentrytitle>V4L2_PIX_FMT_NV12M ('NV12M')</refentrytitle>
|
||||
<refentrytitle>V4L2_PIX_FMT_NV12M ('NM12')</refentrytitle>
|
||||
&manvol;
|
||||
</refmeta>
|
||||
<refnamediv>
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
<refentry id="V4L2-PIX-FMT-YUV420M">
|
||||
<refmeta>
|
||||
<refentrytitle>V4L2_PIX_FMT_YUV420M ('YU12M')</refentrytitle>
|
||||
<refentrytitle>V4L2_PIX_FMT_YUV420M ('YM12')</refentrytitle>
|
||||
&manvol;
|
||||
</refmeta>
|
||||
<refnamediv>
|
||||
|
|
|
@ -1,10 +1,10 @@
|
|||
* Calxeda SATA Controller
|
||||
* AHCI SATA Controller
|
||||
|
||||
SATA nodes are defined to describe on-chip Serial ATA controllers.
|
||||
Each SATA controller should have its own node.
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible list, contains "calxeda,hb-ahci"
|
||||
- compatible : compatible list, contains "calxeda,hb-ahci" or "snps,spear-ahci"
|
||||
- interrupts : <interrupt mapping for SATA IRQ>
|
||||
- reg : <registers mapping>
|
||||
|
||||
|
@ -14,4 +14,3 @@ Example:
|
|||
reg = <0xffe08000 0x1000>;
|
||||
interrupts = <115>;
|
||||
};
|
||||
|
|
@ -3,6 +3,8 @@
|
|||
Required properties:
|
||||
- compatible : "fsl,sgtl5000".
|
||||
|
||||
- reg : the I2C address of the device
|
||||
|
||||
Example:
|
||||
|
||||
codec: sgtl5000@0a {
|
||||
|
|
|
@ -147,7 +147,7 @@ tcp_adv_win_scale - INTEGER
|
|||
(if tcp_adv_win_scale > 0) or bytes-bytes/2^(-tcp_adv_win_scale),
|
||||
if it is <= 0.
|
||||
Possible values are [-31, 31], inclusive.
|
||||
Default: 2
|
||||
Default: 1
|
||||
|
||||
tcp_allowed_congestion_control - STRING
|
||||
Show/set the congestion control choices available to non-privileged
|
||||
|
@ -410,7 +410,7 @@ tcp_rmem - vector of 3 INTEGERs: min, default, max
|
|||
net.core.rmem_max. Calling setsockopt() with SO_RCVBUF disables
|
||||
automatic tuning of that socket's receive buffer size, in which
|
||||
case this value is ignored.
|
||||
Default: between 87380B and 4MB, depending on RAM size.
|
||||
Default: between 87380B and 6MB, depending on RAM size.
|
||||
|
||||
tcp_sack - BOOLEAN
|
||||
Enable select acknowledgments (SACKS).
|
||||
|
|
|
@ -9,7 +9,7 @@ architectures).
|
|||
|
||||
II. How does it work?
|
||||
|
||||
There are four per-task flags used for that, PF_NOFREEZE, PF_FROZEN, TIF_FREEZE
|
||||
There are three per-task flags used for that, PF_NOFREEZE, PF_FROZEN
|
||||
and PF_FREEZER_SKIP (the last one is auxiliary). The tasks that have
|
||||
PF_NOFREEZE unset (all user space processes and some kernel threads) are
|
||||
regarded as 'freezable' and treated in a special way before the system enters a
|
||||
|
@ -17,30 +17,31 @@ suspend state as well as before a hibernation image is created (in what follows
|
|||
we only consider hibernation, but the description also applies to suspend).
|
||||
|
||||
Namely, as the first step of the hibernation procedure the function
|
||||
freeze_processes() (defined in kernel/power/process.c) is called. It executes
|
||||
try_to_freeze_tasks() that sets TIF_FREEZE for all of the freezable tasks and
|
||||
either wakes them up, if they are kernel threads, or sends fake signals to them,
|
||||
if they are user space processes. A task that has TIF_FREEZE set, should react
|
||||
to it by calling the function called __refrigerator() (defined in
|
||||
kernel/freezer.c), which sets the task's PF_FROZEN flag, changes its state
|
||||
to TASK_UNINTERRUPTIBLE and makes it loop until PF_FROZEN is cleared for it.
|
||||
Then, we say that the task is 'frozen' and therefore the set of functions
|
||||
handling this mechanism is referred to as 'the freezer' (these functions are
|
||||
defined in kernel/power/process.c, kernel/freezer.c & include/linux/freezer.h).
|
||||
User space processes are generally frozen before kernel threads.
|
||||
freeze_processes() (defined in kernel/power/process.c) is called. A system-wide
|
||||
variable system_freezing_cnt (as opposed to a per-task flag) is used to indicate
|
||||
whether the system is to undergo a freezing operation. And freeze_processes()
|
||||
sets this variable. After this, it executes try_to_freeze_tasks() that sends a
|
||||
fake signal to all user space processes, and wakes up all the kernel threads.
|
||||
All freezable tasks must react to that by calling try_to_freeze(), which
|
||||
results in a call to __refrigerator() (defined in kernel/freezer.c), which sets
|
||||
the task's PF_FROZEN flag, changes its state to TASK_UNINTERRUPTIBLE and makes
|
||||
it loop until PF_FROZEN is cleared for it. Then, we say that the task is
|
||||
'frozen' and therefore the set of functions handling this mechanism is referred
|
||||
to as 'the freezer' (these functions are defined in kernel/power/process.c,
|
||||
kernel/freezer.c & include/linux/freezer.h). User space processes are generally
|
||||
frozen before kernel threads.
|
||||
|
||||
__refrigerator() must not be called directly. Instead, use the
|
||||
try_to_freeze() function (defined in include/linux/freezer.h), that checks
|
||||
the task's TIF_FREEZE flag and makes the task enter __refrigerator() if the
|
||||
flag is set.
|
||||
if the task is to be frozen and makes the task enter __refrigerator().
|
||||
|
||||
For user space processes try_to_freeze() is called automatically from the
|
||||
signal-handling code, but the freezable kernel threads need to call it
|
||||
explicitly in suitable places or use the wait_event_freezable() or
|
||||
wait_event_freezable_timeout() macros (defined in include/linux/freezer.h)
|
||||
that combine interruptible sleep with checking if TIF_FREEZE is set and calling
|
||||
try_to_freeze(). The main loop of a freezable kernel thread may look like the
|
||||
following one:
|
||||
that combine interruptible sleep with checking if the task is to be frozen and
|
||||
calling try_to_freeze(). The main loop of a freezable kernel thread may look
|
||||
like the following one:
|
||||
|
||||
set_freezable();
|
||||
do {
|
||||
|
@ -53,7 +54,7 @@ following one:
|
|||
(from drivers/usb/core/hub.c::hub_thread()).
|
||||
|
||||
If a freezable kernel thread fails to call try_to_freeze() after the freezer has
|
||||
set TIF_FREEZE for it, the freezing of tasks will fail and the entire
|
||||
initiated a freezing operation, the freezing of tasks will fail and the entire
|
||||
hibernation operation will be cancelled. For this reason, freezable kernel
|
||||
threads must call try_to_freeze() somewhere or use one of the
|
||||
wait_event_freezable() and wait_event_freezable_timeout() macros.
|
||||
|
|
|
@ -123,7 +123,7 @@ KEY SERVICE OVERVIEW
|
|||
|
||||
The key service provides a number of features besides keys:
|
||||
|
||||
(*) The key service defines two special key types:
|
||||
(*) The key service defines three special key types:
|
||||
|
||||
(+) "keyring"
|
||||
|
||||
|
@ -137,6 +137,18 @@ The key service provides a number of features besides keys:
|
|||
blobs of data. These can be created, updated and read by userspace,
|
||||
and aren't intended for use by kernel services.
|
||||
|
||||
(+) "logon"
|
||||
|
||||
Like a "user" key, a "logon" key has a payload that is an arbitrary
|
||||
blob of data. It is intended as a place to store secrets which are
|
||||
accessible to the kernel but not to userspace programs.
|
||||
|
||||
The description can be arbitrary, but must be prefixed with a non-zero
|
||||
length string that describes the key "subclass". The subclass is
|
||||
separated from the rest of the description by a ':'. "logon" keys can
|
||||
be created and updated from userspace, but the payload is only
|
||||
readable from kernel space.
|
||||
|
||||
(*) Each process subscribes to three keyrings: a thread-specific keyring, a
|
||||
process-specific keyring, and a session-specific keyring.
|
||||
|
||||
|
|
16
MAINTAINERS
16
MAINTAINERS
|
@ -1968,10 +1968,7 @@ S: Maintained
|
|||
F: drivers/net/ethernet/ti/cpmac.c
|
||||
|
||||
CPU FREQUENCY DRIVERS
|
||||
M: Dave Jones <davej@redhat.com>
|
||||
L: cpufreq@vger.kernel.org
|
||||
W: http://www.codemonkey.org.uk/projects/cpufreq/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/davej/cpufreq.git
|
||||
S: Maintained
|
||||
F: drivers/cpufreq/
|
||||
F: include/linux/cpufreq.h
|
||||
|
@ -2321,9 +2318,9 @@ S: Supported
|
|||
F: drivers/acpi/dock.c
|
||||
|
||||
DOCUMENTATION
|
||||
M: Randy Dunlap <rdunlap@xenotime.net>
|
||||
M: Rob Landley <rob@landley.net>
|
||||
L: linux-doc@vger.kernel.org
|
||||
T: quilt http://xenotime.net/kernel-doc-patches/current/
|
||||
T: TBD
|
||||
S: Maintained
|
||||
F: Documentation/
|
||||
|
||||
|
@ -3592,6 +3589,7 @@ S: Supported
|
|||
F: drivers/net/wireless/iwlegacy/
|
||||
|
||||
INTEL WIRELESS WIFI LINK (iwlwifi)
|
||||
M: Johannes Berg <johannes.berg@intel.com>
|
||||
M: Wey-Yi Guy <wey-yi.w.guy@intel.com>
|
||||
M: Intel Linux Wireless <ilw@linux.intel.com>
|
||||
L: linux-wireless@vger.kernel.org
|
||||
|
@ -5891,11 +5889,11 @@ F: Documentation/scsi/st.txt
|
|||
F: drivers/scsi/st*
|
||||
|
||||
SCTP PROTOCOL
|
||||
M: Vlad Yasevich <vladislav.yasevich@hp.com>
|
||||
M: Vlad Yasevich <vyasevich@gmail.com>
|
||||
M: Sridhar Samudrala <sri@us.ibm.com>
|
||||
L: linux-sctp@vger.kernel.org
|
||||
W: http://lksctp.sourceforge.net
|
||||
S: Supported
|
||||
S: Maintained
|
||||
F: Documentation/networking/sctp.txt
|
||||
F: include/linux/sctp.h
|
||||
F: include/net/sctp/
|
||||
|
@ -7578,8 +7576,8 @@ F: Documentation/filesystems/xfs.txt
|
|||
F: fs/xfs/
|
||||
|
||||
XILINX AXI ETHERNET DRIVER
|
||||
M: Ariane Keller <ariane.keller@tik.ee.ethz.ch>
|
||||
M: Daniel Borkmann <daniel.borkmann@tik.ee.ethz.ch>
|
||||
M: Anirudha Sarangi <anirudh@xilinx.com>
|
||||
M: John Linn <John.Linn@xilinx.com>
|
||||
S: Maintained
|
||||
F: drivers/net/ethernet/xilinx/xilinx_axienet*
|
||||
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 4
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc3
|
||||
EXTRAVERSION = -rc6
|
||||
NAME = Saber-toothed Squirrel
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -477,7 +477,7 @@ config ALPHA_BROKEN_IRQ_MASK
|
|||
|
||||
config VGA_HOSE
|
||||
bool
|
||||
depends on ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL || ALPHA_TSUNAMI
|
||||
depends on VGA_CONSOLE && (ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL || ALPHA_TSUNAMI)
|
||||
default y
|
||||
help
|
||||
Support VGA on an arbitrary hose; needed for several platforms
|
||||
|
|
|
@ -1,14 +1,10 @@
|
|||
#ifndef _ALPHA_RTC_H
|
||||
#define _ALPHA_RTC_H
|
||||
|
||||
#if defined(CONFIG_ALPHA_GENERIC)
|
||||
#if defined(CONFIG_ALPHA_MARVEL) && defined(CONFIG_SMP) \
|
||||
|| defined(CONFIG_ALPHA_GENERIC)
|
||||
# define get_rtc_time alpha_mv.rtc_get_time
|
||||
# define set_rtc_time alpha_mv.rtc_set_time
|
||||
#else
|
||||
# if defined(CONFIG_ALPHA_MARVEL) && defined(CONFIG_SMP)
|
||||
# define get_rtc_time marvel_get_rtc_time
|
||||
# define set_rtc_time marvel_set_rtc_time
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#include <asm-generic/rtc.h>
|
||||
|
|
|
@ -11,6 +11,7 @@
|
|||
#include <asm/core_tsunami.h>
|
||||
#undef __EXTERN_INLINE
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/sched.h>
|
||||
|
|
|
@ -317,7 +317,7 @@ marvel_init_irq(void)
|
|||
}
|
||||
|
||||
static int
|
||||
marvel_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
marvel_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
struct pci_controller *hose = dev->sysdata;
|
||||
struct io7_port *io7_port = hose->sysdata;
|
||||
|
|
|
@ -1186,6 +1186,15 @@ if !MMU
|
|||
source "arch/arm/Kconfig-nommu"
|
||||
endif
|
||||
|
||||
config ARM_ERRATA_326103
|
||||
bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
|
||||
depends on CPU_V6
|
||||
help
|
||||
Executing a SWP instruction to read-only memory does not set bit 11
|
||||
of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
|
||||
treat the access as a read, preventing a COW from occurring and
|
||||
causing the faulting task to livelock.
|
||||
|
||||
config ARM_ERRATA_411920
|
||||
bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
|
||||
depends on CPU_V6 || CPU_V6K
|
||||
|
|
|
@ -10,7 +10,7 @@ / {
|
|||
intc: interrupt-controller@02080000 {
|
||||
compatible = "qcom,msm-8660-qgic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <3>;
|
||||
reg = < 0x02080000 0x1000 >,
|
||||
< 0x02081000 0x1000 >;
|
||||
};
|
||||
|
@ -19,6 +19,6 @@ serial@19c400000 {
|
|||
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
|
||||
reg = <0x19c40000 0x1000>,
|
||||
<0x19c00000 0x1000>;
|
||||
interrupts = <195>;
|
||||
interrupts = <0 195 0x0>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -173,7 +173,7 @@ aaci@4000 {
|
|||
mmc@5000 {
|
||||
compatible = "arm,primecell";
|
||||
reg = < 0x5000 0x1000>;
|
||||
interrupts = <22>;
|
||||
interrupts = <22 34>;
|
||||
};
|
||||
kmi@6000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
|
|
|
@ -41,7 +41,7 @@ sci@a000 {
|
|||
mmc@b000 {
|
||||
compatible = "arm,primecell";
|
||||
reg = <0xb000 0x1000>;
|
||||
interrupts = <23>;
|
||||
interrupts = <23 34>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -112,6 +112,7 @@ CONFIG_WATCHDOG=y
|
|||
CONFIG_IMX2_WDT=y
|
||||
CONFIG_MFD_MC13XXX=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_MC13783=y
|
||||
CONFIG_REGULATOR_MC13892=y
|
||||
CONFIG_FB=y
|
||||
|
|
|
@ -14,6 +14,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
|
|||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_BLK_DEV_INTEGRITY=y
|
||||
CONFIG_ARCH_S3C24XX=y
|
||||
# CONFIG_CPU_S3C2410 is not set
|
||||
CONFIG_CPU_S3C2440=y
|
||||
CONFIG_S3C_ADC=y
|
||||
CONFIG_S3C24XX_PWM=y
|
||||
CONFIG_MACH_MINI2440=y
|
||||
|
|
|
@ -8,8 +8,6 @@ CONFIG_MODULE_UNLOAD=y
|
|||
# CONFIG_LBDAF is not set
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_ARCH_U8500=y
|
||||
CONFIG_UX500_SOC_DB5500=y
|
||||
CONFIG_UX500_SOC_DB8500=y
|
||||
CONFIG_MACH_HREFV60=y
|
||||
CONFIG_MACH_SNOWBALL=y
|
||||
CONFIG_MACH_U5500=y
|
||||
|
@ -39,7 +37,6 @@ CONFIG_CAIF=y
|
|||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=65536
|
||||
CONFIG_MISC_DEVICES=y
|
||||
CONFIG_AB8500_PWM=y
|
||||
CONFIG_SENSORS_BH1780=y
|
||||
CONFIG_NETDEVICES=y
|
||||
|
@ -65,16 +62,18 @@ CONFIG_SERIAL_AMBA_PL011=y
|
|||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HW_RANDOM_NOMADIK=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_NOMADIK=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_PL022=y
|
||||
CONFIG_GPIO_STMPE=y
|
||||
CONFIG_GPIO_TC3589X=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_AB8500_BM=y
|
||||
CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL=y
|
||||
CONFIG_MFD_STMPE=y
|
||||
CONFIG_MFD_TC3589X=y
|
||||
CONFIG_AB5500_CORE=y
|
||||
CONFIG_AB8500_CORE=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_AB8500=y
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
CONFIG_USB_GADGET=y
|
||||
|
|
|
@ -118,6 +118,13 @@ extern void iwmmxt_task_switch(struct thread_info *);
|
|||
extern void vfp_sync_hwstate(struct thread_info *);
|
||||
extern void vfp_flush_hwstate(struct thread_info *);
|
||||
|
||||
struct user_vfp;
|
||||
struct user_vfp_exc;
|
||||
|
||||
extern int vfp_preserve_user_clear_hwstate(struct user_vfp __user *,
|
||||
struct user_vfp_exc __user *);
|
||||
extern int vfp_restore_user_hwstate(struct user_vfp __user *,
|
||||
struct user_vfp_exc __user *);
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
@ -7,6 +7,8 @@
|
|||
|
||||
.macro set_tls_v6k, tp, tmp1, tmp2
|
||||
mcr p15, 0, \tp, c13, c0, 3 @ set TLS register
|
||||
mov \tmp1, #0
|
||||
mcr p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register
|
||||
.endm
|
||||
|
||||
.macro set_tls_v6, tp, tmp1, tmp2
|
||||
|
@ -15,6 +17,8 @@
|
|||
mov \tmp2, #0xffff0fff
|
||||
tst \tmp1, #HWCAP_TLS @ hardware TLS available?
|
||||
mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register
|
||||
movne \tmp1, #0
|
||||
mcrne p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register
|
||||
streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0
|
||||
.endm
|
||||
|
||||
|
|
|
@ -155,10 +155,10 @@ static bool migrate_one_irq(struct irq_desc *desc)
|
|||
}
|
||||
|
||||
c = irq_data_get_irq_chip(d);
|
||||
if (c->irq_set_affinity)
|
||||
c->irq_set_affinity(d, affinity, true);
|
||||
else
|
||||
if (!c->irq_set_affinity)
|
||||
pr_debug("IRQ%u: unable to set affinity\n", d->irq);
|
||||
else if (c->irq_set_affinity(d, affinity, true) == IRQ_SET_MASK_OK && ret)
|
||||
cpumask_copy(d->affinity, affinity);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -180,44 +180,23 @@ static int restore_iwmmxt_context(struct iwmmxt_sigframe *frame)
|
|||
|
||||
static int preserve_vfp_context(struct vfp_sigframe __user *frame)
|
||||
{
|
||||
struct thread_info *thread = current_thread_info();
|
||||
struct vfp_hard_struct *h = &thread->vfpstate.hard;
|
||||
const unsigned long magic = VFP_MAGIC;
|
||||
const unsigned long size = VFP_STORAGE_SIZE;
|
||||
int err = 0;
|
||||
|
||||
vfp_sync_hwstate(thread);
|
||||
__put_user_error(magic, &frame->magic, err);
|
||||
__put_user_error(size, &frame->size, err);
|
||||
|
||||
/*
|
||||
* Copy the floating point registers. There can be unused
|
||||
* registers see asm/hwcap.h for details.
|
||||
*/
|
||||
err |= __copy_to_user(&frame->ufp.fpregs, &h->fpregs,
|
||||
sizeof(h->fpregs));
|
||||
/*
|
||||
* Copy the status and control register.
|
||||
*/
|
||||
__put_user_error(h->fpscr, &frame->ufp.fpscr, err);
|
||||
if (err)
|
||||
return -EFAULT;
|
||||
|
||||
/*
|
||||
* Copy the exception registers.
|
||||
*/
|
||||
__put_user_error(h->fpexc, &frame->ufp_exc.fpexc, err);
|
||||
__put_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
|
||||
__put_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
|
||||
|
||||
return err ? -EFAULT : 0;
|
||||
return vfp_preserve_user_clear_hwstate(&frame->ufp, &frame->ufp_exc);
|
||||
}
|
||||
|
||||
static int restore_vfp_context(struct vfp_sigframe __user *frame)
|
||||
{
|
||||
struct thread_info *thread = current_thread_info();
|
||||
struct vfp_hard_struct *h = &thread->vfpstate.hard;
|
||||
unsigned long magic;
|
||||
unsigned long size;
|
||||
unsigned long fpexc;
|
||||
int err = 0;
|
||||
|
||||
__get_user_error(magic, &frame->magic, err);
|
||||
|
@ -228,33 +207,7 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame)
|
|||
if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE)
|
||||
return -EINVAL;
|
||||
|
||||
vfp_flush_hwstate(thread);
|
||||
|
||||
/*
|
||||
* Copy the floating point registers. There can be unused
|
||||
* registers see asm/hwcap.h for details.
|
||||
*/
|
||||
err |= __copy_from_user(&h->fpregs, &frame->ufp.fpregs,
|
||||
sizeof(h->fpregs));
|
||||
/*
|
||||
* Copy the status and control register.
|
||||
*/
|
||||
__get_user_error(h->fpscr, &frame->ufp.fpscr, err);
|
||||
|
||||
/*
|
||||
* Sanitise and restore the exception registers.
|
||||
*/
|
||||
__get_user_error(fpexc, &frame->ufp_exc.fpexc, err);
|
||||
/* Ensure the VFP is enabled. */
|
||||
fpexc |= FPEXC_EN;
|
||||
/* Ensure FPINST2 is invalid and the exception flag is cleared. */
|
||||
fpexc &= ~(FPEXC_EX | FPEXC_FP2V);
|
||||
h->fpexc = fpexc;
|
||||
|
||||
__get_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
|
||||
__get_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
|
||||
|
||||
return err ? -EFAULT : 0;
|
||||
return vfp_restore_user_hwstate(&frame->ufp, &frame->ufp_exc);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -510,10 +510,6 @@ static void ipi_cpu_stop(unsigned int cpu)
|
|||
local_fiq_disable();
|
||||
local_irq_disable();
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
platform_cpu_kill(cpu);
|
||||
#endif
|
||||
|
||||
while (1)
|
||||
cpu_relax();
|
||||
}
|
||||
|
@ -576,17 +572,25 @@ void smp_send_reschedule(int cpu)
|
|||
smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
static void smp_kill_cpus(cpumask_t *mask)
|
||||
{
|
||||
unsigned int cpu;
|
||||
for_each_cpu(cpu, mask)
|
||||
platform_cpu_kill(cpu);
|
||||
}
|
||||
#else
|
||||
static void smp_kill_cpus(cpumask_t *mask) { }
|
||||
#endif
|
||||
|
||||
void smp_send_stop(void)
|
||||
{
|
||||
unsigned long timeout;
|
||||
struct cpumask mask;
|
||||
|
||||
if (num_online_cpus() > 1) {
|
||||
struct cpumask mask;
|
||||
cpumask_copy(&mask, cpu_online_mask);
|
||||
cpumask_clear_cpu(smp_processor_id(), &mask);
|
||||
|
||||
smp_cross_call(&mask, IPI_CPU_STOP);
|
||||
}
|
||||
cpumask_copy(&mask, cpu_online_mask);
|
||||
cpumask_clear_cpu(smp_processor_id(), &mask);
|
||||
smp_cross_call(&mask, IPI_CPU_STOP);
|
||||
|
||||
/* Wait up to one second for other CPUs to stop */
|
||||
timeout = USEC_PER_SEC;
|
||||
|
@ -595,6 +599,8 @@ void smp_send_stop(void)
|
|||
|
||||
if (num_online_cpus() > 1)
|
||||
pr_warning("SMP: failed to stop secondary CPUs\n");
|
||||
|
||||
smp_kill_cpus(&mask);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -118,14 +118,10 @@ static int twd_cpufreq_transition(struct notifier_block *nb,
|
|||
* The twd clock events must be reprogrammed to account for the new
|
||||
* frequency. The timer is local to a cpu, so cross-call to the
|
||||
* changing cpu.
|
||||
*
|
||||
* Only wait for it to finish, if the cpu is active to avoid
|
||||
* deadlock when cpu1 is spinning on while(!cpu_active(cpu1)) during
|
||||
* booting of that cpu.
|
||||
*/
|
||||
if (state == CPUFREQ_POSTCHANGE || state == CPUFREQ_RESUMECHANGE)
|
||||
smp_call_function_single(freqs->cpu, twd_update_frequency,
|
||||
NULL, cpu_active(freqs->cpu));
|
||||
NULL, 1);
|
||||
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
|
|
@ -1173,7 +1173,6 @@ void __init at91_add_device_serial(void)
|
|||
printk(KERN_INFO "AT91: No default serial console defined.\n");
|
||||
}
|
||||
#else
|
||||
void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
|
||||
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
|
||||
void __init at91_set_serial_console(unsigned portnr) {}
|
||||
void __init at91_add_device_serial(void) {}
|
||||
|
|
|
@ -23,6 +23,7 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/export.h>
|
||||
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
|
@ -176,6 +177,7 @@ static struct clock_event_device clkevt = {
|
|||
};
|
||||
|
||||
void __iomem *at91_st_base;
|
||||
EXPORT_SYMBOL_GPL(at91_st_base);
|
||||
|
||||
void __init at91rm9200_ioremap_st(u32 addr)
|
||||
{
|
||||
|
|
|
@ -117,7 +117,7 @@ static struct i2c_board_info __initdata ek_i2c_devices[] = {
|
|||
};
|
||||
|
||||
#define EK_FLASH_BASE AT91_CHIPSELECT_0
|
||||
#define EK_FLASH_SIZE SZ_2M
|
||||
#define EK_FLASH_SIZE SZ_8M
|
||||
|
||||
static struct physmap_flash_data ek_flash_data = {
|
||||
.width = 2,
|
||||
|
|
|
@ -85,8 +85,6 @@ static struct resource dm9000_resource[] = {
|
|||
.flags = IORESOURCE_MEM
|
||||
},
|
||||
[2] = {
|
||||
.start = AT91_PIN_PC11,
|
||||
.end = AT91_PIN_PC11,
|
||||
.flags = IORESOURCE_IRQ
|
||||
| IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE,
|
||||
}
|
||||
|
@ -130,6 +128,8 @@ static struct sam9_smc_config __initdata dm9000_smc_config = {
|
|||
|
||||
static void __init ek_add_device_dm9000(void)
|
||||
{
|
||||
struct resource *r = &dm9000_resource[2];
|
||||
|
||||
/* Configure chip-select 2 (DM9000) */
|
||||
sam9_smc_configure(0, 2, &dm9000_smc_config);
|
||||
|
||||
|
@ -139,6 +139,7 @@ static void __init ek_add_device_dm9000(void)
|
|||
/* Configure Interrupt pin as input, no pull-up */
|
||||
at91_set_gpio_input(AT91_PIN_PC11, 0);
|
||||
|
||||
r->start = r->end = gpio_to_irq(AT91_PIN_PC11);
|
||||
platform_device_register(&dm9000_device);
|
||||
}
|
||||
#else
|
||||
|
|
|
@ -35,6 +35,7 @@
|
|||
#include "generic.h"
|
||||
|
||||
void __iomem *at91_pmc_base;
|
||||
EXPORT_SYMBOL_GPL(at91_pmc_base);
|
||||
|
||||
/*
|
||||
* There's a lot more which can be done with clocks, including cpufreq
|
||||
|
|
|
@ -25,7 +25,7 @@ extern void __iomem *at91_pmc_base;
|
|||
#define at91_pmc_write(field, value) \
|
||||
__raw_writel(value, at91_pmc_base + field)
|
||||
#else
|
||||
.extern at91_aic_base
|
||||
.extern at91_pmc_base
|
||||
#endif
|
||||
|
||||
#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
|
||||
|
|
|
@ -54,6 +54,7 @@ void __init at91_init_interrupts(unsigned int *priority)
|
|||
}
|
||||
|
||||
void __iomem *at91_ramc_base[2];
|
||||
EXPORT_SYMBOL_GPL(at91_ramc_base);
|
||||
|
||||
void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
|
||||
{
|
||||
|
@ -292,6 +293,7 @@ void __init at91_ioremap_rstc(u32 base_addr)
|
|||
}
|
||||
|
||||
void __iomem *at91_matrix_base;
|
||||
EXPORT_SYMBOL_GPL(at91_matrix_base);
|
||||
|
||||
void __init at91_ioremap_matrix(u32 base_addr)
|
||||
{
|
||||
|
|
|
@ -52,8 +52,8 @@
|
|||
#include <mach/csp/chipcHw_inline.h>
|
||||
#include <mach/csp/tmrHw_reg.h>
|
||||
|
||||
static AMBA_APB_DEVICE(uartA, "uarta", MM_ADDR_IO_UARTA, { IRQ_UARTA }, NULL);
|
||||
static AMBA_APB_DEVICE(uartB, "uartb", MM_ADDR_IO_UARTB, { IRQ_UARTB }, NULL);
|
||||
static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL);
|
||||
static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL);
|
||||
|
||||
static struct clk pll1_clk = {
|
||||
.name = "PLL1",
|
||||
|
|
|
@ -497,25 +497,25 @@ static struct clk exynos4_init_clocks_off[] = {
|
|||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.0",
|
||||
.devname = "exynos4-sdhci.0",
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 5),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.1",
|
||||
.devname = "exynos4-sdhci.1",
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 6),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.2",
|
||||
.devname = "exynos4-sdhci.2",
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 7),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.3",
|
||||
.devname = "exynos4-sdhci.3",
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
|
@ -1202,7 +1202,7 @@ static struct clksrc_clk exynos4_clk_sclk_uart3 = {
|
|||
static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.0",
|
||||
.devname = "exynos4-sdhci.0",
|
||||
.parent = &exynos4_clk_dout_mmc0.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
|
@ -1213,7 +1213,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
|
|||
static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.1",
|
||||
.devname = "exynos4-sdhci.1",
|
||||
.parent = &exynos4_clk_dout_mmc1.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
|
@ -1224,7 +1224,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
|
|||
static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.2",
|
||||
.devname = "exynos4-sdhci.2",
|
||||
.parent = &exynos4_clk_dout_mmc2.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
|
@ -1235,7 +1235,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
|
|||
static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.3",
|
||||
.devname = "exynos4-sdhci.3",
|
||||
.parent = &exynos4_clk_dout_mmc3.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
|
@ -1340,10 +1340,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
|
|||
CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
|
||||
CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
|
||||
CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
|
||||
CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
|
||||
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
|
||||
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
|
||||
|
|
|
@ -455,25 +455,25 @@ static struct clk exynos5_init_clocks_off[] = {
|
|||
.ctrlbit = (1 << 20),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.0",
|
||||
.devname = "exynos4-sdhci.0",
|
||||
.parent = &exynos5_clk_aclk_200.clk,
|
||||
.enable = exynos5_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.1",
|
||||
.devname = "exynos4-sdhci.1",
|
||||
.parent = &exynos5_clk_aclk_200.clk,
|
||||
.enable = exynos5_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 13),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.2",
|
||||
.devname = "exynos4-sdhci.2",
|
||||
.parent = &exynos5_clk_aclk_200.clk,
|
||||
.enable = exynos5_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 14),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.3",
|
||||
.devname = "exynos4-sdhci.3",
|
||||
.parent = &exynos5_clk_aclk_200.clk,
|
||||
.enable = exynos5_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 15),
|
||||
|
@ -813,7 +813,7 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
|
|||
static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.0",
|
||||
.devname = "exynos4-sdhci.0",
|
||||
.parent = &exynos5_clk_dout_mmc0.clk,
|
||||
.enable = exynos5_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
|
@ -824,7 +824,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
|
|||
static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.1",
|
||||
.devname = "exynos4-sdhci.1",
|
||||
.parent = &exynos5_clk_dout_mmc1.clk,
|
||||
.enable = exynos5_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
|
@ -835,7 +835,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
|
|||
static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.2",
|
||||
.devname = "exynos4-sdhci.2",
|
||||
.parent = &exynos5_clk_dout_mmc2.clk,
|
||||
.enable = exynos5_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
|
@ -846,7 +846,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
|
|||
static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.3",
|
||||
.devname = "exynos4-sdhci.3",
|
||||
.parent = &exynos5_clk_dout_mmc3.clk,
|
||||
.enable = exynos5_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
|
@ -990,10 +990,10 @@ static struct clk_lookup exynos5_clk_lookup[] = {
|
|||
CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
|
||||
CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
|
||||
CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
|
||||
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
|
||||
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
|
||||
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
|
||||
|
|
|
@ -326,6 +326,11 @@ static void __init exynos4_map_io(void)
|
|||
s3c_fimc_setname(2, "exynos4-fimc");
|
||||
s3c_fimc_setname(3, "exynos4-fimc");
|
||||
|
||||
s3c_sdhci_setname(0, "exynos4-sdhci");
|
||||
s3c_sdhci_setname(1, "exynos4-sdhci");
|
||||
s3c_sdhci_setname(2, "exynos4-sdhci");
|
||||
s3c_sdhci_setname(3, "exynos4-sdhci");
|
||||
|
||||
/* The I2C bus controllers are directly compatible with s3c2440 */
|
||||
s3c_i2c0_setname("s3c2440-i2c");
|
||||
s3c_i2c1_setname("s3c2440-i2c");
|
||||
|
@ -344,6 +349,11 @@ static void __init exynos5_map_io(void)
|
|||
s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
|
||||
s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
|
||||
|
||||
s3c_sdhci_setname(0, "exynos4-sdhci");
|
||||
s3c_sdhci_setname(1, "exynos4-sdhci");
|
||||
s3c_sdhci_setname(2, "exynos4-sdhci");
|
||||
s3c_sdhci_setname(3, "exynos4-sdhci");
|
||||
|
||||
/* The I2C bus controllers are directly compatible with s3c2440 */
|
||||
s3c_i2c0_setname("s3c2440-i2c");
|
||||
s3c_i2c1_setname("s3c2440-i2c");
|
||||
|
@ -537,7 +547,9 @@ void __init exynos5_init_irq(void)
|
|||
{
|
||||
int irq;
|
||||
|
||||
gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
|
||||
#ifdef CONFIG_OF
|
||||
of_irq_init(exynos4_dt_irq_match);
|
||||
#endif
|
||||
|
||||
for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
|
||||
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
#include <linux/dma-mapping.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/mmc/dw_mmc.h>
|
||||
|
||||
#include <plat/devs.h>
|
||||
|
@ -33,16 +34,8 @@ static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
|
|||
}
|
||||
|
||||
static struct resource exynos4_dwmci_resource[] = {
|
||||
[0] = {
|
||||
.start = EXYNOS4_PA_DWMCI,
|
||||
.end = EXYNOS4_PA_DWMCI + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_DWMCI,
|
||||
.end = IRQ_DWMCI,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_DWMCI, SZ_4K),
|
||||
[1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_DWMCI),
|
||||
};
|
||||
|
||||
static struct dw_mci_board exynos4_dwci_pdata = {
|
||||
|
|
|
@ -112,6 +112,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
|
|||
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
|
||||
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
|
||||
MMC_CAP_ERASE),
|
||||
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
|
||||
.cd_type = S3C_SDHCI_CD_PERMANENT,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
|
|
@ -747,6 +747,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
|
|||
.max_width = 8,
|
||||
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
|
||||
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
|
||||
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
|
||||
.cd_type = S3C_SDHCI_CD_PERMANENT,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
|
|
@ -35,7 +35,7 @@ static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
|
|||
static int __init imx27_avic_add_irq_domain(struct device_node *np,
|
||||
struct device_node *interrupt_parent)
|
||||
{
|
||||
irq_domain_add_simple(np, 0);
|
||||
irq_domain_add_legacy(np, 64, 0, 0, &irq_domain_simple_ops, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -44,7 +44,9 @@ static int __init imx27_gpio_add_irq_domain(struct device_node *np,
|
|||
{
|
||||
static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
|
||||
|
||||
irq_domain_add_simple(np, gpio_irq_base);
|
||||
gpio_irq_base -= 32;
|
||||
irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops,
|
||||
NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -35,7 +35,7 @@ static void imx5_idle(void)
|
|||
}
|
||||
clk_enable(gpc_dvfs_clk);
|
||||
mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
|
||||
if (tzic_enable_wake() != 0)
|
||||
if (!tzic_enable_wake())
|
||||
cpu_do_idle();
|
||||
clk_disable(gpc_dvfs_clk);
|
||||
}
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/irqdomain.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/memblock.h>
|
||||
|
||||
|
@ -49,10 +50,22 @@ static void __init msm8x60_map_io(void)
|
|||
msm_map_msm8x60_io();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static struct of_device_id msm_dt_gic_match[] __initdata = {
|
||||
{ .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
|
||||
{}
|
||||
};
|
||||
#endif
|
||||
|
||||
static void __init msm8x60_init_irq(void)
|
||||
{
|
||||
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
|
||||
(void *)MSM_QGIC_CPU_BASE);
|
||||
if (!of_have_populated_dt())
|
||||
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
|
||||
(void *)MSM_QGIC_CPU_BASE);
|
||||
#ifdef CONFIG_OF
|
||||
else
|
||||
of_irq_init(msm_dt_gic_match);
|
||||
#endif
|
||||
|
||||
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
|
||||
writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
|
||||
|
@ -73,16 +86,8 @@ static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
|
|||
{}
|
||||
};
|
||||
|
||||
static struct of_device_id msm_dt_gic_match[] __initdata = {
|
||||
{ .compatible = "qcom,msm-8660-qgic", },
|
||||
{}
|
||||
};
|
||||
|
||||
static void __init msm8x60_dt_init(void)
|
||||
{
|
||||
irq_domain_generate_simple(msm_dt_gic_match, MSM8X60_QGIC_DIST_PHYS,
|
||||
GIC_SPI_START);
|
||||
|
||||
if (of_machine_is_compatible("qcom,msm8660-surf")) {
|
||||
printk(KERN_INFO "Init surf UART registers\n");
|
||||
msm8x60_init_uart12dm();
|
||||
|
|
|
@ -27,6 +27,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#include <plat/mux.h>
|
||||
|
||||
|
|
|
@ -47,9 +47,9 @@ static int omap1_dm_timer_set_src(struct platform_device *pdev,
|
|||
int n = (pdev->id - 1) << 1;
|
||||
u32 l;
|
||||
|
||||
l = __raw_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
|
||||
l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
|
||||
l |= source << n;
|
||||
__raw_writel(l, MOD_CONF_CTRL_1);
|
||||
omap_writel(l, MOD_CONF_CTRL_1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -20,6 +20,7 @@
|
|||
#include <linux/usb/otg.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/i2c/twl.h>
|
||||
#include <linux/mfd/twl6040.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
|
@ -560,7 +561,7 @@ static struct regulator_init_data sdp4430_vusim = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct twl4030_codec_data twl6040_codec = {
|
||||
static struct twl6040_codec_data twl6040_codec = {
|
||||
/* single-step ramp for headset and handsfree */
|
||||
.hs_left_step = 0x0f,
|
||||
.hs_right_step = 0x0f,
|
||||
|
@ -568,7 +569,7 @@ static struct twl4030_codec_data twl6040_codec = {
|
|||
.hf_right_step = 0x1d,
|
||||
};
|
||||
|
||||
static struct twl4030_vibra_data twl6040_vibra = {
|
||||
static struct twl6040_vibra_data twl6040_vibra = {
|
||||
.vibldrv_res = 8,
|
||||
.vibrdrv_res = 3,
|
||||
.viblmotor_res = 10,
|
||||
|
@ -577,16 +578,14 @@ static struct twl4030_vibra_data twl6040_vibra = {
|
|||
.vddvibr_uV = 0, /* fixed volt supply - VBAT */
|
||||
};
|
||||
|
||||
static struct twl4030_audio_data twl6040_audio = {
|
||||
static struct twl6040_platform_data twl6040_data = {
|
||||
.codec = &twl6040_codec,
|
||||
.vibra = &twl6040_vibra,
|
||||
.audpwron_gpio = 127,
|
||||
.naudint_irq = OMAP44XX_IRQ_SYS_2N,
|
||||
.irq_base = TWL6040_CODEC_IRQ_BASE,
|
||||
};
|
||||
|
||||
static struct twl4030_platform_data sdp4430_twldata = {
|
||||
.audio = &twl6040_audio,
|
||||
/* Regulators */
|
||||
.vusim = &sdp4430_vusim,
|
||||
.vaux1 = &sdp4430_vaux1,
|
||||
|
@ -617,7 +616,8 @@ static int __init omap4_i2c_init(void)
|
|||
TWL_COMMON_REGULATOR_VCXIO |
|
||||
TWL_COMMON_REGULATOR_VUSB |
|
||||
TWL_COMMON_REGULATOR_CLK32KG);
|
||||
omap4_pmic_init("twl6030", &sdp4430_twldata);
|
||||
omap4_pmic_init("twl6030", &sdp4430_twldata,
|
||||
&twl6040_data, OMAP44XX_IRQ_SYS_2N);
|
||||
omap_register_i2c_bus(2, 400, NULL, 0);
|
||||
omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
|
||||
ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
|
||||
|
|
|
@ -137,7 +137,7 @@ static struct twl4030_platform_data sdp4430_twldata = {
|
|||
|
||||
static void __init omap4_i2c_init(void)
|
||||
{
|
||||
omap4_pmic_init("twl6030", &sdp4430_twldata);
|
||||
omap4_pmic_init("twl6030", &sdp4430_twldata, NULL, 0);
|
||||
}
|
||||
|
||||
static void __init omap4_init(void)
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
#include <linux/gpio.h>
|
||||
#include <linux/usb/otg.h>
|
||||
#include <linux/i2c/twl.h>
|
||||
#include <linux/mfd/twl6040.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/wl12xx.h>
|
||||
|
@ -284,7 +285,7 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct twl4030_codec_data twl6040_codec = {
|
||||
static struct twl6040_codec_data twl6040_codec = {
|
||||
/* single-step ramp for headset and handsfree */
|
||||
.hs_left_step = 0x0f,
|
||||
.hs_right_step = 0x0f,
|
||||
|
@ -292,17 +293,14 @@ static struct twl4030_codec_data twl6040_codec = {
|
|||
.hf_right_step = 0x1d,
|
||||
};
|
||||
|
||||
static struct twl4030_audio_data twl6040_audio = {
|
||||
static struct twl6040_platform_data twl6040_data = {
|
||||
.codec = &twl6040_codec,
|
||||
.audpwron_gpio = 127,
|
||||
.naudint_irq = OMAP44XX_IRQ_SYS_2N,
|
||||
.irq_base = TWL6040_CODEC_IRQ_BASE,
|
||||
};
|
||||
|
||||
/* Panda board uses the common PMIC configuration */
|
||||
static struct twl4030_platform_data omap4_panda_twldata = {
|
||||
.audio = &twl6040_audio,
|
||||
};
|
||||
static struct twl4030_platform_data omap4_panda_twldata;
|
||||
|
||||
/*
|
||||
* Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
|
||||
|
@ -326,7 +324,8 @@ static int __init omap4_panda_i2c_init(void)
|
|||
TWL_COMMON_REGULATOR_VCXIO |
|
||||
TWL_COMMON_REGULATOR_VUSB |
|
||||
TWL_COMMON_REGULATOR_CLK32KG);
|
||||
omap4_pmic_init("twl6030", &omap4_panda_twldata);
|
||||
omap4_pmic_init("twl6030", &omap4_panda_twldata,
|
||||
&twl6040_data, OMAP44XX_IRQ_SYS_2N);
|
||||
omap_register_i2c_bus(2, 400, NULL, 0);
|
||||
/*
|
||||
* Bus 3 is attached to the DVI port where devices like the pico DLP
|
||||
|
|
|
@ -1422,6 +1422,9 @@ static int _ocp_softreset(struct omap_hwmod *oh)
|
|||
goto dis_opt_clks;
|
||||
_write_sysconfig(v, oh);
|
||||
|
||||
if (oh->class->sysc->srst_udelay)
|
||||
udelay(oh->class->sysc->srst_udelay);
|
||||
|
||||
if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
|
||||
omap_test_timeout((omap_hwmod_read(oh,
|
||||
oh->class->sysc->syss_offs)
|
||||
|
@ -1903,10 +1906,20 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
|
|||
*/
|
||||
int omap_hwmod_softreset(struct omap_hwmod *oh)
|
||||
{
|
||||
if (!oh)
|
||||
u32 v;
|
||||
int ret;
|
||||
|
||||
if (!oh || !(oh->_sysc_cache))
|
||||
return -EINVAL;
|
||||
|
||||
return _ocp_softreset(oh);
|
||||
v = oh->_sysc_cache;
|
||||
ret = _set_softreset(oh, &v);
|
||||
if (ret)
|
||||
goto error;
|
||||
_write_sysconfig(v, oh);
|
||||
|
||||
error:
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -1000,7 +1000,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
|
|||
.flags = OMAP_FIREWALL_L4,
|
||||
}
|
||||
},
|
||||
.flags = OCPIF_SWSUP_IDLE,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
|
@ -1049,7 +1049,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
|
|||
.slave = &omap2430_dss_venc_hwmod,
|
||||
.clk = "dss_ick",
|
||||
.addr = omap2_dss_venc_addrs,
|
||||
.flags = OCPIF_SWSUP_IDLE,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
|
@ -1676,7 +1676,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
|
|||
.flags = OMAP_FIREWALL_L4,
|
||||
}
|
||||
},
|
||||
.flags = OCPIF_SWSUP_IDLE,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
|
|
@ -2594,6 +2594,15 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
|
|||
static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x0010,
|
||||
/*
|
||||
* ISS needs 100 OCP clk cycles delay after a softreset before
|
||||
* accessing sysconfig again.
|
||||
* The lowest frequency at the moment for L3 bus is 100 MHz, so
|
||||
* 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
|
||||
*
|
||||
* TODO: Indicate errata when available.
|
||||
*/
|
||||
.srst_udelay = 2,
|
||||
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
|
||||
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
||||
|
|
|
@ -108,8 +108,14 @@ static void omap_uart_set_noidle(struct platform_device *pdev)
|
|||
static void omap_uart_set_smartidle(struct platform_device *pdev)
|
||||
{
|
||||
struct omap_device *od = to_omap_device(pdev);
|
||||
u8 idlemode;
|
||||
|
||||
omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_SMART);
|
||||
if (od->hwmods[0]->class->sysc->idlemodes & SIDLE_SMART_WKUP)
|
||||
idlemode = HWMOD_IDLEMODE_SMART_WKUP;
|
||||
else
|
||||
idlemode = HWMOD_IDLEMODE_SMART;
|
||||
|
||||
omap_hwmod_set_slave_idlemode(od->hwmods[0], idlemode);
|
||||
}
|
||||
|
||||
#else
|
||||
|
@ -120,124 +126,8 @@ static void omap_uart_set_smartidle(struct platform_device *pdev) {}
|
|||
#endif /* CONFIG_PM */
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_device_pad default_uart1_pads[] __initdata = {
|
||||
{
|
||||
.name = "uart1_cts.uart1_cts",
|
||||
.enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
|
||||
},
|
||||
{
|
||||
.name = "uart1_rts.uart1_rts",
|
||||
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
|
||||
},
|
||||
{
|
||||
.name = "uart1_tx.uart1_tx",
|
||||
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
|
||||
},
|
||||
{
|
||||
.name = "uart1_rx.uart1_rx",
|
||||
.flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
|
||||
.enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
|
||||
.idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_device_pad default_uart2_pads[] __initdata = {
|
||||
{
|
||||
.name = "uart2_cts.uart2_cts",
|
||||
.enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
|
||||
},
|
||||
{
|
||||
.name = "uart2_rts.uart2_rts",
|
||||
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
|
||||
},
|
||||
{
|
||||
.name = "uart2_tx.uart2_tx",
|
||||
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
|
||||
},
|
||||
{
|
||||
.name = "uart2_rx.uart2_rx",
|
||||
.flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
|
||||
.enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
|
||||
.idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_device_pad default_uart3_pads[] __initdata = {
|
||||
{
|
||||
.name = "uart3_cts_rctx.uart3_cts_rctx",
|
||||
.enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
|
||||
},
|
||||
{
|
||||
.name = "uart3_rts_sd.uart3_rts_sd",
|
||||
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
|
||||
},
|
||||
{
|
||||
.name = "uart3_tx_irtx.uart3_tx_irtx",
|
||||
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
|
||||
},
|
||||
{
|
||||
.name = "uart3_rx_irrx.uart3_rx_irrx",
|
||||
.flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
|
||||
.enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
|
||||
.idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = {
|
||||
{
|
||||
.name = "gpmc_wait2.uart4_tx",
|
||||
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
|
||||
},
|
||||
{
|
||||
.name = "gpmc_wait3.uart4_rx",
|
||||
.flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
|
||||
.enable = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
|
||||
.idle = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_device_pad default_omap4_uart4_pads[] __initdata = {
|
||||
{
|
||||
.name = "uart4_tx.uart4_tx",
|
||||
.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
|
||||
},
|
||||
{
|
||||
.name = "uart4_rx.uart4_rx",
|
||||
.flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
|
||||
.enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
|
||||
.idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
|
||||
},
|
||||
};
|
||||
|
||||
static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
|
||||
{
|
||||
switch (bdata->id) {
|
||||
case 0:
|
||||
bdata->pads = default_uart1_pads;
|
||||
bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads);
|
||||
break;
|
||||
case 1:
|
||||
bdata->pads = default_uart2_pads;
|
||||
bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads);
|
||||
break;
|
||||
case 2:
|
||||
bdata->pads = default_uart3_pads;
|
||||
bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads);
|
||||
break;
|
||||
case 3:
|
||||
if (cpu_is_omap44xx()) {
|
||||
bdata->pads = default_omap4_uart4_pads;
|
||||
bdata->pads_cnt =
|
||||
ARRAY_SIZE(default_omap4_uart4_pads);
|
||||
} else if (cpu_is_omap3630()) {
|
||||
bdata->pads = default_omap36xx_uart4_pads;
|
||||
bdata->pads_cnt =
|
||||
ARRAY_SIZE(default_omap36xx_uart4_pads);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
#else
|
||||
static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
|
||||
|
|
|
@ -37,6 +37,16 @@ static struct i2c_board_info __initdata pmic_i2c_board_info = {
|
|||
.flags = I2C_CLIENT_WAKE,
|
||||
};
|
||||
|
||||
static struct i2c_board_info __initdata omap4_i2c1_board_info[] = {
|
||||
{
|
||||
.addr = 0x48,
|
||||
.flags = I2C_CLIENT_WAKE,
|
||||
},
|
||||
{
|
||||
I2C_BOARD_INFO("twl6040", 0x4b),
|
||||
},
|
||||
};
|
||||
|
||||
void __init omap_pmic_init(int bus, u32 clkrate,
|
||||
const char *pmic_type, int pmic_irq,
|
||||
struct twl4030_platform_data *pmic_data)
|
||||
|
@ -49,14 +59,31 @@ void __init omap_pmic_init(int bus, u32 clkrate,
|
|||
omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
|
||||
}
|
||||
|
||||
void __init omap4_pmic_init(const char *pmic_type,
|
||||
struct twl4030_platform_data *pmic_data,
|
||||
struct twl6040_platform_data *twl6040_data, int twl6040_irq)
|
||||
{
|
||||
/* PMIC part*/
|
||||
strncpy(omap4_i2c1_board_info[0].type, pmic_type,
|
||||
sizeof(omap4_i2c1_board_info[0].type));
|
||||
omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N;
|
||||
omap4_i2c1_board_info[0].platform_data = pmic_data;
|
||||
|
||||
/* TWL6040 audio IC part */
|
||||
omap4_i2c1_board_info[1].irq = twl6040_irq;
|
||||
omap4_i2c1_board_info[1].platform_data = twl6040_data;
|
||||
|
||||
omap_register_i2c_bus(1, 400, omap4_i2c1_board_info, 2);
|
||||
|
||||
}
|
||||
|
||||
void __init omap_pmic_late_init(void)
|
||||
{
|
||||
/* Init the OMAP TWL parameters (if PMIC has been registerd) */
|
||||
if (!pmic_i2c_board_info.irq)
|
||||
return;
|
||||
|
||||
omap3_twl_init();
|
||||
omap4_twl_init();
|
||||
if (pmic_i2c_board_info.irq)
|
||||
omap3_twl_init();
|
||||
if (omap4_i2c1_board_info[0].irq)
|
||||
omap4_twl_init();
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP3)
|
||||
|
|
|
@ -29,6 +29,7 @@
|
|||
|
||||
|
||||
struct twl4030_platform_data;
|
||||
struct twl6040_platform_data;
|
||||
|
||||
void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
|
||||
struct twl4030_platform_data *pmic_data);
|
||||
|
@ -46,12 +47,9 @@ static inline void omap3_pmic_init(const char *pmic_type,
|
|||
omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
|
||||
}
|
||||
|
||||
static inline void omap4_pmic_init(const char *pmic_type,
|
||||
struct twl4030_platform_data *pmic_data)
|
||||
{
|
||||
/* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */
|
||||
omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
|
||||
}
|
||||
void omap4_pmic_init(const char *pmic_type,
|
||||
struct twl4030_platform_data *pmic_data,
|
||||
struct twl6040_platform_data *audio_data, int twl6040_irq);
|
||||
|
||||
void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
|
||||
u32 pdata_flags, u32 regulators_flags);
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
*
|
||||
* bit 23 - Input/Output (PXA2xx specific)
|
||||
* bit 24 - Wakeup Enable(PXA2xx specific)
|
||||
* bit 25 - Keep Output (PXA2xx specific)
|
||||
*/
|
||||
|
||||
#define MFP_DIR_IN (0x0 << 23)
|
||||
|
@ -25,6 +26,12 @@
|
|||
#define MFP_DIR(x) (((x) >> 23) & 0x1)
|
||||
|
||||
#define MFP_LPM_CAN_WAKEUP (0x1 << 24)
|
||||
|
||||
/*
|
||||
* MFP_LPM_KEEP_OUTPUT must be specified for pins that need to
|
||||
* retain their last output level (low or high).
|
||||
* Note: MFP_LPM_KEEP_OUTPUT has no effect on pins configured for input.
|
||||
*/
|
||||
#define MFP_LPM_KEEP_OUTPUT (0x1 << 25)
|
||||
|
||||
#define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)
|
||||
|
|
|
@ -33,6 +33,8 @@
|
|||
#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
|
||||
#define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5))
|
||||
#define GPDR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c)
|
||||
#define GPSR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x18)
|
||||
#define GPCR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24)
|
||||
|
||||
#define PWER_WE35 (1 << 24)
|
||||
|
||||
|
@ -348,6 +350,7 @@ static inline void pxa27x_mfp_init(void) {}
|
|||
#ifdef CONFIG_PM
|
||||
static unsigned long saved_gafr[2][4];
|
||||
static unsigned long saved_gpdr[4];
|
||||
static unsigned long saved_gplr[4];
|
||||
static unsigned long saved_pgsr[4];
|
||||
|
||||
static int pxa2xx_mfp_suspend(void)
|
||||
|
@ -366,14 +369,26 @@ static int pxa2xx_mfp_suspend(void)
|
|||
}
|
||||
|
||||
for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
|
||||
|
||||
saved_gafr[0][i] = GAFR_L(i);
|
||||
saved_gafr[1][i] = GAFR_U(i);
|
||||
saved_gpdr[i] = GPDR(i * 32);
|
||||
saved_gplr[i] = GPLR(i * 32);
|
||||
saved_pgsr[i] = PGSR(i);
|
||||
|
||||
GPDR(i * 32) = gpdr_lpm[i];
|
||||
GPSR(i * 32) = PGSR(i);
|
||||
GPCR(i * 32) = ~PGSR(i);
|
||||
}
|
||||
|
||||
/* set GPDR bits taking into account MFP_LPM_KEEP_OUTPUT */
|
||||
for (i = 0; i < pxa_last_gpio; i++) {
|
||||
if ((gpdr_lpm[gpio_to_bank(i)] & GPIO_bit(i)) ||
|
||||
((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
|
||||
(saved_gpdr[gpio_to_bank(i)] & GPIO_bit(i))))
|
||||
GPDR(i) |= GPIO_bit(i);
|
||||
else
|
||||
GPDR(i) &= ~GPIO_bit(i);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -384,6 +399,8 @@ static void pxa2xx_mfp_resume(void)
|
|||
for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
|
||||
GAFR_L(i) = saved_gafr[0][i];
|
||||
GAFR_U(i) = saved_gafr[1][i];
|
||||
GPSR(i * 32) = saved_gplr[i];
|
||||
GPCR(i * 32) = ~saved_gplr[i];
|
||||
GPDR(i * 32) = saved_gpdr[i];
|
||||
PGSR(i) = saved_pgsr[i];
|
||||
}
|
||||
|
|
|
@ -421,8 +421,11 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
|
|||
pxa_register_device(&pxa27x_device_i2c_power, info);
|
||||
}
|
||||
|
||||
static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
|
||||
.gpio_set_wake = gpio_set_wake,
|
||||
};
|
||||
|
||||
static struct platform_device *devices[] __initdata = {
|
||||
&pxa_device_gpio,
|
||||
&pxa27x_device_udc,
|
||||
&pxa_device_pmu,
|
||||
&pxa_device_i2s,
|
||||
|
@ -458,6 +461,7 @@ static int __init pxa27x_init(void)
|
|||
register_syscore_ops(&pxa2xx_mfp_syscore_ops);
|
||||
register_syscore_ops(&pxa2xx_clock_syscore_ops);
|
||||
|
||||
pxa_register_device(&pxa_device_gpio, &pxa27x_gpio_info);
|
||||
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
}
|
||||
|
||||
|
|
|
@ -111,10 +111,6 @@ config S3C24XX_SETUP_TS
|
|||
help
|
||||
Compile in platform device definition for Samsung TouchScreen.
|
||||
|
||||
# cpu-specific sections
|
||||
|
||||
if CPU_S3C2410
|
||||
|
||||
config S3C2410_DMA
|
||||
bool
|
||||
depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
|
||||
|
@ -127,6 +123,10 @@ config S3C2410_PM
|
|||
help
|
||||
Power Management code common to S3C2410 and better
|
||||
|
||||
# cpu-specific sections
|
||||
|
||||
if CPU_S3C2410
|
||||
|
||||
config S3C24XX_SIMTEC_NOR
|
||||
bool
|
||||
help
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
#include <linux/gpio_keys.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
|
@ -765,6 +766,7 @@ static void __init goni_pmic_init(void)
|
|||
/* MoviNAND */
|
||||
static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = {
|
||||
.max_width = 4,
|
||||
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
|
||||
.cd_type = S3C_SDHCI_CD_PERMANENT,
|
||||
};
|
||||
|
||||
|
|
|
@ -306,7 +306,7 @@ void sa11x0_register_irda(struct irda_platform_data *irda)
|
|||
}
|
||||
|
||||
static struct resource sa1100_rtc_resources[] = {
|
||||
DEFINE_RES_MEM(0x90010000, 0x9001003f),
|
||||
DEFINE_RES_MEM(0x90010000, 0x40),
|
||||
DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
|
||||
DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
|
||||
};
|
||||
|
|
|
@ -1667,8 +1667,10 @@ void __init u300_init_irq(void)
|
|||
|
||||
for (i = 0; i < U300_VIC_IRQS_END; i++)
|
||||
set_bit(i, (unsigned long *) &mask[0]);
|
||||
vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
|
||||
vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
|
||||
vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
|
||||
mask[0], mask[0]);
|
||||
vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
|
||||
mask[1], mask[1]);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -146,9 +146,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
|
|||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.valid_ops_mask =
|
||||
REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_STATUS,
|
||||
.always_on = 1,
|
||||
.boot_on = 1,
|
||||
},
|
||||
|
@ -160,9 +157,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
|
|||
.min_uV = 2500000,
|
||||
.max_uV = 2500000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.valid_ops_mask =
|
||||
REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_STATUS,
|
||||
.always_on = 1,
|
||||
.boot_on = 1,
|
||||
},
|
||||
|
@ -230,8 +224,7 @@ static struct ab3100_platform_data ab3100_plf_data = {
|
|||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.valid_ops_mask =
|
||||
REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_STATUS,
|
||||
REGULATOR_CHANGE_VOLTAGE,
|
||||
.always_on = 1,
|
||||
.boot_on = 1,
|
||||
},
|
||||
|
|
|
@ -12,101 +12,101 @@
|
|||
#ifndef __MACH_IRQS_H
|
||||
#define __MACH_IRQS_H
|
||||
|
||||
#define IRQ_U300_INTCON0_START 0
|
||||
#define IRQ_U300_INTCON1_START 32
|
||||
#define IRQ_U300_INTCON0_START 1
|
||||
#define IRQ_U300_INTCON1_START 33
|
||||
/* These are on INTCON0 - 30 lines */
|
||||
#define IRQ_U300_IRQ0_EXT 0
|
||||
#define IRQ_U300_IRQ1_EXT 1
|
||||
#define IRQ_U300_DMA 2
|
||||
#define IRQ_U300_VIDEO_ENC_0 3
|
||||
#define IRQ_U300_VIDEO_ENC_1 4
|
||||
#define IRQ_U300_AAIF_RX 5
|
||||
#define IRQ_U300_AAIF_TX 6
|
||||
#define IRQ_U300_AAIF_VGPIO 7
|
||||
#define IRQ_U300_AAIF_WAKEUP 8
|
||||
#define IRQ_U300_PCM_I2S0_FRAME 9
|
||||
#define IRQ_U300_PCM_I2S0_FIFO 10
|
||||
#define IRQ_U300_PCM_I2S1_FRAME 11
|
||||
#define IRQ_U300_PCM_I2S1_FIFO 12
|
||||
#define IRQ_U300_XGAM_GAMCON 13
|
||||
#define IRQ_U300_XGAM_CDI 14
|
||||
#define IRQ_U300_XGAM_CDICON 15
|
||||
#define IRQ_U300_IRQ0_EXT 1
|
||||
#define IRQ_U300_IRQ1_EXT 2
|
||||
#define IRQ_U300_DMA 3
|
||||
#define IRQ_U300_VIDEO_ENC_0 4
|
||||
#define IRQ_U300_VIDEO_ENC_1 5
|
||||
#define IRQ_U300_AAIF_RX 6
|
||||
#define IRQ_U300_AAIF_TX 7
|
||||
#define IRQ_U300_AAIF_VGPIO 8
|
||||
#define IRQ_U300_AAIF_WAKEUP 9
|
||||
#define IRQ_U300_PCM_I2S0_FRAME 10
|
||||
#define IRQ_U300_PCM_I2S0_FIFO 11
|
||||
#define IRQ_U300_PCM_I2S1_FRAME 12
|
||||
#define IRQ_U300_PCM_I2S1_FIFO 13
|
||||
#define IRQ_U300_XGAM_GAMCON 14
|
||||
#define IRQ_U300_XGAM_CDI 15
|
||||
#define IRQ_U300_XGAM_CDICON 16
|
||||
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
|
||||
/* MMIACC not used on the DB3210 or DB3350 chips */
|
||||
#define IRQ_U300_XGAM_MMIACC 16
|
||||
#define IRQ_U300_XGAM_MMIACC 17
|
||||
#endif
|
||||
#define IRQ_U300_XGAM_PDI 17
|
||||
#define IRQ_U300_XGAM_PDICON 18
|
||||
#define IRQ_U300_XGAM_GAMEACC 19
|
||||
#define IRQ_U300_XGAM_MCIDCT 20
|
||||
#define IRQ_U300_APEX 21
|
||||
#define IRQ_U300_UART0 22
|
||||
#define IRQ_U300_SPI 23
|
||||
#define IRQ_U300_TIMER_APP_OS 24
|
||||
#define IRQ_U300_TIMER_APP_DD 25
|
||||
#define IRQ_U300_TIMER_APP_GP1 26
|
||||
#define IRQ_U300_TIMER_APP_GP2 27
|
||||
#define IRQ_U300_TIMER_OS 28
|
||||
#define IRQ_U300_TIMER_MS 29
|
||||
#define IRQ_U300_KEYPAD_KEYBF 30
|
||||
#define IRQ_U300_KEYPAD_KEYBR 31
|
||||
#define IRQ_U300_XGAM_PDI 18
|
||||
#define IRQ_U300_XGAM_PDICON 19
|
||||
#define IRQ_U300_XGAM_GAMEACC 20
|
||||
#define IRQ_U300_XGAM_MCIDCT 21
|
||||
#define IRQ_U300_APEX 22
|
||||
#define IRQ_U300_UART0 23
|
||||
#define IRQ_U300_SPI 24
|
||||
#define IRQ_U300_TIMER_APP_OS 25
|
||||
#define IRQ_U300_TIMER_APP_DD 26
|
||||
#define IRQ_U300_TIMER_APP_GP1 27
|
||||
#define IRQ_U300_TIMER_APP_GP2 28
|
||||
#define IRQ_U300_TIMER_OS 29
|
||||
#define IRQ_U300_TIMER_MS 30
|
||||
#define IRQ_U300_KEYPAD_KEYBF 31
|
||||
#define IRQ_U300_KEYPAD_KEYBR 32
|
||||
/* These are on INTCON1 - 32 lines */
|
||||
#define IRQ_U300_GPIO_PORT0 32
|
||||
#define IRQ_U300_GPIO_PORT1 33
|
||||
#define IRQ_U300_GPIO_PORT2 34
|
||||
#define IRQ_U300_GPIO_PORT0 33
|
||||
#define IRQ_U300_GPIO_PORT1 34
|
||||
#define IRQ_U300_GPIO_PORT2 35
|
||||
|
||||
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
|
||||
defined(CONFIG_MACH_U300_BS335)
|
||||
/* These are for DB3150, DB3200 and DB3350 */
|
||||
#define IRQ_U300_WDOG 35
|
||||
#define IRQ_U300_EVHIST 36
|
||||
#define IRQ_U300_MSPRO 37
|
||||
#define IRQ_U300_MMCSD_MCIINTR0 38
|
||||
#define IRQ_U300_MMCSD_MCIINTR1 39
|
||||
#define IRQ_U300_I2C0 40
|
||||
#define IRQ_U300_I2C1 41
|
||||
#define IRQ_U300_RTC 42
|
||||
#define IRQ_U300_NFIF 43
|
||||
#define IRQ_U300_NFIF2 44
|
||||
#define IRQ_U300_WDOG 36
|
||||
#define IRQ_U300_EVHIST 37
|
||||
#define IRQ_U300_MSPRO 38
|
||||
#define IRQ_U300_MMCSD_MCIINTR0 39
|
||||
#define IRQ_U300_MMCSD_MCIINTR1 40
|
||||
#define IRQ_U300_I2C0 41
|
||||
#define IRQ_U300_I2C1 42
|
||||
#define IRQ_U300_RTC 43
|
||||
#define IRQ_U300_NFIF 44
|
||||
#define IRQ_U300_NFIF2 45
|
||||
#endif
|
||||
|
||||
/* DB3150 and DB3200 have only 45 IRQs */
|
||||
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
|
||||
#define U300_VIC_IRQS_END 45
|
||||
#define U300_VIC_IRQS_END 46
|
||||
#endif
|
||||
|
||||
/* The DB3350-specific interrupt lines */
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
#define IRQ_U300_ISP_F0 45
|
||||
#define IRQ_U300_ISP_F1 46
|
||||
#define IRQ_U300_ISP_F2 47
|
||||
#define IRQ_U300_ISP_F3 48
|
||||
#define IRQ_U300_ISP_F4 49
|
||||
#define IRQ_U300_GPIO_PORT3 50
|
||||
#define IRQ_U300_SYSCON_PLL_LOCK 51
|
||||
#define IRQ_U300_UART1 52
|
||||
#define IRQ_U300_GPIO_PORT4 53
|
||||
#define IRQ_U300_GPIO_PORT5 54
|
||||
#define IRQ_U300_GPIO_PORT6 55
|
||||
#define U300_VIC_IRQS_END 56
|
||||
#define IRQ_U300_ISP_F0 46
|
||||
#define IRQ_U300_ISP_F1 47
|
||||
#define IRQ_U300_ISP_F2 48
|
||||
#define IRQ_U300_ISP_F3 49
|
||||
#define IRQ_U300_ISP_F4 50
|
||||
#define IRQ_U300_GPIO_PORT3 51
|
||||
#define IRQ_U300_SYSCON_PLL_LOCK 52
|
||||
#define IRQ_U300_UART1 53
|
||||
#define IRQ_U300_GPIO_PORT4 54
|
||||
#define IRQ_U300_GPIO_PORT5 55
|
||||
#define IRQ_U300_GPIO_PORT6 56
|
||||
#define U300_VIC_IRQS_END 57
|
||||
#endif
|
||||
|
||||
/* The DB3210-specific interrupt lines */
|
||||
#ifdef CONFIG_MACH_U300_BS365
|
||||
#define IRQ_U300_GPIO_PORT3 35
|
||||
#define IRQ_U300_GPIO_PORT4 36
|
||||
#define IRQ_U300_WDOG 37
|
||||
#define IRQ_U300_EVHIST 38
|
||||
#define IRQ_U300_MSPRO 39
|
||||
#define IRQ_U300_MMCSD_MCIINTR0 40
|
||||
#define IRQ_U300_MMCSD_MCIINTR1 41
|
||||
#define IRQ_U300_I2C0 42
|
||||
#define IRQ_U300_I2C1 43
|
||||
#define IRQ_U300_RTC 44
|
||||
#define IRQ_U300_NFIF 45
|
||||
#define IRQ_U300_NFIF2 46
|
||||
#define IRQ_U300_SYSCON_PLL_LOCK 47
|
||||
#define U300_VIC_IRQS_END 48
|
||||
#define IRQ_U300_GPIO_PORT3 36
|
||||
#define IRQ_U300_GPIO_PORT4 37
|
||||
#define IRQ_U300_WDOG 38
|
||||
#define IRQ_U300_EVHIST 39
|
||||
#define IRQ_U300_MSPRO 40
|
||||
#define IRQ_U300_MMCSD_MCIINTR0 41
|
||||
#define IRQ_U300_MMCSD_MCIINTR1 42
|
||||
#define IRQ_U300_I2C0 43
|
||||
#define IRQ_U300_I2C1 44
|
||||
#define IRQ_U300_RTC 45
|
||||
#define IRQ_U300_NFIF 46
|
||||
#define IRQ_U300_NFIF2 47
|
||||
#define IRQ_U300_SYSCON_PLL_LOCK 48
|
||||
#define U300_VIC_IRQS_END 49
|
||||
#endif
|
||||
|
||||
/* Maximum 8*7 GPIO lines */
|
||||
|
@ -117,6 +117,6 @@
|
|||
#define IRQ_U300_GPIO_END (U300_VIC_IRQS_END)
|
||||
#endif
|
||||
|
||||
#define NR_IRQS (IRQ_U300_GPIO_END)
|
||||
#define NR_IRQS (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
|
||||
|
||||
#endif
|
||||
|
|
|
@ -17,6 +17,7 @@ config UX500_SOC_DB5500
|
|||
config UX500_SOC_DB8500
|
||||
bool
|
||||
select MFD_DB8500_PRCMU
|
||||
select REGULATOR
|
||||
select REGULATOR_DB8500_PRCMU
|
||||
select CPU_FREQ_TABLE if CPU_FREQ
|
||||
|
||||
|
|
|
@ -168,7 +168,7 @@ static ssize_t mbox_read_fifo(struct device *dev,
|
|||
return sprintf(buf, "0x%X\n", mbox_value);
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(fifo, S_IWUGO | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
|
||||
static DEVICE_ATTR(fifo, S_IWUSR | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
|
||||
|
||||
static int mbox_show(struct seq_file *s, void *data)
|
||||
{
|
||||
|
|
|
@ -99,7 +99,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|||
*/
|
||||
write_pen_release(cpu_logical_map(cpu));
|
||||
|
||||
gic_raise_softirq(cpumask_of(cpu), 1);
|
||||
smp_send_reschedule(cpu);
|
||||
|
||||
timeout = jiffies + (1 * HZ);
|
||||
while (time_before(jiffies, timeout)) {
|
||||
|
|
|
@ -26,18 +26,23 @@ ENTRY(v6_early_abort)
|
|||
mrc p15, 0, r1, c5, c0, 0 @ get FSR
|
||||
mrc p15, 0, r0, c6, c0, 0 @ get FAR
|
||||
/*
|
||||
* Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103).
|
||||
* The test below covers all the write situations, including Java bytecodes
|
||||
* Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR.
|
||||
*/
|
||||
bic r1, r1, #1 << 11 @ clear bit 11 of FSR
|
||||
tst r5, #PSR_J_BIT @ Java?
|
||||
#ifdef CONFIG_ARM_ERRATA_326103
|
||||
ldr ip, =0x4107b36
|
||||
mrc p15, 0, r3, c0, c0, 0 @ get processor id
|
||||
teq ip, r3, lsr #4 @ r0 ARM1136?
|
||||
bne do_DataAbort
|
||||
do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
|
||||
ldreq r3, [r4] @ read aborted ARM instruction
|
||||
tst r5, #PSR_J_BIT @ Java?
|
||||
tsteq r5, #PSR_T_BIT @ Thumb?
|
||||
bne do_DataAbort
|
||||
bic r1, r1, #1 << 11 @ clear bit 11 of FSR
|
||||
ldr r3, [r4] @ read aborted ARM instruction
|
||||
#ifdef CONFIG_CPU_ENDIAN_BE8
|
||||
reveq r3, r3
|
||||
rev r3, r3
|
||||
#endif
|
||||
do_ldrd_abort tmp=ip, insn=r3
|
||||
tst r3, #1 << 20 @ L = 0 -> write
|
||||
orreq r1, r1, #1 << 11 @ yes.
|
||||
#endif
|
||||
b do_DataAbort
|
||||
|
|
|
@ -32,6 +32,7 @@ static void __iomem *l2x0_base;
|
|||
static DEFINE_RAW_SPINLOCK(l2x0_lock);
|
||||
static u32 l2x0_way_mask; /* Bitmask of active ways */
|
||||
static u32 l2x0_size;
|
||||
static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
|
||||
|
||||
struct l2x0_regs l2x0_saved_regs;
|
||||
|
||||
|
@ -61,12 +62,7 @@ static inline void cache_sync(void)
|
|||
{
|
||||
void __iomem *base = l2x0_base;
|
||||
|
||||
#ifdef CONFIG_PL310_ERRATA_753970
|
||||
/* write to an unmmapped register */
|
||||
writel_relaxed(0, base + L2X0_DUMMY_REG);
|
||||
#else
|
||||
writel_relaxed(0, base + L2X0_CACHE_SYNC);
|
||||
#endif
|
||||
writel_relaxed(0, base + sync_reg_offset);
|
||||
cache_wait(base + L2X0_CACHE_SYNC, 1);
|
||||
}
|
||||
|
||||
|
@ -85,10 +81,13 @@ static inline void l2x0_inv_line(unsigned long addr)
|
|||
}
|
||||
|
||||
#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
|
||||
static inline void debug_writel(unsigned long val)
|
||||
{
|
||||
if (outer_cache.set_debug)
|
||||
outer_cache.set_debug(val);
|
||||
}
|
||||
|
||||
#define debug_writel(val) outer_cache.set_debug(val)
|
||||
|
||||
static void l2x0_set_debug(unsigned long val)
|
||||
static void pl310_set_debug(unsigned long val)
|
||||
{
|
||||
writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
|
||||
}
|
||||
|
@ -98,7 +97,7 @@ static inline void debug_writel(unsigned long val)
|
|||
{
|
||||
}
|
||||
|
||||
#define l2x0_set_debug NULL
|
||||
#define pl310_set_debug NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PL310_ERRATA_588369
|
||||
|
@ -331,6 +330,11 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
|
|||
else
|
||||
ways = 8;
|
||||
type = "L310";
|
||||
#ifdef CONFIG_PL310_ERRATA_753970
|
||||
/* Unmapped register. */
|
||||
sync_reg_offset = L2X0_DUMMY_REG;
|
||||
#endif
|
||||
outer_cache.set_debug = pl310_set_debug;
|
||||
break;
|
||||
case L2X0_CACHE_ID_PART_L210:
|
||||
ways = (aux >> 13) & 0xf;
|
||||
|
@ -379,7 +383,6 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
|
|||
outer_cache.flush_all = l2x0_flush_all;
|
||||
outer_cache.inv_all = l2x0_inv_all;
|
||||
outer_cache.disable = l2x0_disable;
|
||||
outer_cache.set_debug = l2x0_set_debug;
|
||||
|
||||
printk(KERN_INFO "%s cache controller enabled\n", type);
|
||||
printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
|
||||
|
|
|
@ -293,11 +293,11 @@ EXPORT_SYMBOL(pfn_valid);
|
|||
#endif
|
||||
|
||||
#ifndef CONFIG_SPARSEMEM
|
||||
static void arm_memory_present(void)
|
||||
static void __init arm_memory_present(void)
|
||||
{
|
||||
}
|
||||
#else
|
||||
static void arm_memory_present(void)
|
||||
static void __init arm_memory_present(void)
|
||||
{
|
||||
struct memblock_region *reg;
|
||||
|
||||
|
|
|
@ -618,8 +618,8 @@ static void __init alloc_init_section(pud_t *pud, unsigned long addr,
|
|||
}
|
||||
}
|
||||
|
||||
static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
|
||||
unsigned long phys, const struct mem_type *type)
|
||||
static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
|
||||
unsigned long end, unsigned long phys, const struct mem_type *type)
|
||||
{
|
||||
pud_t *pud = pud_offset(pgd, addr);
|
||||
unsigned long next;
|
||||
|
|
|
@ -916,6 +916,13 @@ void omap_start_dma(int lch)
|
|||
l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
|
||||
l |= OMAP_DMA_CCR_EN;
|
||||
|
||||
/*
|
||||
* As dma_write() uses IO accessors which are weakly ordered, there
|
||||
* is no guarantee that data in coherent DMA memory will be visible
|
||||
* to the DMA device. Add a memory barrier here to ensure that any
|
||||
* such data is visible prior to enabling DMA.
|
||||
*/
|
||||
mb();
|
||||
p->dma_write(l, CCR, lch);
|
||||
|
||||
dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
|
||||
|
@ -965,6 +972,13 @@ void omap_stop_dma(int lch)
|
|||
p->dma_write(l, CCR, lch);
|
||||
}
|
||||
|
||||
/*
|
||||
* Ensure that data transferred by DMA is visible to any access
|
||||
* after DMA has been disabled. This is important for coherent
|
||||
* DMA regions.
|
||||
*/
|
||||
mb();
|
||||
|
||||
if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
|
||||
int next_lch, cur_lch = lch;
|
||||
char dma_chan_link_map[dma_lch_count];
|
||||
|
|
|
@ -305,6 +305,7 @@ struct omap_hwmod_sysc_fields {
|
|||
* @rev_offs: IP block revision register offset (from module base addr)
|
||||
* @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
|
||||
* @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
|
||||
* @srst_udelay: Delay needed after doing a softreset in usecs
|
||||
* @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
|
||||
* @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
|
||||
* @clockact: the default value of the module CLOCKACTIVITY bits
|
||||
|
@ -330,9 +331,10 @@ struct omap_hwmod_class_sysconfig {
|
|||
u16 sysc_offs;
|
||||
u16 syss_offs;
|
||||
u16 sysc_flags;
|
||||
struct omap_hwmod_sysc_fields *sysc_fields;
|
||||
u8 srst_udelay;
|
||||
u8 idlemodes;
|
||||
u8 clockact;
|
||||
struct omap_hwmod_sysc_fields *sysc_fields;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
@ -348,7 +348,6 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
|
|||
sdrc_actim_ctrl_b_1, sdrc_mr_1);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
void omap3_sram_restore_context(void)
|
||||
{
|
||||
omap_sram_ceil = omap_sram_base + omap_sram_size;
|
||||
|
@ -358,17 +357,18 @@ void omap3_sram_restore_context(void)
|
|||
omap3_sram_configure_core_dpll_sz);
|
||||
omap_push_sram_idle();
|
||||
}
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
#endif /* CONFIG_ARCH_OMAP3 */
|
||||
|
||||
static inline int omap34xx_sram_init(void)
|
||||
{
|
||||
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
|
||||
omap3_sram_restore_context();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
static inline int omap34xx_sram_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_ARCH_OMAP3 */
|
||||
|
||||
static inline int am33xx_sram_init(void)
|
||||
{
|
||||
|
|
|
@ -18,6 +18,8 @@
|
|||
#ifndef __PLAT_S3C_SDHCI_H
|
||||
#define __PLAT_S3C_SDHCI_H __FILE__
|
||||
|
||||
#include <plat/devs.h>
|
||||
|
||||
struct platform_device;
|
||||
struct mmc_host;
|
||||
struct mmc_card;
|
||||
|
@ -356,4 +358,30 @@ static inline void exynos4_default_sdhci3(void) { }
|
|||
|
||||
#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
|
||||
|
||||
static inline void s3c_sdhci_setname(int id, char *name)
|
||||
{
|
||||
switch (id) {
|
||||
#ifdef CONFIG_S3C_DEV_HSMMC
|
||||
case 0:
|
||||
s3c_device_hsmmc0.name = name;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_S3C_DEV_HSMMC1
|
||||
case 1:
|
||||
s3c_device_hsmmc1.name = name;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_S3C_DEV_HSMMC2
|
||||
case 2:
|
||||
s3c_device_hsmmc2.name = name;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_S3C_DEV_HSMMC3
|
||||
case 3:
|
||||
s3c_device_hsmmc3.name = name;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* __PLAT_S3C_SDHCI_H */
|
||||
|
|
|
@ -17,6 +17,8 @@
|
|||
#include <linux/sched.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/user.h>
|
||||
|
||||
#include <asm/cp15.h>
|
||||
#include <asm/cputype.h>
|
||||
|
@ -528,6 +530,103 @@ void vfp_flush_hwstate(struct thread_info *thread)
|
|||
put_cpu();
|
||||
}
|
||||
|
||||
/*
|
||||
* Save the current VFP state into the provided structures and prepare
|
||||
* for entry into a new function (signal handler).
|
||||
*/
|
||||
int vfp_preserve_user_clear_hwstate(struct user_vfp __user *ufp,
|
||||
struct user_vfp_exc __user *ufp_exc)
|
||||
{
|
||||
struct thread_info *thread = current_thread_info();
|
||||
struct vfp_hard_struct *hwstate = &thread->vfpstate.hard;
|
||||
int err = 0;
|
||||
|
||||
/* Ensure that the saved hwstate is up-to-date. */
|
||||
vfp_sync_hwstate(thread);
|
||||
|
||||
/*
|
||||
* Copy the floating point registers. There can be unused
|
||||
* registers see asm/hwcap.h for details.
|
||||
*/
|
||||
err |= __copy_to_user(&ufp->fpregs, &hwstate->fpregs,
|
||||
sizeof(hwstate->fpregs));
|
||||
/*
|
||||
* Copy the status and control register.
|
||||
*/
|
||||
__put_user_error(hwstate->fpscr, &ufp->fpscr, err);
|
||||
|
||||
/*
|
||||
* Copy the exception registers.
|
||||
*/
|
||||
__put_user_error(hwstate->fpexc, &ufp_exc->fpexc, err);
|
||||
__put_user_error(hwstate->fpinst, &ufp_exc->fpinst, err);
|
||||
__put_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err);
|
||||
|
||||
if (err)
|
||||
return -EFAULT;
|
||||
|
||||
/* Ensure that VFP is disabled. */
|
||||
vfp_flush_hwstate(thread);
|
||||
|
||||
/*
|
||||
* As per the PCS, clear the length and stride bits for function
|
||||
* entry.
|
||||
*/
|
||||
hwstate->fpscr &= ~(FPSCR_LENGTH_MASK | FPSCR_STRIDE_MASK);
|
||||
|
||||
/*
|
||||
* Disable VFP in the hwstate so that we can detect if it gets
|
||||
* used.
|
||||
*/
|
||||
hwstate->fpexc &= ~FPEXC_EN;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Sanitise and restore the current VFP state from the provided structures. */
|
||||
int vfp_restore_user_hwstate(struct user_vfp __user *ufp,
|
||||
struct user_vfp_exc __user *ufp_exc)
|
||||
{
|
||||
struct thread_info *thread = current_thread_info();
|
||||
struct vfp_hard_struct *hwstate = &thread->vfpstate.hard;
|
||||
unsigned long fpexc;
|
||||
int err = 0;
|
||||
|
||||
/*
|
||||
* If VFP has been used, then disable it to avoid corrupting
|
||||
* the new thread state.
|
||||
*/
|
||||
if (hwstate->fpexc & FPEXC_EN)
|
||||
vfp_flush_hwstate(thread);
|
||||
|
||||
/*
|
||||
* Copy the floating point registers. There can be unused
|
||||
* registers see asm/hwcap.h for details.
|
||||
*/
|
||||
err |= __copy_from_user(&hwstate->fpregs, &ufp->fpregs,
|
||||
sizeof(hwstate->fpregs));
|
||||
/*
|
||||
* Copy the status and control register.
|
||||
*/
|
||||
__get_user_error(hwstate->fpscr, &ufp->fpscr, err);
|
||||
|
||||
/*
|
||||
* Sanitise and restore the exception registers.
|
||||
*/
|
||||
__get_user_error(fpexc, &ufp_exc->fpexc, err);
|
||||
|
||||
/* Ensure the VFP is enabled. */
|
||||
fpexc |= FPEXC_EN;
|
||||
|
||||
/* Ensure FPINST2 is invalid and the exception flag is cleared. */
|
||||
fpexc &= ~(FPEXC_EX | FPEXC_FP2V);
|
||||
hwstate->fpexc = fpexc;
|
||||
|
||||
__get_user_error(hwstate->fpinst, &ufp_exc->fpinst, err);
|
||||
__get_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err);
|
||||
|
||||
return err ? -EFAULT : 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* VFP hardware can lose all context when a CPU goes offline.
|
||||
* As we will be running in SMP mode with CPU hotplug, we will save the
|
||||
|
|
|
@ -38,7 +38,7 @@ static struct platform_device rtc_device = {
|
|||
.name = "rtc-bfin",
|
||||
.id = -1,
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_RTC_DRV_BFIN */
|
||||
|
||||
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
|
@ -100,7 +100,7 @@ static struct platform_device bfin_uart0_device = {
|
|||
.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_UART0 */
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART1
|
||||
static struct resource bfin_uart1_resources[] = {
|
||||
{
|
||||
|
@ -148,7 +148,7 @@ static struct platform_device bfin_uart1_device = {
|
|||
.platform_data = &bfin_uart1_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_UART1 */
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART2
|
||||
static struct resource bfin_uart2_resources[] = {
|
||||
{
|
||||
|
@ -196,8 +196,8 @@ static struct platform_device bfin_uart2_device = {
|
|||
.platform_data = &bfin_uart2_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_UART2 */
|
||||
#endif /* CONFIG_SERIAL_BFIN */
|
||||
|
||||
#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
|
||||
#ifdef CONFIG_BFIN_SIR0
|
||||
|
@ -224,7 +224,7 @@ static struct platform_device bfin_sir0_device = {
|
|||
.num_resources = ARRAY_SIZE(bfin_sir0_resources),
|
||||
.resource = bfin_sir0_resources,
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_BFIN_SIR0 */
|
||||
#ifdef CONFIG_BFIN_SIR1
|
||||
static struct resource bfin_sir1_resources[] = {
|
||||
{
|
||||
|
@ -249,7 +249,7 @@ static struct platform_device bfin_sir1_device = {
|
|||
.num_resources = ARRAY_SIZE(bfin_sir1_resources),
|
||||
.resource = bfin_sir1_resources,
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_BFIN_SIR1 */
|
||||
#ifdef CONFIG_BFIN_SIR2
|
||||
static struct resource bfin_sir2_resources[] = {
|
||||
{
|
||||
|
@ -274,8 +274,8 @@ static struct platform_device bfin_sir2_device = {
|
|||
.num_resources = ARRAY_SIZE(bfin_sir2_resources),
|
||||
.resource = bfin_sir2_resources,
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
#endif /* CONFIG_BFIN_SIR2 */
|
||||
#endif /* CONFIG_BFIN_SIR */
|
||||
|
||||
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
|
||||
|
@ -311,7 +311,7 @@ static struct platform_device bfin_sport0_uart_device = {
|
|||
.platform_data = &bfin_sport0_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT0_UART */
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
|
||||
static struct resource bfin_sport1_uart_resources[] = {
|
||||
{
|
||||
|
@ -345,7 +345,7 @@ static struct platform_device bfin_sport1_uart_device = {
|
|||
.platform_data = &bfin_sport1_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT1_UART */
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
|
||||
static struct resource bfin_sport2_uart_resources[] = {
|
||||
{
|
||||
|
@ -379,7 +379,7 @@ static struct platform_device bfin_sport2_uart_device = {
|
|||
.platform_data = &bfin_sport2_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT2_UART */
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
|
||||
static struct resource bfin_sport3_uart_resources[] = {
|
||||
{
|
||||
|
@ -413,8 +413,8 @@ static struct platform_device bfin_sport3_uart_device = {
|
|||
.platform_data = &bfin_sport3_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT3_UART */
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT */
|
||||
|
||||
#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
|
||||
static unsigned short bfin_can_peripherals[] = {
|
||||
|
@ -452,7 +452,7 @@ static struct platform_device bfin_can_device = {
|
|||
.platform_data = &bfin_can_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_CAN_BFIN */
|
||||
|
||||
/*
|
||||
* USB-LAN EzExtender board
|
||||
|
@ -488,7 +488,7 @@ static struct platform_device smc91x_device = {
|
|||
.platform_data = &smc91x_info,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_SMC91X */
|
||||
|
||||
#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
|
||||
/* all SPI peripherals info goes here */
|
||||
|
@ -518,7 +518,8 @@ static struct flash_platform_data bfin_spi_flash_data = {
|
|||
static struct bfin5xx_spi_chip spi_flash_chip_info = {
|
||||
.enable_dma = 0, /* use dma transfer with this chip*/
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_MTD_M25P80 */
|
||||
#endif /* CONFIG_SPI_BFIN5XX */
|
||||
|
||||
#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
|
||||
#include <linux/spi/ad7879.h>
|
||||
|
@ -535,7 +536,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
|
|||
.gpio_export = 1, /* Export GPIO to gpiolib */
|
||||
.gpio_base = -1, /* Dynamic allocation */
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_TOUCHSCREEN_AD7879 */
|
||||
|
||||
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
|
||||
#include <asm/bfin-lq035q1.h>
|
||||
|
@ -564,7 +565,7 @@ static struct platform_device bfin_lq035q1_device = {
|
|||
.platform_data = &bfin_lq035q1_data,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_FB_BFIN_LQ035Q1 */
|
||||
|
||||
static struct spi_board_info bf538_spi_board_info[] __initdata = {
|
||||
#if defined(CONFIG_MTD_M25P80) \
|
||||
|
@ -579,7 +580,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
|
|||
.controller_data = &spi_flash_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
#endif /* CONFIG_MTD_M25P80 */
|
||||
#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
|
||||
{
|
||||
.modalias = "ad7879",
|
||||
|
@ -590,7 +591,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
|
|||
.chip_select = 1,
|
||||
.mode = SPI_CPHA | SPI_CPOL,
|
||||
},
|
||||
#endif
|
||||
#endif /* CONFIG_TOUCHSCREEN_AD7879_SPI */
|
||||
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
|
||||
{
|
||||
.modalias = "bfin-lq035q1-spi",
|
||||
|
@ -599,7 +600,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
|
|||
.chip_select = 2,
|
||||
.mode = SPI_CPHA | SPI_CPOL,
|
||||
},
|
||||
#endif
|
||||
#endif /* CONFIG_FB_BFIN_LQ035Q1 */
|
||||
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
|
||||
{
|
||||
.modalias = "spidev",
|
||||
|
@ -607,7 +608,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
|
|||
.bus_num = 0,
|
||||
.chip_select = 1,
|
||||
},
|
||||
#endif
|
||||
#endif /* CONFIG_SPI_SPIDEV */
|
||||
};
|
||||
|
||||
/* SPI (0) */
|
||||
|
@ -716,8 +717,6 @@ static struct platform_device bf538_spi_master2 = {
|
|||
},
|
||||
};
|
||||
|
||||
#endif /* spi master and devices */
|
||||
|
||||
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
|
||||
static struct resource bfin_twi0_resource[] = {
|
||||
[0] = {
|
||||
|
@ -759,8 +758,8 @@ static struct platform_device i2c_bfin_twi1_device = {
|
|||
.num_resources = ARRAY_SIZE(bfin_twi1_resource),
|
||||
.resource = bfin_twi1_resource,
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
#endif /* CONFIG_BF542 */
|
||||
#endif /* CONFIG_I2C_BLACKFIN_TWI */
|
||||
|
||||
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
|
||||
#include <linux/gpio_keys.h>
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/bootmem.h>
|
||||
#include <linux/genalloc.h>
|
||||
#include <asm/dma-mapping.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
struct dma_map_ops *dma_ops;
|
||||
EXPORT_SYMBOL(dma_ops);
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Process creation support for Hexagon
|
||||
*
|
||||
* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
|
||||
* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
|
@ -88,7 +88,7 @@ void (*idle_sleep)(void) = default_idle;
|
|||
void cpu_idle(void)
|
||||
{
|
||||
while (1) {
|
||||
tick_nohz_stop_sched_tick(1);
|
||||
tick_nohz_idle_enter();
|
||||
local_irq_disable();
|
||||
while (!need_resched()) {
|
||||
idle_sleep();
|
||||
|
@ -97,7 +97,7 @@ void cpu_idle(void)
|
|||
local_irq_disable();
|
||||
}
|
||||
local_irq_enable();
|
||||
tick_nohz_restart_sched_tick();
|
||||
tick_nohz_idle_exit();
|
||||
schedule();
|
||||
}
|
||||
}
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
#include <linux/ptrace.h>
|
||||
#include <linux/regset.h>
|
||||
#include <linux/user.h>
|
||||
#include <linux/elf.h>
|
||||
|
||||
#include <asm/user.h>
|
||||
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* SMP support for Hexagon
|
||||
*
|
||||
* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
|
||||
* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
|
@ -28,6 +28,7 @@
|
|||
#include <linux/sched.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/cpu.h>
|
||||
|
||||
#include <asm/time.h> /* timer_interrupt */
|
||||
#include <asm/hexagon_vm.h>
|
||||
|
@ -177,7 +178,12 @@ void __cpuinit start_secondary(void)
|
|||
|
||||
printk(KERN_INFO "%s cpu %d\n", __func__, current_thread_info()->cpu);
|
||||
|
||||
notify_cpu_starting(cpu);
|
||||
|
||||
ipi_call_lock();
|
||||
set_cpu_online(cpu, true);
|
||||
ipi_call_unlock();
|
||||
|
||||
local_irq_enable();
|
||||
|
||||
cpu_idle();
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/timer-regs.h>
|
||||
#include <asm/hexagon_vm.h>
|
||||
|
|
|
@ -21,6 +21,7 @@
|
|||
#include <linux/err.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/binfmts.h>
|
||||
|
||||
#include <asm/vdso.h>
|
||||
|
||||
|
|
|
@ -106,15 +106,16 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
|
|||
return -EFAULT;
|
||||
|
||||
{
|
||||
register unsigned long r8 __asm ("r8") = 0;
|
||||
register unsigned long r8 __asm ("r8");
|
||||
unsigned long prev;
|
||||
__asm__ __volatile__(
|
||||
" mf;; \n"
|
||||
" mov ar.ccv=%3;; \n"
|
||||
"[1:] cmpxchg4.acq %0=[%1],%2,ar.ccv \n"
|
||||
" mov %0=r0 \n"
|
||||
" mov ar.ccv=%4;; \n"
|
||||
"[1:] cmpxchg4.acq %1=[%2],%3,ar.ccv \n"
|
||||
" .xdata4 \"__ex_table\", 1b-., 2f-. \n"
|
||||
"[2:]"
|
||||
: "=r" (prev)
|
||||
: "=r" (r8), "=r" (prev)
|
||||
: "r" (uaddr), "r" (newval),
|
||||
"rO" ((long) (unsigned) oldval)
|
||||
: "memory");
|
||||
|
|
|
@ -604,12 +604,6 @@ pfm_unprotect_ctx_ctxsw(pfm_context_t *x, unsigned long f)
|
|||
spin_unlock(&(x)->ctx_lock);
|
||||
}
|
||||
|
||||
static inline unsigned int
|
||||
pfm_do_munmap(struct mm_struct *mm, unsigned long addr, size_t len, int acct)
|
||||
{
|
||||
return do_munmap(mm, addr, len);
|
||||
}
|
||||
|
||||
static inline unsigned long
|
||||
pfm_get_unmapped_area(struct file *file, unsigned long addr, unsigned long len, unsigned long pgoff, unsigned long flags, unsigned long exec)
|
||||
{
|
||||
|
@ -1458,8 +1452,9 @@ pfm_unreserve_session(pfm_context_t *ctx, int is_syswide, unsigned int cpu)
|
|||
* a PROTECT_CTX() section.
|
||||
*/
|
||||
static int
|
||||
pfm_remove_smpl_mapping(struct task_struct *task, void *vaddr, unsigned long size)
|
||||
pfm_remove_smpl_mapping(void *vaddr, unsigned long size)
|
||||
{
|
||||
struct task_struct *task = current;
|
||||
int r;
|
||||
|
||||
/* sanity checks */
|
||||
|
@ -1473,13 +1468,8 @@ pfm_remove_smpl_mapping(struct task_struct *task, void *vaddr, unsigned long siz
|
|||
/*
|
||||
* does the actual unmapping
|
||||
*/
|
||||
down_write(&task->mm->mmap_sem);
|
||||
r = vm_munmap((unsigned long)vaddr, size);
|
||||
|
||||
DPRINT(("down_write done smpl_vaddr=%p size=%lu\n", vaddr, size));
|
||||
|
||||
r = pfm_do_munmap(task->mm, (unsigned long)vaddr, size, 0);
|
||||
|
||||
up_write(&task->mm->mmap_sem);
|
||||
if (r !=0) {
|
||||
printk(KERN_ERR "perfmon: [%d] unable to unmap sampling buffer @%p size=%lu\n", task_pid_nr(task), vaddr, size);
|
||||
}
|
||||
|
@ -1945,7 +1935,7 @@ pfm_flush(struct file *filp, fl_owner_t id)
|
|||
* because some VM function reenables interrupts.
|
||||
*
|
||||
*/
|
||||
if (smpl_buf_vaddr) pfm_remove_smpl_mapping(current, smpl_buf_vaddr, smpl_buf_size);
|
||||
if (smpl_buf_vaddr) pfm_remove_smpl_mapping(smpl_buf_vaddr, smpl_buf_size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -49,7 +49,6 @@ CONFIG_BLK_DEV_RAM=y
|
|||
CONFIG_NETDEVICES=y
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_FEC=y
|
||||
CONFIG_FEC2=y
|
||||
# CONFIG_NETDEV_1000 is not set
|
||||
# CONFIG_NETDEV_10000 is not set
|
||||
CONFIG_PPP=y
|
||||
|
|
|
@ -74,9 +74,7 @@ static void __init m527x_fec_init(void)
|
|||
writew(par | 0xf00, MCF_IPSBAR + 0x100082);
|
||||
v = readb(MCF_IPSBAR + 0x100078);
|
||||
writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC2
|
||||
/* Set multi-function pins to ethernet mode for fec1 */
|
||||
par = readw(MCF_IPSBAR + 0x100082);
|
||||
writew(par | 0xa0, MCF_IPSBAR + 0x100082);
|
||||
|
|
|
@ -3,9 +3,3 @@
|
|||
#
|
||||
|
||||
obj-y := config.o
|
||||
|
||||
extra-y := bootlogo.rh
|
||||
|
||||
$(obj)/bootlogo.rh: $(src)/bootlogo.h
|
||||
perl $(src)/../68328/bootlogo.pl < $(src)/bootlogo.h \
|
||||
> $(obj)/bootlogo.rh
|
||||
|
|
|
@ -3,14 +3,9 @@
|
|||
#
|
||||
|
||||
obj-y := config.o
|
||||
logo-$(UCDIMM) := bootlogo.rh
|
||||
logo-$(DRAGEN2) := screen.h
|
||||
extra-y := $(logo-y)
|
||||
|
||||
$(obj)/bootlogo.rh: $(src)/../68EZ328/bootlogo.h
|
||||
perl $(src)/bootlogo.pl < $(src)/../68328/bootlogo.h > $(obj)/bootlogo.rh
|
||||
extra-$(DRAGEN2):= screen.h
|
||||
|
||||
$(obj)/screen.h: $(src)/screen.xbm $(src)/xbm2lcd.pl
|
||||
perl $(src)/xbm2lcd.pl < $(src)/screen.xbm > $(obj)/screen.h
|
||||
|
||||
clean-files := $(obj)/screen.h $(obj)/bootlogo.rh
|
||||
clean-files := $(obj)/screen.h
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
#define splash_width 640
|
||||
#define splash_height 480
|
||||
static unsigned char splash_bits[] = {
|
||||
unsigned char __attribute__ ((aligned(16))) bootlogo_bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
@ -114,7 +114,7 @@ static struct resource mcf_fec1_resources[] = {
|
|||
|
||||
static struct platform_device mcf_fec1 = {
|
||||
.name = "fec",
|
||||
.id = 0,
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(mcf_fec1_resources),
|
||||
.resource = mcf_fec1_resources,
|
||||
};
|
||||
|
|
|
@ -58,8 +58,8 @@ static void __init ar913x_wmac_setup(void)
|
|||
|
||||
static int ar933x_wmac_reset(void)
|
||||
{
|
||||
ath79_device_reset_clear(AR933X_RESET_WMAC);
|
||||
ath79_device_reset_set(AR933X_RESET_WMAC);
|
||||
ath79_device_reset_clear(AR933X_RESET_WMAC);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -45,7 +45,7 @@
|
|||
#define JZ4740_IRQ_LCD JZ4740_IRQ(30)
|
||||
|
||||
/* 2nd-level interrupts */
|
||||
#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(32) + (X))
|
||||
#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(32) + (x))
|
||||
|
||||
#define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
|
||||
#define JZ4740_IRQ_GPIO(x) (JZ4740_IRQ(48) + (x))
|
||||
|
|
|
@ -37,12 +37,6 @@ extern void tlbmiss_handler_setup_pgd(unsigned long pgd);
|
|||
write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
|
||||
} while (0)
|
||||
|
||||
|
||||
static inline unsigned long get_current_pgd(void)
|
||||
{
|
||||
return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL);
|
||||
}
|
||||
|
||||
#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
|
||||
|
||||
/*
|
||||
|
|
|
@ -257,11 +257,8 @@ asmlinkage int sys_sigsuspend(nabi_no_regargs struct pt_regs regs)
|
|||
return -EFAULT;
|
||||
sigdelsetmask(&newset, ~_BLOCKABLE);
|
||||
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->saved_sigmask = current->blocked;
|
||||
current->blocked = newset;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&newset);
|
||||
|
||||
current->state = TASK_INTERRUPTIBLE;
|
||||
schedule();
|
||||
|
@ -286,11 +283,8 @@ asmlinkage int sys_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
|
|||
return -EFAULT;
|
||||
sigdelsetmask(&newset, ~_BLOCKABLE);
|
||||
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->saved_sigmask = current->blocked;
|
||||
current->blocked = newset;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&newset);
|
||||
|
||||
current->state = TASK_INTERRUPTIBLE;
|
||||
schedule();
|
||||
|
@ -362,10 +356,7 @@ asmlinkage void sys_sigreturn(nabi_no_regargs struct pt_regs regs)
|
|||
goto badframe;
|
||||
|
||||
sigdelsetmask(&blocked, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = blocked;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&blocked);
|
||||
|
||||
sig = restore_sigcontext(®s, &frame->sf_sc);
|
||||
if (sig < 0)
|
||||
|
@ -401,10 +392,7 @@ asmlinkage void sys_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
|
|||
goto badframe;
|
||||
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = set;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&set);
|
||||
|
||||
sig = restore_sigcontext(®s, &frame->rs_uc.uc_mcontext);
|
||||
if (sig < 0)
|
||||
|
@ -580,12 +568,7 @@ static int handle_signal(unsigned long sig, siginfo_t *info,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
sigorsets(¤t->blocked, ¤t->blocked, &ka->sa.sa_mask);
|
||||
if (!(ka->sa.sa_flags & SA_NODEFER))
|
||||
sigaddset(¤t->blocked, sig);
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
block_sigmask(ka, sig);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -290,11 +290,8 @@ asmlinkage int sys32_sigsuspend(nabi_no_regargs struct pt_regs regs)
|
|||
return -EFAULT;
|
||||
sigdelsetmask(&newset, ~_BLOCKABLE);
|
||||
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->saved_sigmask = current->blocked;
|
||||
current->blocked = newset;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&newset);
|
||||
|
||||
current->state = TASK_INTERRUPTIBLE;
|
||||
schedule();
|
||||
|
@ -318,11 +315,8 @@ asmlinkage int sys32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
|
|||
return -EFAULT;
|
||||
sigdelsetmask(&newset, ~_BLOCKABLE);
|
||||
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->saved_sigmask = current->blocked;
|
||||
current->blocked = newset;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&newset);
|
||||
|
||||
current->state = TASK_INTERRUPTIBLE;
|
||||
schedule();
|
||||
|
@ -488,10 +482,7 @@ asmlinkage void sys32_sigreturn(nabi_no_regargs struct pt_regs regs)
|
|||
goto badframe;
|
||||
|
||||
sigdelsetmask(&blocked, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = blocked;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&blocked);
|
||||
|
||||
sig = restore_sigcontext32(®s, &frame->sf_sc);
|
||||
if (sig < 0)
|
||||
|
@ -529,10 +520,7 @@ asmlinkage void sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
|
|||
goto badframe;
|
||||
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = set;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&set);
|
||||
|
||||
sig = restore_sigcontext32(®s, &frame->rs_uc.uc_mcontext);
|
||||
if (sig < 0)
|
||||
|
|
|
@ -93,11 +93,8 @@ asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
|
|||
sigset_from_compat(&newset, &uset);
|
||||
sigdelsetmask(&newset, ~_BLOCKABLE);
|
||||
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->saved_sigmask = current->blocked;
|
||||
current->blocked = newset;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&newset);
|
||||
|
||||
current->state = TASK_INTERRUPTIBLE;
|
||||
schedule();
|
||||
|
@ -121,10 +118,7 @@ asmlinkage void sysn32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
|
|||
goto badframe;
|
||||
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = set;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&set);
|
||||
|
||||
sig = restore_sigcontext(®s, &frame->rs_uc.uc_mcontext);
|
||||
if (sig < 0)
|
||||
|
|
|
@ -104,7 +104,7 @@ static int pdc_console_tty_open(struct tty_struct *tty, struct file *filp)
|
|||
|
||||
static void pdc_console_tty_close(struct tty_struct *tty, struct file *filp)
|
||||
{
|
||||
if (!tty->count) {
|
||||
if (tty->count == 1) {
|
||||
del_timer_sync(&pdc_console_timer);
|
||||
tty_port_tty_set(&tty_port, NULL);
|
||||
}
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue