mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-29 23:53:32 +00:00
net/mlx5: Introduce physical port TC/prio access functions
Add access functions to set and query a physical port TC groups and prio parameters. Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
ad909eb064
commit
4f3961eeaf
4 changed files with 132 additions and 1 deletions
|
@ -405,3 +405,79 @@ int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx)
|
|||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);
|
||||
|
||||
int mlx5_max_tc(struct mlx5_core_dev *mdev)
|
||||
{
|
||||
u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;
|
||||
|
||||
return num_tc - 1;
|
||||
}
|
||||
|
||||
int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc)
|
||||
{
|
||||
u32 in[MLX5_ST_SZ_DW(qtct_reg)];
|
||||
u32 out[MLX5_ST_SZ_DW(qtct_reg)];
|
||||
int err;
|
||||
int i;
|
||||
|
||||
memset(in, 0, sizeof(in));
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (prio_tc[i] > mlx5_max_tc(mdev))
|
||||
return -EINVAL;
|
||||
|
||||
MLX5_SET(qtct_reg, in, prio, i);
|
||||
MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);
|
||||
|
||||
err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
|
||||
sizeof(out), MLX5_REG_QTCT, 0, 1);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);
|
||||
|
||||
static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in,
|
||||
int inlen)
|
||||
{
|
||||
u32 out[MLX5_ST_SZ_DW(qtct_reg)];
|
||||
|
||||
if (!MLX5_CAP_GEN(mdev, ets))
|
||||
return -ENOTSUPP;
|
||||
|
||||
return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
|
||||
MLX5_REG_QETCR, 0, 1);
|
||||
}
|
||||
|
||||
int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group)
|
||||
{
|
||||
u32 in[MLX5_ST_SZ_DW(qetc_reg)];
|
||||
int i;
|
||||
|
||||
memset(in, 0, sizeof(in));
|
||||
|
||||
for (i = 0; i <= mlx5_max_tc(mdev); i++) {
|
||||
MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
|
||||
MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
|
||||
}
|
||||
|
||||
return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);
|
||||
|
||||
int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw)
|
||||
{
|
||||
u32 in[MLX5_ST_SZ_DW(qetc_reg)];
|
||||
int i;
|
||||
|
||||
memset(in, 0, sizeof(in));
|
||||
|
||||
for (i = 0; i <= mlx5_max_tc(mdev); i++) {
|
||||
MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
|
||||
MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
|
||||
}
|
||||
|
||||
return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);
|
||||
|
|
|
@ -99,6 +99,8 @@ enum {
|
|||
};
|
||||
|
||||
enum {
|
||||
MLX5_REG_QETCR = 0x4005,
|
||||
MLX5_REG_QTCT = 0x400a,
|
||||
MLX5_REG_PCAP = 0x5001,
|
||||
MLX5_REG_PMTU = 0x5003,
|
||||
MLX5_REG_PTYS = 0x5004,
|
||||
|
|
|
@ -729,7 +729,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
|
|||
|
||||
u8 reserved_at_1bf[0x3];
|
||||
u8 log_max_msg[0x5];
|
||||
u8 reserved_at_1c7[0x18];
|
||||
u8 reserved_at_1c7[0x4];
|
||||
u8 max_tc[0x4];
|
||||
u8 reserved_at_1cf[0x10];
|
||||
|
||||
u8 stat_rate_support[0x10];
|
||||
u8 reserved_at_1ef[0xc];
|
||||
|
@ -7061,4 +7063,49 @@ struct mlx5_ifc_modify_flow_table_in_bits {
|
|||
u8 reserved_at_100[0x100];
|
||||
};
|
||||
|
||||
struct mlx5_ifc_ets_tcn_config_reg_bits {
|
||||
u8 g[0x1];
|
||||
u8 b[0x1];
|
||||
u8 r[0x1];
|
||||
u8 reserved_at_3[0x9];
|
||||
u8 group[0x4];
|
||||
u8 reserved_at_10[0x9];
|
||||
u8 bw_allocation[0x7];
|
||||
|
||||
u8 reserved_at_20[0xc];
|
||||
u8 max_bw_units[0x4];
|
||||
u8 reserved_at_30[0x8];
|
||||
u8 max_bw_value[0x8];
|
||||
};
|
||||
|
||||
struct mlx5_ifc_ets_global_config_reg_bits {
|
||||
u8 reserved_at_0[0x2];
|
||||
u8 r[0x1];
|
||||
u8 reserved_at_3[0x1d];
|
||||
|
||||
u8 reserved_at_20[0xc];
|
||||
u8 max_bw_units[0x4];
|
||||
u8 reserved_at_30[0x8];
|
||||
u8 max_bw_value[0x8];
|
||||
};
|
||||
|
||||
struct mlx5_ifc_qetc_reg_bits {
|
||||
u8 reserved_at_0[0x8];
|
||||
u8 port_number[0x8];
|
||||
u8 reserved_at_10[0x30];
|
||||
|
||||
struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
|
||||
struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
|
||||
};
|
||||
|
||||
struct mlx5_ifc_qtct_reg_bits {
|
||||
u8 reserved_at_0[0x8];
|
||||
u8 port_number[0x8];
|
||||
u8 reserved_at_10[0xd];
|
||||
u8 prio[0x3];
|
||||
|
||||
u8 reserved_at_20[0x1d];
|
||||
u8 tclass[0x3];
|
||||
};
|
||||
|
||||
#endif /* MLX5_IFC_H */
|
||||
|
|
|
@ -70,4 +70,10 @@ int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx);
|
|||
int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx,
|
||||
u8 *pfc_en_rx);
|
||||
|
||||
int mlx5_max_tc(struct mlx5_core_dev *mdev);
|
||||
|
||||
int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc);
|
||||
int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group);
|
||||
int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw);
|
||||
|
||||
#endif /* __MLX5_PORT_H__ */
|
||||
|
|
Loading…
Reference in a new issue