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ARM: SoC fixes for 6.2, part 4

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All the changes this time are minor devicetree corrections, the majority
 being for 64-bit Rockchip SoC support. These are a couple of corrections
 for properties that are in violation of the binding, some that put the
 machine into safer operating points for the eMMC and thermal settings,
 and missing properties that prevented rk356x PCIe and ethernet from
 working correctly.
 
 The changes for amlogic and mediatek address incorrect properties that
 were preventing the display support on MT8195 and the MMC support
 on various Meson SoCs from working correctly.
 
 The stihxxx-b2120 change fixes the GPIO polarity for the DVB tuner
 to allow this to be used correctly after a futre driver change,
 though it has no effect on older kernels.
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Merge tag 'soc-fixes-6.2-4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
 "All the changes this time are minor devicetree corrections, the
  majority being for 64-bit Rockchip SoC support. These are a couple of
  corrections for properties that are in violation of the binding, some
  that put the machine into safer operating points for the eMMC and
  thermal settings, and missing properties that prevented rk356x PCIe
  and ethernet from working correctly.

  The changes for amlogic and mediatek address incorrect properties that
  were preventing the display support on MT8195 and the MMC support on
  various Meson SoCs from working correctly.

  The stihxxx-b2120 change fixes the GPIO polarity for the DVB tuner to
  allow this to be used correctly after a futre driver change, though it
  has no effect on older kernels"

* tag 'soc-fixes-6.2-4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  arm64: dts: meson-gx: Make mmc host controller interrupts level-sensitive
  arm64: dts: meson-g12-common: Make mmc host controller interrupts level-sensitive
  arm64: dts: meson-axg: Make mmc host controller interrupts level-sensitive
  ARM: dts: stihxxx-b2120: fix polarity of reset line of tsin0 port
  arm64: dts: mediatek: mt8195: Fix vdosys* compatible strings
  arm64: dts: rockchip: align rk3399 DMC OPP table with bindings
  arm64: dts: rockchip: set sdmmc0 speed to sd-uhs-sdr50 on rock-3a
  arm64: dts: rockchip: fix probe of analog sound card on rock-3a
  arm64: dts: rockchip: add missing #interrupt-cells to rk356x pcie2x1
  arm64: dts: rockchip: fix input enable pinconf on rk3399
  ARM: dts: rockchip: add power-domains property to dp node on rk3288
  arm64: dts: rockchip: add io domain setting to rk3566-box-demo
  arm64: dts: rockchip: remove unsupported property from sdmmc2 for rock-3a
  arm64: dts: rockchip: drop unused LED mode property from rk3328-roc-cc
  arm64: dts: rockchip: reduce thermal limits on rk3399-pinephone-pro
  arm64: dts: rockchip: use correct reset names for rk3399 crypto nodes
This commit is contained in:
Linus Torvalds 2023-02-10 09:48:42 -08:00
commit 4f72a263e1
13 changed files with 37 additions and 20 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
arch/arm/boot/dts/rk3288.dtsi
View file

@ -1181,6 +1181,7 @@ edp: dp@ff970000 {
clock-names = "dp", "pclk";
phys = <&edp_phy>;
phy-names = "dp";
power-domains = <&power RK3288_PD_VIO>;
resets = <&cru SRST_EDP>;
reset-names = "dp";
rockchip,grf = <&grf>;

2
arch/arm/boot/dts/stihxxx-b2120.dtsi
View file

@ -178,7 +178,7 @@ tsin0: port {
tsin-num = <0>;
serial-not-parallel;
i2c-bus = <&ssc2>;
reset-gpios = <&pio15 4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&pio15 4 GPIO_ACTIVE_LOW>;
dvb-card = <STV0367_TDA18212_NIMA_1>;
};
};

4
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
View file

@ -1886,7 +1886,7 @@ apb: bus@ffe00000 {
sd_emmc_b: sd@5000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0x5000 0x0 0x800>;
interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_B>,
<&clkc CLKID_SD_EMMC_B_CLK0>,
@ -1898,7 +1898,7 @@ sd_emmc_b: sd@5000 {
sd_emmc_c: mmc@7000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0x7000 0x0 0x800>;
interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_C>,
<&clkc CLKID_SD_EMMC_C_CLK0>,

6
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
View file

@ -2324,7 +2324,7 @@ uart_A: serial@24000 {
sd_emmc_a: sd@ffe03000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0xffe03000 0x0 0x800>;
interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_A>,
<&clkc CLKID_SD_EMMC_A_CLK0>,
@ -2336,7 +2336,7 @@ sd_emmc_a: sd@ffe03000 {
sd_emmc_b: sd@ffe05000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0xffe05000 0x0 0x800>;
interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_B>,
<&clkc CLKID_SD_EMMC_B_CLK0>,
@ -2348,7 +2348,7 @@ sd_emmc_b: sd@ffe05000 {
sd_emmc_c: mmc@ffe07000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0xffe07000 0x0 0x800>;
interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_C>,
<&clkc CLKID_SD_EMMC_C_CLK0>,

6
arch/arm64/boot/dts/amlogic/meson-gx.dtsi
View file

@ -603,21 +603,21 @@ apb: apb@d0000000 {
sd_emmc_a: mmc@70000 {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x70000 0x0 0x800>;
interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sd_emmc_b: mmc@72000 {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x72000 0x0 0x800>;
interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sd_emmc_c: mmc@74000 {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x74000 0x0 0x800>;
interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};

4
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View file

@ -2146,7 +2146,7 @@ vencsys_core1: clock-controller@1b000000 {
};
vdosys0: syscon@1c01a000 {
compatible = "mediatek,mt8195-mmsys", "syscon";
compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
reg = <0 0x1c01a000 0 0x1000>;
mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
#clock-cells = <1>;
@ -2292,7 +2292,7 @@ larb1: larb@1c019000 {
};
vdosys1: syscon@1c100000 {
compatible = "mediatek,mt8195-mmsys", "syscon";
compatible = "mediatek,mt8195-vdosys1", "syscon";
reg = <0 0x1c100000 0 0x1000>;
#clock-cells = <1>;
};

2
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
View file

@ -96,7 +96,6 @@ power_led: led-0 {
linux,default-trigger = "heartbeat";
gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
default-state = "on";
mode = <0x23>;
};
user_led: led-1 {
@ -104,7 +103,6 @@ user_led: led-1 {
linux,default-trigger = "mmc1";
gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
default-state = "off";
mode = <0x05>;
};
};
};

2
arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi
View file

@ -111,7 +111,7 @@ opp05 {
};
};
dmc_opp_table: dmc_opp_table {
dmc_opp_table: opp-table-3 {
compatible = "operating-points-v2";
opp00 {

7
arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
View file

@ -104,6 +104,13 @@ wifi_pwrseq: sdio-wifi-pwrseq {
};
};
&cpu_alert0 {
temperature = <65000>;
};
&cpu_alert1 {
temperature = <68000>;
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};

6
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View file

@ -589,7 +589,7 @@ crypto0: crypto@ff8b0000 {
clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>;
clock-names = "hclk_master", "hclk_slave", "sclk";
resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>;
reset-names = "master", "lave", "crypto";
reset-names = "master", "slave", "crypto-rst";
};
crypto1: crypto@ff8b8000 {
@ -599,7 +599,7 @@ crypto1: crypto@ff8b8000 {
clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>;
clock-names = "hclk_master", "hclk_slave", "sclk";
resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>;
reset-names = "master", "slave", "crypto";
reset-names = "master", "slave", "crypto-rst";
};
i2c1: i2c@ff110000 {
@ -2241,13 +2241,11 @@ pcfg_input_enable: pcfg-input-enable {
pcfg_input_pull_up: pcfg-input-pull-up {
input-enable;
bias-pull-up;
drive-strength = <2>;
};
pcfg_input_pull_down: pcfg-input-pull-down {
input-enable;
bias-pull-down;
drive-strength = <2>;
};
clock {

11
arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
View file

@ -353,6 +353,17 @@ led_work_en: led_work_en {
};
};
&pmu_io_domains {
pmuio2-supply = <&vcc_3v3>;
vccio1-supply = <&vcc_3v3>;
vccio3-supply = <&vcc_3v3>;
vccio4-supply = <&vcca_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcca_1v8>;
vccio7-supply = <&vcc_3v3>;
status = "okay";
};
&pwm0 {
status = "okay";
};

5
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
View file

@ -571,6 +571,8 @@ &i2s0_8ch {
};
&i2s1_8ch {
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>;
rockchip,trcm-sync-tx-only;
status = "okay";
};
@ -730,14 +732,13 @@ &sdmmc0 {
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
sd-uhs-sdr104;
sd-uhs-sdr50;
vmmc-supply = <&vcc3v3_sd>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&sdmmc2 {
supports-sdio;
bus-width = <4>;
disable-wp;
cap-sd-highspeed;

1
arch/arm64/boot/dts/rockchip/rk356x.dtsi
View file

@ -966,6 +966,7 @@ pcie2x1: pcie@fe260000 {
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux";
device_type = "pci";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc 0>,
<0 0 0 2 &pcie_intc 1>,