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[ARM] pxa: add preliminary CPUFREQ support for PXA3xx
Signed-off-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Eric Miao
Russell King
parent
5c52de4a66
commit
4f788bb200
2 changed files with 259 additions and 0 deletions
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@ -10,6 +10,7 @@ obj-$(CONFIG_PM) += pm.o sleep.o standby.o
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ifeq ($(CONFIG_CPU_FREQ),y)
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obj-$(CONFIG_PXA25x) += cpufreq-pxa2xx.o
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obj-$(CONFIG_PXA27x) += cpufreq-pxa2xx.o
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obj-$(CONFIG_PXA3xx) += cpufreq-pxa3xx.o
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endif
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# Generic drivers that other drivers may depend upon
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258
arch/arm/mach-pxa/cpufreq-pxa3xx.c
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258
arch/arm/mach-pxa/cpufreq-pxa3xx.c
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@ -0,0 +1,258 @@
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/*
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* linux/arch/arm/mach-pxa/cpufreq-pxa3xx.c
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*
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* Copyright (C) 2008 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <mach/hardware.h>
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#include <mach/pxa-regs.h>
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#include <mach/pxa3xx-regs.h>
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#include "generic.h"
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#define HSS_104M (0)
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#define HSS_156M (1)
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#define HSS_208M (2)
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#define HSS_312M (3)
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#define SMCFS_78M (0)
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#define SMCFS_104M (2)
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#define SMCFS_208M (5)
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#define SFLFS_104M (0)
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#define SFLFS_156M (1)
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#define SFLFS_208M (2)
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#define SFLFS_312M (3)
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#define XSPCLK_156M (0)
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#define XSPCLK_NONE (3)
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#define DMCFS_26M (0)
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#define DMCFS_260M (3)
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struct pxa3xx_freq_info {
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unsigned int cpufreq_mhz;
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unsigned int core_xl : 5;
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unsigned int core_xn : 3;
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unsigned int hss : 2;
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unsigned int dmcfs : 2;
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unsigned int smcfs : 3;
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unsigned int sflfs : 2;
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unsigned int df_clkdiv : 3;
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int vcc_core; /* in mV */
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int vcc_sram; /* in mV */
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};
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#define OP(cpufreq, _xl, _xn, _hss, _dmc, _smc, _sfl, _dfi, vcore, vsram) \
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{ \
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.cpufreq_mhz = cpufreq, \
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.core_xl = _xl, \
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.core_xn = _xn, \
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.hss = HSS_##_hss##M, \
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.dmcfs = DMCFS_##_dmc##M, \
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.smcfs = SMCFS_##_smc##M, \
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.sflfs = SFLFS_##_sfl##M, \
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.df_clkdiv = _dfi, \
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.vcc_core = vcore, \
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.vcc_sram = vsram, \
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}
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static struct pxa3xx_freq_info pxa300_freqs[] = {
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/* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
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OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
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OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
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OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
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OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
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};
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static struct pxa3xx_freq_info pxa320_freqs[] = {
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/* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
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OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
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OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
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OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
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OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
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OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
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};
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static unsigned int pxa3xx_freqs_num;
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static struct pxa3xx_freq_info *pxa3xx_freqs;
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static struct cpufreq_frequency_table *pxa3xx_freqs_table;
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static int setup_freqs_table(struct cpufreq_policy *policy,
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struct pxa3xx_freq_info *freqs, int num)
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{
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struct cpufreq_frequency_table *table;
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int i;
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table = kzalloc((num + 1) * sizeof(*table), GFP_KERNEL);
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if (table == NULL)
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return -ENOMEM;
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for (i = 0; i < num; i++) {
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table[i].index = i;
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table[i].frequency = freqs[i].cpufreq_mhz * 1000;
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}
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table[num].frequency = i;
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table[num].frequency = CPUFREQ_TABLE_END;
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pxa3xx_freqs = freqs;
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pxa3xx_freqs_num = num;
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pxa3xx_freqs_table = table;
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return cpufreq_frequency_table_cpuinfo(policy, table);
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}
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static void __update_core_freq(struct pxa3xx_freq_info *info)
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{
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uint32_t mask = ACCR_XN_MASK | ACCR_XL_MASK;
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uint32_t accr = ACCR;
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uint32_t xclkcfg;
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accr &= ~(ACCR_XN_MASK | ACCR_XL_MASK | ACCR_XSPCLK_MASK);
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accr |= ACCR_XN(info->core_xn) | ACCR_XL(info->core_xl);
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/* No clock until core PLL is re-locked */
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accr |= ACCR_XSPCLK(XSPCLK_NONE);
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xclkcfg = (info->core_xn == 2) ? 0x3 : 0x2; /* turbo bit */
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ACCR = accr;
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__asm__("mcr p14, 0, %0, c6, c0, 0\n" : : "r"(xclkcfg));
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while ((ACSR & mask) != (accr & mask))
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cpu_relax();
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}
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static void __update_bus_freq(struct pxa3xx_freq_info *info)
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{
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uint32_t mask;
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uint32_t accr = ACCR;
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mask = ACCR_SMCFS_MASK | ACCR_SFLFS_MASK | ACCR_HSS_MASK |
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ACCR_DMCFS_MASK;
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accr &= ~mask;
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accr |= ACCR_SMCFS(info->smcfs) | ACCR_SFLFS(info->sflfs) |
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ACCR_HSS(info->hss) | ACCR_DMCFS(info->dmcfs);
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ACCR = accr;
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while ((ACSR & mask) != (accr & mask))
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cpu_relax();
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}
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static int pxa3xx_cpufreq_verify(struct cpufreq_policy *policy)
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{
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return cpufreq_frequency_table_verify(policy, pxa3xx_freqs_table);
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}
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static unsigned int pxa3xx_cpufreq_get(unsigned int cpu)
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{
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return get_clk_frequency_khz(0);
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}
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static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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{
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struct pxa3xx_freq_info *next;
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struct cpufreq_freqs freqs;
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unsigned long flags;
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int idx;
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if (policy->cpu != 0)
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return -EINVAL;
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/* Lookup the next frequency */
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if (cpufreq_frequency_table_target(policy, pxa3xx_freqs_table,
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target_freq, relation, &idx))
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return -EINVAL;
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next = &pxa3xx_freqs[idx];
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freqs.old = policy->cur;
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freqs.new = next->cpufreq_mhz * 1000;
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freqs.cpu = policy->cpu;
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pr_debug("CPU frequency from %d MHz to %d MHz%s\n",
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freqs.old / 1000, freqs.new / 1000,
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(freqs.old == freqs.new) ? " (skipped)" : "");
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if (freqs.old == target_freq)
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return 0;
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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local_irq_save(flags);
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__update_core_freq(next);
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__update_bus_freq(next);
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local_irq_restore(flags);
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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return 0;
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}
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static __init int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
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{
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int ret = -EINVAL;
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/* set default policy and cpuinfo */
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policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
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policy->cpuinfo.min_freq = 104000;
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policy->cpuinfo.max_freq = (cpu_is_pxa320()) ? 806000 : 624000;
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policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
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policy->cur = policy->min = policy->max = get_clk_frequency_khz(0);
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if (cpu_is_pxa300() || cpu_is_pxa310())
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ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa300_freqs));
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if (cpu_is_pxa320())
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ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa320_freqs));
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if (ret) {
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pr_err("failed to setup frequency table\n");
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return ret;
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}
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pr_info("CPUFREQ support for PXA3xx initialized\n");
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return 0;
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}
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static struct cpufreq_driver pxa3xx_cpufreq_driver = {
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.verify = pxa3xx_cpufreq_verify,
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.target = pxa3xx_cpufreq_set,
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.init = pxa3xx_cpufreq_init,
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.get = pxa3xx_cpufreq_get,
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.name = "pxa3xx-cpufreq",
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};
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static int __init cpufreq_init(void)
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{
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if (cpu_is_pxa3xx())
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return cpufreq_register_driver(&pxa3xx_cpufreq_driver);
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return 0;
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}
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module_init(cpufreq_init);
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static void __exit cpufreq_exit(void)
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{
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cpufreq_unregister_driver(&pxa3xx_cpufreq_driver);
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}
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module_exit(cpufreq_exit);
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MODULE_DESCRIPTION("CPU frequency scaling driver for PXA3xx");
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MODULE_LICENSE("GPL");
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