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thunderbolt: Get rid of __tb_switch_[en|dis]able_clx()
No need to have separate functions for these so fold them into tb_switch_clx_enable() and tb_switch_clx_disable() accordingly. No functional changes. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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parent
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commit
4f9a4f25ad
1 changed files with 42 additions and 49 deletions
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@ -205,12 +205,46 @@ static int tb_switch_mask_clx_objections(struct tb_switch *sw)
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sw->cap_lp + offset, ARRAY_SIZE(val));
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}
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static int __tb_switch_enable_clx(struct tb_switch *sw, enum tb_clx clx)
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/**
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* tb_switch_clx_enable() - Enable CLx on upstream port of specified router
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* @sw: Router to enable CLx for
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* @clx: The CLx state to enable
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*
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* Enable CLx state only for first hop router. That is the most common
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* use-case, that is intended for better thermal management, and so helps
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* to improve performance. CLx is enabled only if both sides of the link
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* support CLx, and if both sides of the link are not configured as two
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* single lane links and only if the link is not inter-domain link. The
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* complete set of conditions is described in CM Guide 1.0 section 8.1.
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*
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* Return: Returns 0 on success or an error code on failure.
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*/
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int tb_switch_clx_enable(struct tb_switch *sw, enum tb_clx clx)
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{
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struct tb_switch *root_sw = sw->tb->root_switch;
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bool up_clx_support, down_clx_support;
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struct tb_port *up, *down;
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int ret;
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if (!clx_enabled)
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return 0;
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/*
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* CLx is not enabled and validated on Intel USB4 platforms before
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* Alder Lake.
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*/
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if (root_sw->generation < 4 || tb_switch_is_tiger_lake(root_sw))
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return 0;
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switch (clx) {
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case TB_CL1:
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/* CL0s and CL1 are enabled and supported together */
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break;
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default:
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return -EOPNOTSUPP;
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}
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if (!tb_switch_clx_is_supported(sw))
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return 0;
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@ -267,47 +301,28 @@ static int __tb_switch_enable_clx(struct tb_switch *sw, enum tb_clx clx)
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}
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/**
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* tb_switch_clx_enable() - Enable CLx on upstream port of specified router
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* @sw: Router to enable CLx for
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* @clx: The CLx state to enable
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*
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* Enable CLx state only for first hop router. That is the most common
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* use-case, that is intended for better thermal management, and so helps
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* to improve performance. CLx is enabled only if both sides of the link
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* support CLx, and if both sides of the link are not configured as two
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* single lane links and only if the link is not inter-domain link. The
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* complete set of conditions is described in CM Guide 1.0 section 8.1.
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* tb_switch_clx_disable() - Disable CLx on upstream port of specified router
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* @sw: Router to disable CLx for
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* @clx: The CLx state to disable
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*
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* Return: Returns 0 on success or an error code on failure.
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*/
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int tb_switch_clx_enable(struct tb_switch *sw, enum tb_clx clx)
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int tb_switch_clx_disable(struct tb_switch *sw, enum tb_clx clx)
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{
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struct tb_switch *root_sw = sw->tb->root_switch;
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struct tb_port *up, *down;
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int ret;
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if (!clx_enabled)
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return 0;
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/*
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* CLx is not enabled and validated on Intel USB4 platforms before
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* Alder Lake.
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*/
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if (root_sw->generation < 4 || tb_switch_is_tiger_lake(root_sw))
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return 0;
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switch (clx) {
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case TB_CL1:
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/* CL0s and CL1 are enabled and supported together */
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return __tb_switch_enable_clx(sw, clx);
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break;
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default:
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return -EOPNOTSUPP;
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}
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}
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static int __tb_switch_disable_clx(struct tb_switch *sw, enum tb_clx clx)
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{
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struct tb_port *up, *down;
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int ret;
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if (!tb_switch_clx_is_supported(sw))
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return 0;
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@ -338,25 +353,3 @@ static int __tb_switch_disable_clx(struct tb_switch *sw, enum tb_clx clx)
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tb_port_dbg(up, "%s disabled\n", tb_switch_clx_name(clx));
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return 0;
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}
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/**
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* tb_switch_cls_disable() - Disable CLx on upstream port of specified router
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* @sw: Router to disable CLx for
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* @clx: The CLx state to disable
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*
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* Return: Returns 0 on success or an error code on failure.
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*/
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int tb_switch_clx_disable(struct tb_switch *sw, enum tb_clx clx)
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{
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if (!clx_enabled)
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return 0;
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switch (clx) {
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case TB_CL1:
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/* CL0s and CL1 are enabled and supported together */
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return __tb_switch_disable_clx(sw, clx);
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default:
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return -EOPNOTSUPP;
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}
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}
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