PCI: tegra194: Enable support for 256 Byte payload

Set 256 byte payload as the default in the Device Control Register to allow
the PCIe subsystem to enable 256 byte Max Payload Size when a capable link
partner is connected.

Link: https://lore.kernel.org/r/20220721142052.25971-13-vidyas@nvidia.com
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Vidya Sagar 2022-07-21 19:50:48 +05:30 committed by Bjorn Helgaas
parent 6c12e3e139
commit 4fb8e46c1b

View file

@ -839,6 +839,7 @@ static int tegra_pcie_dw_host_init(struct pcie_port *pp)
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
u32 val;
u16 val_16;
pp->bridge->ops = &tegra_pci_ops;
@ -846,6 +847,11 @@ static int tegra_pcie_dw_host_init(struct pcie_port *pp)
pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
PCI_CAP_ID_EXP);
val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
val = dw_pcie_readl_dbi(pci, PCI_IO_BASE);
val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8);
dw_pcie_writel_dbi(pci, PCI_IO_BASE, val);
@ -1632,6 +1638,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
struct device *dev = pcie->dev;
u32 val;
int ret;
u16 val_16;
if (pcie->ep_state == EP_STATE_ENABLED)
return;
@ -1749,6 +1756,12 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
PCI_CAP_ID_EXP);
val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK);