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clk: renesas: r8a779f0: Correct PFC/GPIO parent clock
[ Upstream commitd1b32a83a0
] According to the R-Car S4 Series Hardware User’s Manual Rev.0.81, the parent clock of the Pin Function (PFC/GPIO) module clock is the CP clock. As this clock is not documented to exist on R-Car S4, use the CPEX clock instead. Fixes:73421f2a48
("clk: renesas: r8a779f0: Add PFC clock") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f88ec4aede0eaf0107c8bb7b28ba719ac6cd418f.1706197415.git.geert+renesas@glider.be Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -161,7 +161,7 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
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DEF_MOD("cmt1", 911, R8A779F0_CLK_R),
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DEF_MOD("cmt2", 912, R8A779F0_CLK_R),
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DEF_MOD("cmt3", 913, R8A779F0_CLK_R),
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DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M),
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DEF_MOD("pfc0", 915, R8A779F0_CLK_CPEX),
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DEF_MOD("tsc", 919, R8A779F0_CLK_CL16M),
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DEF_MOD("rswitch2", 1505, R8A779F0_CLK_RSW2),
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DEF_MOD("ether-serdes", 1506, R8A779F0_CLK_S0D2_HSC),
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