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MIPS: Initial PCI support for Atheros 724x SoCs.
[ralf@linux-mips.org: Fixed the odd formatting of all break statements.] Signed-off-by: Rene Bolldorf <xsecute@googlemail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/3019/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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3 changed files with 196 additions and 0 deletions
21
arch/mips/include/asm/mach-ath79/pci-ath724x.h
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21
arch/mips/include/asm/mach-ath79/pci-ath724x.h
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@ -0,0 +1,21 @@
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/*
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* Atheros 724x PCI support
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*
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* Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
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#define __ASM_MACH_ATH79_PCI_ATH724X_H
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struct ath724x_pci_data {
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int irq;
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void *pdata;
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};
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void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
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#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
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@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
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obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
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ops-bcm63xx.o
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obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
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obj-$(CONFIG_SOC_AR724X) += pci-ath724x.o
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#
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# These are still pretty much in the old state, watch, go blind.
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174
arch/mips/pci/pci-ath724x.c
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arch/mips/pci/pci-ath724x.c
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/*
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* Atheros 724x PCI support
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*
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* Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/pci.h>
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#include <asm/mach-ath79/pci-ath724x.h>
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#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
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#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
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#define ATH724X_PCI_DEV_BASE 0x14000000
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#define ATH724X_PCI_MEM_BASE 0x10000000
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#define ATH724X_PCI_MEM_SIZE 0x08000000
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static DEFINE_SPINLOCK(ath724x_pci_lock);
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static struct ath724x_pci_data *pci_data;
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static int pci_data_size;
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static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t *value)
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{
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unsigned long flags, addr, tval, mask;
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if (devfn)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (where & (size - 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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spin_lock_irqsave(&ath724x_pci_lock, flags);
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switch (size) {
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case 1:
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addr = where & ~3;
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mask = 0xff000000 >> ((where % 4) * 8);
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tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
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tval = tval & ~mask;
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*value = (tval >> ((4 - (where % 4))*8));
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break;
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case 2:
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addr = where & ~3;
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mask = 0xffff0000 >> ((where % 4)*8);
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tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
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tval = tval & ~mask;
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*value = (tval >> ((4 - (where % 4))*8));
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break;
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case 4:
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*value = reg_read(ATH724X_PCI_DEV_BASE + where);
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break;
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default:
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spin_unlock_irqrestore(&ath724x_pci_lock, flags);
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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spin_unlock_irqrestore(&ath724x_pci_lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t value)
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{
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unsigned long flags, tval, addr, mask;
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if (devfn)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (where & (size - 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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spin_lock_irqsave(&ath724x_pci_lock, flags);
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switch (size) {
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case 1:
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addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
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mask = 0xff000000 >> ((where % 4)*8);
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tval = reg_read(addr);
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tval = tval & ~mask;
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tval |= (value << ((4 - (where % 4))*8)) & mask;
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reg_write(addr, tval);
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break;
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case 2:
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addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
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mask = 0xffff0000 >> ((where % 4)*8);
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tval = reg_read(addr);
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tval = tval & ~mask;
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tval |= (value << ((4 - (where % 4))*8)) & mask;
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reg_write(addr, tval);
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break;
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case 4:
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reg_write((ATH724X_PCI_DEV_BASE + where), value);
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break;
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default:
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spin_unlock_irqrestore(&ath724x_pci_lock, flags);
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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spin_unlock_irqrestore(&ath724x_pci_lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops ath724x_pci_ops = {
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.read = ath724x_pci_read,
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.write = ath724x_pci_write,
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};
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static struct resource ath724x_io_resource = {
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.name = "PCI IO space",
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_IO,
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};
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static struct resource ath724x_mem_resource = {
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.name = "PCI memory space",
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.start = ATH724X_PCI_MEM_BASE,
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.end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct pci_controller ath724x_pci_controller = {
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.pci_ops = &ath724x_pci_ops,
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.io_resource = &ath724x_io_resource,
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.mem_resource = &ath724x_mem_resource,
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};
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void ath724x_pci_add_data(struct ath724x_pci_data *data, int size)
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{
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pci_data = data;
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pci_data_size = size;
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}
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int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
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{
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unsigned int devfn = dev->devfn;
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int irq = -1;
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if (devfn > pci_data_size - 1)
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return irq;
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irq = pci_data[devfn].irq;
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return irq;
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}
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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unsigned int devfn = dev->devfn;
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if (devfn > pci_data_size - 1)
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return PCIBIOS_DEVICE_NOT_FOUND;
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dev->dev.platform_data = pci_data[devfn].pdata;
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return PCIBIOS_SUCCESSFUL;
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}
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static int __init ath724x_pcibios_init(void)
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{
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register_pci_controller(&ath724x_pci_controller);
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return PCIBIOS_SUCCESSFUL;
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}
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arch_initcall(ath724x_pcibios_init);
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