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MIPS: ath79: Fix the DDR control initialization on ar71xx and ar934x
The DDR control initialization needs to know the SoC type, however ath79_detect_sys_type() was called after ath79_ddr_ctrl_init(). Reverse the order to fix the DDR control initialization on ar71xx and ar934x. Signed-off-by: Alban Bedel <albeu@free.fr> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> CC: stable@vger.kernel.org # v4.2+ Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11500/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -216,9 +216,9 @@ void __init plat_mem_setup(void)
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AR71XX_RESET_SIZE);
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ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
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AR71XX_PLL_SIZE);
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ath79_detect_sys_type();
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ath79_ddr_ctrl_init();
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ath79_detect_sys_type();
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if (mips_machtype != ATH79_MACH_GENERIC_OF)
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detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
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