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staging: r8188eu: remove ODM_SetBBReg()
ODM_SetBBReg() is just a wrapper around rtl8188e_PHY_SetBBReg(). Remove ODM_SetBBReg() and call rtl8188e_PHY_SetBBReg() directly. Signed-off-by: Michael Straube <straube.linux@gmail.com> Link: https://lore.kernel.org/r/20211229205108.26373-7-straube.linux@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Michael Straube
Greg Kroah-Hartman
parent
8aedc08edf
commit
502ddefa50
6 changed files with 131 additions and 149 deletions
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@ -329,17 +329,17 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
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/* wtite new elements A, C, D to regC88 and regC9C, element B is always 0 */
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value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
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ODM_SetBBReg(dm_odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);
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rtl8188e_PHY_SetBBReg(Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);
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value32 = (ele_C & 0x000003C0) >> 6;
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ODM_SetBBReg(dm_odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32);
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rtl8188e_PHY_SetBBReg(Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, value32);
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value32 = ((X * ele_D) >> 7) & 0x01;
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ODM_SetBBReg(dm_odm, rOFDM0_ECCAThreshold, BIT(28), value32);
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rtl8188e_PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT(28), value32);
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} else {
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ODM_SetBBReg(dm_odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[(u8)OFDM_index[1]]);
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ODM_SetBBReg(dm_odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);
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ODM_SetBBReg(dm_odm, rOFDM0_ECCAThreshold, BIT(28), 0x00);
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rtl8188e_PHY_SetBBReg(Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[(u8)OFDM_index[1]]);
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rtl8188e_PHY_SetBBReg(Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);
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rtl8188e_PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT(28), 0x00);
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}
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}
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}
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@ -365,22 +365,20 @@ phy_PathA_IQK_8188E(struct adapter *adapt)
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{
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u32 regeac, regE94, regE9C;
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u8 result = 0x00;
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struct hal_data_8188e *pHalData = &adapt->haldata;
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struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
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/* 1 Tx IQK */
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/* path-A IQK setting */
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ODM_SetBBReg(dm_odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
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ODM_SetBBReg(dm_odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
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ODM_SetBBReg(dm_odm, rTx_IQK_PI_A, bMaskDWord, 0x8214032a);
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ODM_SetBBReg(dm_odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000);
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rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
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rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
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rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x8214032a);
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rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000);
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/* LO calibration setting */
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ODM_SetBBReg(dm_odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
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rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
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/* One shot, path A LOK & IQK */
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ODM_SetBBReg(dm_odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
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ODM_SetBBReg(dm_odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
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rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
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rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
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/* delay x ms */
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/* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
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@ -403,12 +401,10 @@ phy_PathA_RxIQK(struct adapter *adapt)
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{
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u32 regeac, regE94, regE9C, regEA4, u4tmp;
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u8 result = 0x00;
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struct hal_data_8188e *pHalData = &adapt->haldata;
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struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
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/* 1 Get TXIMR setting */
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/* modify RXIQK mode table */
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ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
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rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);
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rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0);
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rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
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rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f);
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@ -418,24 +414,24 @@ phy_PathA_RxIQK(struct adapter *adapt)
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rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980);
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rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000);
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ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
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rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
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/* IQK setting */
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ODM_SetBBReg(dm_odm, rTx_IQK, bMaskDWord, 0x01007c00);
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ODM_SetBBReg(dm_odm, rRx_IQK, bMaskDWord, 0x81004800);
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rtl8188e_PHY_SetBBReg(adapt, rTx_IQK, bMaskDWord, 0x01007c00);
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rtl8188e_PHY_SetBBReg(adapt, rRx_IQK, bMaskDWord, 0x81004800);
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/* path-A IQK setting */
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ODM_SetBBReg(dm_odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
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ODM_SetBBReg(dm_odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
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ODM_SetBBReg(dm_odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f);
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ODM_SetBBReg(dm_odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000);
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rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
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rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
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rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f);
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rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000);
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/* LO calibration setting */
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ODM_SetBBReg(dm_odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
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rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
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/* One shot, path A LOK & IQK */
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ODM_SetBBReg(dm_odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
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ODM_SetBBReg(dm_odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
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rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
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rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
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/* delay x ms */
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ODM_delay_ms(IQK_DELAY_TIME_88E);
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@ -453,32 +449,32 @@ phy_PathA_RxIQK(struct adapter *adapt)
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return result;
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u4tmp = 0x80007C00 | (regE94 & 0x3FF0000) | ((regE9C & 0x3FF0000) >> 16);
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ODM_SetBBReg(dm_odm, rTx_IQK, bMaskDWord, u4tmp);
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rtl8188e_PHY_SetBBReg(adapt, rTx_IQK, bMaskDWord, u4tmp);
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/* 1 RX IQK */
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/* modify RXIQK mode table */
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ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
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rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);
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rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0);
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rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);
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rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f);
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rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa);
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ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
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rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
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/* IQK setting */
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ODM_SetBBReg(dm_odm, rRx_IQK, bMaskDWord, 0x01004800);
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rtl8188e_PHY_SetBBReg(adapt, rRx_IQK, bMaskDWord, 0x01004800);
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/* path-A IQK setting */
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ODM_SetBBReg(dm_odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
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ODM_SetBBReg(dm_odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
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ODM_SetBBReg(dm_odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c05);
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ODM_SetBBReg(dm_odm, rRx_IQK_PI_A, bMaskDWord, 0x28160c1f);
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rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
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rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
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rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x82160c05);
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rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160c1f);
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/* LO calibration setting */
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ODM_SetBBReg(dm_odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
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rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
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/* One shot, path A LOK & IQK */
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ODM_SetBBReg(dm_odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
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ODM_SetBBReg(dm_odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
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rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
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rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
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/* delay x ms */
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/* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
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@ -491,7 +487,7 @@ phy_PathA_RxIQK(struct adapter *adapt)
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regEA4 = rtl8188e_PHY_QueryBBReg(adapt, rRx_Power_Before_IQK_A_2, bMaskDWord);
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/* reload RF 0xdf */
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ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
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rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);
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rtl8188e_PHY_SetRFReg(adapt, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180);
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if (!(regeac & BIT(27)) && /* if Tx is OK, check whether Rx is OK */
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@ -506,8 +502,6 @@ static void patha_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8], u
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{
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u32 Oldval_0, X, TX0_A, reg;
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s32 Y, TX0_C;
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struct hal_data_8188e *pHalData = &adapt->haldata;
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struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
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if (final_candidate == 0xFF) {
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return;
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@ -518,31 +512,31 @@ static void patha_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8], u
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if ((X & 0x00000200) != 0)
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X = X | 0xFFFFFC00;
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TX0_A = (X * Oldval_0) >> 8;
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ODM_SetBBReg(dm_odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);
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rtl8188e_PHY_SetBBReg(adapt, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);
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ODM_SetBBReg(dm_odm, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0 >> 7) & 0x1));
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rtl8188e_PHY_SetBBReg(adapt, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0 >> 7) & 0x1));
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Y = result[final_candidate][1];
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if ((Y & 0x00000200) != 0)
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Y = Y | 0xFFFFFC00;
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TX0_C = (Y * Oldval_0) >> 8;
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ODM_SetBBReg(dm_odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C & 0x3C0) >> 6));
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ODM_SetBBReg(dm_odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C & 0x3F));
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rtl8188e_PHY_SetBBReg(adapt, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C & 0x3C0) >> 6));
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rtl8188e_PHY_SetBBReg(adapt, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C & 0x3F));
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ODM_SetBBReg(dm_odm, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0 >> 7) & 0x1));
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rtl8188e_PHY_SetBBReg(adapt, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0 >> 7) & 0x1));
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if (txonly)
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return;
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reg = result[final_candidate][2];
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ODM_SetBBReg(dm_odm, rOFDM0_XARxIQImbalance, 0x3FF, reg);
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rtl8188e_PHY_SetBBReg(adapt, rOFDM0_XARxIQImbalance, 0x3FF, reg);
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reg = result[final_candidate][3] & 0x3F;
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ODM_SetBBReg(dm_odm, rOFDM0_XARxIQImbalance, 0xFC00, reg);
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rtl8188e_PHY_SetBBReg(adapt, rOFDM0_XARxIQImbalance, 0xFC00, reg);
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reg = (result[final_candidate][3] >> 6) & 0xF;
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ODM_SetBBReg(dm_odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg);
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rtl8188e_PHY_SetBBReg(adapt, rOFDM0_RxIQExtAnta, 0xF0000000, reg);
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}
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}
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@ -572,11 +566,9 @@ static void _PHY_SaveMACRegisters(
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static void reload_adda_reg(struct adapter *adapt, u32 *ADDAReg, u32 *ADDABackup, u32 RegiesterNum)
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{
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u32 i;
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struct hal_data_8188e *pHalData = &adapt->haldata;
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struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
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for (i = 0; i < RegiesterNum; i++)
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ODM_SetBBReg(dm_odm, ADDAReg[i], bMaskDWord, ADDABackup[i]);
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rtl8188e_PHY_SetBBReg(adapt, ADDAReg[i], bMaskDWord, ADDABackup[i]);
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}
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static void
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@ -600,13 +592,11 @@ _PHY_PathADDAOn(
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u32 *ADDAReg)
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{
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u32 i;
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struct hal_data_8188e *pHalData = &adapt->haldata;
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struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
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ODM_SetBBReg(dm_odm, ADDAReg[0], bMaskDWord, 0x0b1b25a0);
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rtl8188e_PHY_SetBBReg(adapt, ADDAReg[0], bMaskDWord, 0x0b1b25a0);
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for (i = 1; i < IQK_ADDA_REG_NUM; i++)
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ODM_SetBBReg(dm_odm, ADDAReg[i], bMaskDWord, 0x0bdb25a0);
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rtl8188e_PHY_SetBBReg(adapt, ADDAReg[i], bMaskDWord, 0x0bdb25a0);
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}
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void
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@ -632,12 +622,10 @@ static void _PHY_PIModeSwitch(
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)
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{
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u32 mode;
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struct hal_data_8188e *pHalData = &adapt->haldata;
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struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
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mode = PIMode ? 0x01000100 : 0x01000000;
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ODM_SetBBReg(dm_odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode);
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ODM_SetBBReg(dm_odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode);
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rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode);
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rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode);
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}
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static bool phy_SimularityCompare_8188E(
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@ -766,28 +754,28 @@ static void phy_IQCalibrate_8188E(struct adapter *adapt, s32 result[][8], u8 t)
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}
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/* BB setting */
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ODM_SetBBReg(dm_odm, rFPGA0_RFMOD, BIT(24), 0x00);
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ODM_SetBBReg(dm_odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
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ODM_SetBBReg(dm_odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
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ODM_SetBBReg(dm_odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
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rtl8188e_PHY_SetBBReg(adapt, rFPGA0_RFMOD, BIT(24), 0x00);
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rtl8188e_PHY_SetBBReg(adapt, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
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rtl8188e_PHY_SetBBReg(adapt, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
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rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
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ODM_SetBBReg(dm_odm, rFPGA0_XAB_RFInterfaceSW, BIT(10), 0x01);
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ODM_SetBBReg(dm_odm, rFPGA0_XAB_RFInterfaceSW, BIT(26), 0x01);
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ODM_SetBBReg(dm_odm, rFPGA0_XA_RFInterfaceOE, BIT(10), 0x00);
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ODM_SetBBReg(dm_odm, rFPGA0_XB_RFInterfaceOE, BIT(10), 0x00);
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rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(10), 0x01);
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rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(26), 0x01);
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rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XA_RFInterfaceOE, BIT(10), 0x00);
|
||||
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XB_RFInterfaceOE, BIT(10), 0x00);
|
||||
|
||||
/* MAC settings */
|
||||
_PHY_MACSettingCalibration(adapt, IQK_MAC_REG, dm_odm->RFCalibrateInfo.IQK_MAC_backup);
|
||||
|
||||
/* Page B init */
|
||||
/* AP or IQK */
|
||||
ODM_SetBBReg(dm_odm, rConfig_AntA, bMaskDWord, 0x0f600000);
|
||||
rtl8188e_PHY_SetBBReg(adapt, rConfig_AntA, bMaskDWord, 0x0f600000);
|
||||
|
||||
|
||||
/* IQ calibration setting */
|
||||
ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
|
||||
ODM_SetBBReg(dm_odm, rTx_IQK, bMaskDWord, 0x01007c00);
|
||||
ODM_SetBBReg(dm_odm, rRx_IQK, bMaskDWord, 0x81004800);
|
||||
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
|
||||
rtl8188e_PHY_SetBBReg(adapt, rTx_IQK, bMaskDWord, 0x01007c00);
|
||||
rtl8188e_PHY_SetBBReg(adapt, rRx_IQK, bMaskDWord, 0x81004800);
|
||||
|
||||
for (i = 0; i < retryCount; i++) {
|
||||
PathAOK = phy_PathA_IQK_8188E(adapt);
|
||||
|
|
@ -808,7 +796,7 @@ static void phy_IQCalibrate_8188E(struct adapter *adapt, s32 result[][8], u8 t)
|
|||
}
|
||||
|
||||
/* Back to BB mode, load original value */
|
||||
ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0);
|
||||
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0);
|
||||
|
||||
if (t != 0) {
|
||||
if (!dm_odm->RFCalibrateInfo.bRfPiEnable) {
|
||||
|
|
@ -825,11 +813,11 @@ static void phy_IQCalibrate_8188E(struct adapter *adapt, s32 result[][8], u8 t)
|
|||
reload_adda_reg(adapt, IQK_BB_REG_92C, dm_odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
|
||||
|
||||
/* Restore RX initial gain */
|
||||
ODM_SetBBReg(dm_odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3);
|
||||
rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3);
|
||||
|
||||
/* load 0xe30 IQC default value */
|
||||
ODM_SetBBReg(dm_odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
|
||||
ODM_SetBBReg(dm_odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
|
||||
rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
|
||||
rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -302,9 +302,10 @@ void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm)
|
|||
void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI)
|
||||
{
|
||||
struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
|
||||
struct adapter *adapter = pDM_Odm->Adapter;
|
||||
|
||||
if (pDM_DigTable->CurIGValue != CurrentIGI) {
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N, CurrentIGI);
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N, CurrentIGI);
|
||||
pDM_DigTable->CurIGValue = CurrentIGI;
|
||||
}
|
||||
}
|
||||
|
|
@ -484,8 +485,8 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm)
|
|||
return;
|
||||
|
||||
/* hold ofdm counter */
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); /* hold page C counter */
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); /* hold page D counter */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); /* hold page C counter */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); /* hold page D counter */
|
||||
|
||||
ret_value = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
|
||||
FalseAlmCnt->Cnt_Fast_Fsync = (ret_value & 0xffff);
|
||||
|
|
@ -508,8 +509,8 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm)
|
|||
FalseAlmCnt->Cnt_BW_USC = ((ret_value & 0xffff0000) >> 16);
|
||||
|
||||
/* hold cck counter */
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);
|
||||
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);
|
||||
|
||||
ret_value = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
|
||||
FalseAlmCnt->Cnt_Cck_fail = ret_value;
|
||||
|
|
@ -620,19 +621,19 @@ void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal)
|
|||
|
||||
if (pDM_PSTable->pre_rf_state != pDM_PSTable->cur_rf_state) {
|
||||
if (pDM_PSTable->cur_rf_state == RF_Save) {
|
||||
ODM_SetBBReg(pDM_Odm, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */
|
||||
ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), 0); /* RegC70[3]=1'b0 */
|
||||
ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */
|
||||
ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */
|
||||
ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */
|
||||
ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0); /* Reg818[28]=1'b0 */
|
||||
ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x1); /* Reg818[28]=1'b1 */
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0xc70, BIT(3), 0); /* RegC70[3]=1'b0 */
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0x818, BIT(28), 0x0); /* Reg818[28]=1'b0 */
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0x818, BIT(28), 0x1); /* Reg818[28]=1'b1 */
|
||||
} else {
|
||||
ODM_SetBBReg(pDM_Odm, 0x874, 0x1CC000, pDM_PSTable->reg_874);
|
||||
ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), pDM_PSTable->reg_c70);
|
||||
ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->reg_85c);
|
||||
ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->reg_a74);
|
||||
ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0);
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0x874, 0x1CC000, pDM_PSTable->reg_874);
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0xc70, BIT(3), pDM_PSTable->reg_c70);
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0x85c, 0xFF000000, pDM_PSTable->reg_85c);
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0xa74, 0xF000, pDM_PSTable->reg_a74);
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0x818, BIT(28), 0x0);
|
||||
}
|
||||
pDM_PSTable->pre_rf_state = pDM_PSTable->cur_rf_state;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -12,17 +12,17 @@ static void odm_RX_HWAntDivInit(struct odm_dm_struct *dm_odm)
|
|||
value32 = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
|
||||
/* Pin Settings */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); /* Regb2c[22]=1'b0 disable CS/CG switch */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); /* Regb2c[22]=1'b0 disable CS/CG switch */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */
|
||||
/* OFDM Settings */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);
|
||||
/* CCK Settings */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
|
||||
ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201); /* antenna mapping table */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201); /* antenna mapping table */
|
||||
}
|
||||
|
||||
static void odm_TRX_HWAntDivInit(struct odm_dm_struct *dm_odm)
|
||||
|
|
@ -34,25 +34,25 @@ static void odm_TRX_HWAntDivInit(struct odm_dm_struct *dm_odm)
|
|||
value32 = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
|
||||
/* Pin Settings */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */
|
||||
/* OFDM Settings */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);
|
||||
/* CCK Settings */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
|
||||
/* Tx Settings */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0); /* Reg80c[21]=1'b0 from TX Reg */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0); /* Reg80c[21]=1'b0 from TX Reg */
|
||||
ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);
|
||||
|
||||
/* antenna mapping table */
|
||||
if (!dm_odm->bIsMPChip) { /* testchip */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_RX_DEFUALT_A_11N, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_RX_DEFUALT_A_11N, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
|
||||
} else { /* MPchip */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_ANT_MAPPING1_11N, bMaskDWord, 0x0201); /* Reg914=3'b010, Reg915=3'b001 */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord, 0x0201); /* Reg914=3'b010, Reg915=3'b001 */
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -71,28 +71,28 @@ static void odm_FastAntTrainingInit(struct odm_dm_struct *dm_odm)
|
|||
rtl8188e_PHY_SetBBReg(adapter, 0x7b4, 0xFFFF, 0);
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0x7b0, bMaskDWord, 0);
|
||||
|
||||
ODM_SetBBReg(dm_odm, 0x870, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
|
||||
ODM_SetBBReg(dm_odm, 0x864, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */
|
||||
ODM_SetBBReg(dm_odm, 0xb2c, BIT(22), 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
|
||||
ODM_SetBBReg(dm_odm, 0xb2c, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */
|
||||
ODM_SetBBReg(dm_odm, 0xca4, bMaskDWord, 0x000000a0);
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0x870, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0xb2c, BIT(22), 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0xb2c, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0xca4, bMaskDWord, 0x000000a0);
|
||||
|
||||
if (!dm_odm->bIsMPChip) { /* testchip */
|
||||
ODM_SetBBReg(dm_odm, 0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
|
||||
ODM_SetBBReg(dm_odm, 0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
|
||||
} else { /* MPchip */
|
||||
ODM_SetBBReg(dm_odm, 0x914, bMaskByte0, 1);
|
||||
ODM_SetBBReg(dm_odm, 0x914, bMaskByte1, 2);
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0x914, bMaskByte0, 1);
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0x914, bMaskByte1, 2);
|
||||
}
|
||||
|
||||
/* Default Ant Setting when no fast training */
|
||||
ODM_SetBBReg(dm_odm, 0x80c, BIT(21), 1); /* Reg80c[21]=1'b1 from TX Info */
|
||||
ODM_SetBBReg(dm_odm, 0x864, BIT(5) | BIT(4) | BIT(3), 0); /* Default RX */
|
||||
ODM_SetBBReg(dm_odm, 0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0x80c, BIT(21), 1); /* Reg80c[21]=1'b1 from TX Info */
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(5) | BIT(4) | BIT(3), 0); /* Default RX */
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */
|
||||
|
||||
/* Enter Training state */
|
||||
ODM_SetBBReg(dm_odm, 0x864, BIT(2) | BIT(1) | BIT(0), 1);
|
||||
ODM_SetBBReg(dm_odm, 0xc50, BIT(7), 1); /* RegC50[7]=1'b1 enable HW AntDiv */
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(2) | BIT(1) | BIT(0), 1);
|
||||
rtl8188e_PHY_SetBBReg(adapter, 0xc50, BIT(7), 1); /* RegC50[7]=1'b1 enable HW AntDiv */
|
||||
}
|
||||
|
||||
void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *dm_odm)
|
||||
|
|
@ -121,13 +121,13 @@ void ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant)
|
|||
}
|
||||
|
||||
if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT(4) | BIT(3), DefaultAnt); /* Default RX */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(8) | BIT(7) | BIT(6), OptionalAnt); /* Optional RX */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_ANTSEL_CTRL_11N, BIT(14) | BIT(13) | BIT(12), DefaultAnt); /* Default TX */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT(4) | BIT(3), DefaultAnt); /* Default RX */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(8) | BIT(7) | BIT(6), OptionalAnt); /* Optional RX */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTSEL_CTRL_11N, BIT(14) | BIT(13) | BIT(12), DefaultAnt); /* Default TX */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RESP_TX_11N, BIT(6) | BIT(7), DefaultAnt); /* Resp Tx */
|
||||
} else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT(4) | BIT(3), DefaultAnt); /* Default RX */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(8) | BIT(7) | BIT(6), OptionalAnt); /* Optional RX */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT(4) | BIT(3), DefaultAnt); /* Default RX */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(8) | BIT(7) | BIT(6), OptionalAnt); /* Optional RX */
|
||||
}
|
||||
}
|
||||
dm_fat_tbl->RxIdleAnt = Ant;
|
||||
|
|
@ -236,24 +236,26 @@ static void odm_HWAntDiv(struct odm_dm_struct *dm_odm)
|
|||
void ODM_AntennaDiversity_88E(struct odm_dm_struct *dm_odm)
|
||||
{
|
||||
struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
|
||||
struct adapter *adapter = dm_odm->Adapter;
|
||||
|
||||
if (!(dm_odm->SupportAbility & ODM_BB_ANT_DIV))
|
||||
return;
|
||||
if (!dm_odm->bLinked) {
|
||||
if (dm_fat_tbl->bBecomeLinked) {
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_IGI_A_11N, BIT(7), 0); /* RegC50[7]=1'b1 enable HW AntDiv */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT(15), 0); /* Enable CCK AntDiv */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0); /* RegC50[7]=1'b1 enable HW AntDiv */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT(15), 0); /* Enable CCK AntDiv */
|
||||
if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0); /* Reg80c[21]=1'b0 from TX Reg */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0); /* Reg80c[21]=1'b0 from TX Reg */
|
||||
dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
|
||||
}
|
||||
return;
|
||||
} else {
|
||||
if (!dm_fat_tbl->bBecomeLinked) {
|
||||
/* Because HW AntDiv is disabled before Link, we enable HW AntDiv after link */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_IGI_A_11N, BIT(7), 1); /* RegC50[7]=1'b1 enable HW AntDiv */
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT(15), 1); /* Enable CCK AntDiv */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT(7), 1); /* RegC50[7]=1'b1 enable HW AntDiv */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT(15), 1); /* Enable CCK AntDiv */
|
||||
if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
|
||||
ODM_SetBBReg(dm_odm, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 1); /* Reg80c[21]=1'b1 from TX Info */
|
||||
rtl8188e_PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 1); /* Reg80c[21]=1'b1 from TX Info */
|
||||
dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ void odm_ConfigMAC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u8 Data)
|
|||
|
||||
void odm_ConfigBB_AGC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data)
|
||||
{
|
||||
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
|
||||
rtl8188e_PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data);
|
||||
/* Add 1us delay between BB/RF register setting. */
|
||||
ODM_delay_us(1);
|
||||
}
|
||||
|
|
@ -82,7 +82,7 @@ void odm_ConfigBB_PHY_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask
|
|||
} else {
|
||||
if (Addr == 0xa24)
|
||||
pDM_Odm->RFCalibrateInfo.RegA24 = Data;
|
||||
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
|
||||
rtl8188e_PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data);
|
||||
|
||||
/* Add 1us delay between BB/RF register setting. */
|
||||
ODM_delay_us(1);
|
||||
|
|
|
|||
|
|
@ -4,12 +4,6 @@
|
|||
#include "../include/odm_precomp.h"
|
||||
/* ODM IO Relative API. */
|
||||
|
||||
void ODM_SetBBReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask, u32 Data)
|
||||
{
|
||||
struct adapter *Adapter = pDM_Odm->Adapter;
|
||||
rtl8188e_PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);
|
||||
}
|
||||
|
||||
/* ODM Memory relative API. */
|
||||
s32 ODM_CompareMemory(struct odm_dm_struct *pDM_Odm, void *pBuf1, void *pBuf2, u32 length)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -12,9 +12,6 @@ typedef void (*RT_WORKITEM_CALL_BACK)(void *pContext);
|
|||
|
||||
/* =========== EXtern Function Prototype */
|
||||
|
||||
void ODM_SetBBReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr,
|
||||
u32 BitMask, u32 Data);
|
||||
|
||||
/* Memory Relative Function. */
|
||||
s32 ODM_CompareMemory(struct odm_dm_struct *pDM_Odm, void *pBuf1, void *pBuf2,
|
||||
u32 length);
|
||||
|
|
|
|||
Loading…
Reference in a new issue