mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-25 02:09:42 +00:00
Merge branch 'fix' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
This commit is contained in:
commit
50ad5f591b
197 changed files with 11715 additions and 773 deletions
|
@ -1,4 +1,4 @@
|
||||||
What: /sys/class/usb_host/usb_hostN/wusb_chid
|
What: /sys/class/uwb_rc/uwbN/wusbhc/wusb_chid
|
||||||
Date: July 2008
|
Date: July 2008
|
||||||
KernelVersion: 2.6.27
|
KernelVersion: 2.6.27
|
||||||
Contact: David Vrabel <david.vrabel@csr.com>
|
Contact: David Vrabel <david.vrabel@csr.com>
|
||||||
|
@ -9,7 +9,7 @@ Description:
|
||||||
|
|
||||||
Set an all zero CHID to stop the host controller.
|
Set an all zero CHID to stop the host controller.
|
||||||
|
|
||||||
What: /sys/class/usb_host/usb_hostN/wusb_trust_timeout
|
What: /sys/class/uwb_rc/uwbN/wusbhc/wusb_trust_timeout
|
||||||
Date: July 2008
|
Date: July 2008
|
||||||
KernelVersion: 2.6.27
|
KernelVersion: 2.6.27
|
||||||
Contact: David Vrabel <david.vrabel@csr.com>
|
Contact: David Vrabel <david.vrabel@csr.com>
|
|
@ -64,14 +64,14 @@ be used to view the printk buffer of a remote machine, even with live update.
|
||||||
|
|
||||||
Bernhard Kaindl enhanced firescope to support accessing 64-bit machines
|
Bernhard Kaindl enhanced firescope to support accessing 64-bit machines
|
||||||
from 32-bit firescope and vice versa:
|
from 32-bit firescope and vice versa:
|
||||||
- ftp://ftp.suse.de/private/bk/firewire/tools/firescope-0.2.2.tar.bz2
|
- http://halobates.de/firewire/firescope-0.2.2.tar.bz2
|
||||||
|
|
||||||
and he implemented fast system dump (alpha version - read README.txt):
|
and he implemented fast system dump (alpha version - read README.txt):
|
||||||
- ftp://ftp.suse.de/private/bk/firewire/tools/firedump-0.1.tar.bz2
|
- http://halobates.de/firewire/firedump-0.1.tar.bz2
|
||||||
|
|
||||||
There is also a gdb proxy for firewire which allows to use gdb to access
|
There is also a gdb proxy for firewire which allows to use gdb to access
|
||||||
data which can be referenced from symbols found by gdb in vmlinux:
|
data which can be referenced from symbols found by gdb in vmlinux:
|
||||||
- ftp://ftp.suse.de/private/bk/firewire/tools/fireproxy-0.33.tar.bz2
|
- http://halobates.de/firewire/fireproxy-0.33.tar.bz2
|
||||||
|
|
||||||
The latest version of this gdb proxy (fireproxy-0.34) can communicate (not
|
The latest version of this gdb proxy (fireproxy-0.34) can communicate (not
|
||||||
yet stable) with kgdb over an memory-based communication module (kgdbom).
|
yet stable) with kgdb over an memory-based communication module (kgdbom).
|
||||||
|
@ -178,7 +178,7 @@ Step-by-step instructions for using firescope with early OHCI initialization:
|
||||||
|
|
||||||
Notes
|
Notes
|
||||||
-----
|
-----
|
||||||
Documentation and specifications: ftp://ftp.suse.de/private/bk/firewire/docs
|
Documentation and specifications: http://halobates.de/firewire/
|
||||||
|
|
||||||
FireWire is a trademark of Apple Inc. - for more information please refer to:
|
FireWire is a trademark of Apple Inc. - for more information please refer to:
|
||||||
http://en.wikipedia.org/wiki/FireWire
|
http://en.wikipedia.org/wiki/FireWire
|
||||||
|
|
|
@ -451,3 +451,33 @@ Why: OSS sound_core grabs all legacy minors (0-255) of SOUND_MAJOR
|
||||||
will also allow making ALSA OSS emulation independent of
|
will also allow making ALSA OSS emulation independent of
|
||||||
sound_core. The dependency will be broken then too.
|
sound_core. The dependency will be broken then too.
|
||||||
Who: Tejun Heo <tj@kernel.org>
|
Who: Tejun Heo <tj@kernel.org>
|
||||||
|
|
||||||
|
----------------------------
|
||||||
|
|
||||||
|
What: Support for VMware's guest paravirtuliazation technique [VMI] will be
|
||||||
|
dropped.
|
||||||
|
When: 2.6.37 or earlier.
|
||||||
|
Why: With the recent innovations in CPU hardware acceleration technologies
|
||||||
|
from Intel and AMD, VMware ran a few experiments to compare these
|
||||||
|
techniques to guest paravirtualization technique on VMware's platform.
|
||||||
|
These hardware assisted virtualization techniques have outperformed the
|
||||||
|
performance benefits provided by VMI in most of the workloads. VMware
|
||||||
|
expects that these hardware features will be ubiquitous in a couple of
|
||||||
|
years, as a result, VMware has started a phased retirement of this
|
||||||
|
feature from the hypervisor. We will be removing this feature from the
|
||||||
|
Kernel too. Right now we are targeting 2.6.37 but can retire earlier if
|
||||||
|
technical reasons (read opportunity to remove major chunk of pvops)
|
||||||
|
arise.
|
||||||
|
|
||||||
|
Please note that VMI has always been an optimization and non-VMI kernels
|
||||||
|
still work fine on VMware's platform.
|
||||||
|
Latest versions of VMware's product which support VMI are,
|
||||||
|
Workstation 7.0 and VSphere 4.0 on ESX side, future maintainence
|
||||||
|
releases for these products will continue supporting VMI.
|
||||||
|
|
||||||
|
For more details about VMI retirement take a look at this,
|
||||||
|
http://blogs.vmware.com/guestosguide/2009/09/vmi-retirement.html
|
||||||
|
|
||||||
|
Who: Alok N Kataria <akataria@vmware.com>
|
||||||
|
|
||||||
|
----------------------------
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
Using flexible arrays in the kernel
|
Using flexible arrays in the kernel
|
||||||
Last updated for 2.6.31
|
Last updated for 2.6.32
|
||||||
Jonathan Corbet <corbet@lwn.net>
|
Jonathan Corbet <corbet@lwn.net>
|
||||||
|
|
||||||
Large contiguous memory allocations can be unreliable in the Linux kernel.
|
Large contiguous memory allocations can be unreliable in the Linux kernel.
|
||||||
|
@ -40,6 +40,13 @@ argument is passed directly to the internal memory allocation calls. With
|
||||||
the current code, using flags to ask for high memory is likely to lead to
|
the current code, using flags to ask for high memory is likely to lead to
|
||||||
notably unpleasant side effects.
|
notably unpleasant side effects.
|
||||||
|
|
||||||
|
It is also possible to define flexible arrays at compile time with:
|
||||||
|
|
||||||
|
DEFINE_FLEX_ARRAY(name, element_size, total);
|
||||||
|
|
||||||
|
This macro will result in a definition of an array with the given name; the
|
||||||
|
element size and total will be checked for validity at compile time.
|
||||||
|
|
||||||
Storing data into a flexible array is accomplished with a call to:
|
Storing data into a flexible array is accomplished with a call to:
|
||||||
|
|
||||||
int flex_array_put(struct flex_array *array, unsigned int element_nr,
|
int flex_array_put(struct flex_array *array, unsigned int element_nr,
|
||||||
|
@ -76,16 +83,30 @@ particular element has never been allocated.
|
||||||
Note that it is possible to get back a valid pointer for an element which
|
Note that it is possible to get back a valid pointer for an element which
|
||||||
has never been stored in the array. Memory for array elements is allocated
|
has never been stored in the array. Memory for array elements is allocated
|
||||||
one page at a time; a single allocation could provide memory for several
|
one page at a time; a single allocation could provide memory for several
|
||||||
adjacent elements. The flexible array code does not know if a specific
|
adjacent elements. Flexible array elements are normally initialized to the
|
||||||
element has been written; it only knows if the associated memory is
|
value FLEX_ARRAY_FREE (defined as 0x6c in <linux/poison.h>), so errors
|
||||||
present. So a flex_array_get() call on an element which was never stored
|
involving that number probably result from use of unstored array entries.
|
||||||
in the array has the potential to return a pointer to random data. If the
|
Note that, if array elements are allocated with __GFP_ZERO, they will be
|
||||||
caller does not have a separate way to know which elements were actually
|
initialized to zero and this poisoning will not happen.
|
||||||
stored, it might be wise, at least, to add GFP_ZERO to the flags argument
|
|
||||||
to ensure that all elements are zeroed.
|
|
||||||
|
|
||||||
There is no way to remove a single element from the array. It is possible,
|
Individual elements in the array can be cleared with:
|
||||||
though, to remove all elements with a call to:
|
|
||||||
|
int flex_array_clear(struct flex_array *array, unsigned int element_nr);
|
||||||
|
|
||||||
|
This function will set the given element to FLEX_ARRAY_FREE and return
|
||||||
|
zero. If storage for the indicated element is not allocated for the array,
|
||||||
|
flex_array_clear() will return -EINVAL instead. Note that clearing an
|
||||||
|
element does not release the storage associated with it; to reduce the
|
||||||
|
allocated size of an array, call:
|
||||||
|
|
||||||
|
int flex_array_shrink(struct flex_array *array);
|
||||||
|
|
||||||
|
The return value will be the number of pages of memory actually freed.
|
||||||
|
This function works by scanning the array for pages containing nothing but
|
||||||
|
FLEX_ARRAY_FREE bytes, so (1) it can be expensive, and (2) it will not work
|
||||||
|
if the array's pages are allocated with __GFP_ZERO.
|
||||||
|
|
||||||
|
It is possible to remove all elements of an array with a call to:
|
||||||
|
|
||||||
void flex_array_free_parts(struct flex_array *array);
|
void flex_array_free_parts(struct flex_array *array);
|
||||||
|
|
||||||
|
|
16
MAINTAINERS
16
MAINTAINERS
|
@ -2615,6 +2615,7 @@ L: linux1394-devel@lists.sourceforge.net
|
||||||
W: http://www.linux1394.org/
|
W: http://www.linux1394.org/
|
||||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394/linux1394-2.6.git
|
T: git git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394/linux1394-2.6.git
|
||||||
S: Maintained
|
S: Maintained
|
||||||
|
F: Documentation/debugging-via-ohci1394.txt
|
||||||
F: drivers/ieee1394/
|
F: drivers/ieee1394/
|
||||||
|
|
||||||
IEEE 1394 RAW I/O DRIVER
|
IEEE 1394 RAW I/O DRIVER
|
||||||
|
@ -3666,6 +3667,7 @@ NETWORKING [GENERAL]
|
||||||
M: "David S. Miller" <davem@davemloft.net>
|
M: "David S. Miller" <davem@davemloft.net>
|
||||||
L: netdev@vger.kernel.org
|
L: netdev@vger.kernel.org
|
||||||
W: http://www.linuxfoundation.org/en/Net
|
W: http://www.linuxfoundation.org/en/Net
|
||||||
|
W: http://patchwork.ozlabs.org/project/netdev/list/
|
||||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6.git
|
T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6.git
|
||||||
S: Maintained
|
S: Maintained
|
||||||
F: net/
|
F: net/
|
||||||
|
@ -4076,6 +4078,13 @@ M: Peter Zijlstra <a.p.zijlstra@chello.nl>
|
||||||
M: Paul Mackerras <paulus@samba.org>
|
M: Paul Mackerras <paulus@samba.org>
|
||||||
M: Ingo Molnar <mingo@elte.hu>
|
M: Ingo Molnar <mingo@elte.hu>
|
||||||
S: Supported
|
S: Supported
|
||||||
|
F: kernel/perf_event.c
|
||||||
|
F: include/linux/perf_event.h
|
||||||
|
F: arch/*/*/kernel/perf_event.c
|
||||||
|
F: arch/*/include/asm/perf_event.h
|
||||||
|
F: arch/*/lib/perf_event.c
|
||||||
|
F: arch/*/kernel/perf_callchain.c
|
||||||
|
F: tools/perf/
|
||||||
|
|
||||||
PERSONALITY HANDLING
|
PERSONALITY HANDLING
|
||||||
M: Christoph Hellwig <hch@infradead.org>
|
M: Christoph Hellwig <hch@infradead.org>
|
||||||
|
@ -5656,6 +5665,13 @@ S: Maintained
|
||||||
F: drivers/vlynq/vlynq.c
|
F: drivers/vlynq/vlynq.c
|
||||||
F: include/linux/vlynq.h
|
F: include/linux/vlynq.h
|
||||||
|
|
||||||
|
VMWARE VMXNET3 ETHERNET DRIVER
|
||||||
|
M: Shreyas Bhatewara <sbhatewara@vmware.com>
|
||||||
|
M: VMware, Inc. <pv-drivers@vmware.com>
|
||||||
|
L: netdev@vger.kernel.org
|
||||||
|
S: Maintained
|
||||||
|
F: drivers/net/vmxnet3/
|
||||||
|
|
||||||
VOLTAGE AND CURRENT REGULATOR FRAMEWORK
|
VOLTAGE AND CURRENT REGULATOR FRAMEWORK
|
||||||
M: Liam Girdwood <lrg@slimlogic.co.uk>
|
M: Liam Girdwood <lrg@slimlogic.co.uk>
|
||||||
M: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
M: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
||||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
||||||
VERSION = 2
|
VERSION = 2
|
||||||
PATCHLEVEL = 6
|
PATCHLEVEL = 6
|
||||||
SUBLEVEL = 32
|
SUBLEVEL = 32
|
||||||
EXTRAVERSION = -rc4
|
EXTRAVERSION = -rc5
|
||||||
NAME = Man-Eating Seals of Antiquity
|
NAME = Man-Eating Seals of Antiquity
|
||||||
|
|
||||||
# *DOCUMENTATION*
|
# *DOCUMENTATION*
|
||||||
|
|
|
@ -969,7 +969,6 @@ CONFIG_USB_ETH_RNDIS=y
|
||||||
#
|
#
|
||||||
CONFIG_USB_OTG_UTILS=y
|
CONFIG_USB_OTG_UTILS=y
|
||||||
# CONFIG_USB_GPIO_VBUS is not set
|
# CONFIG_USB_GPIO_VBUS is not set
|
||||||
# CONFIG_ISP1301_OMAP is not set
|
|
||||||
CONFIG_TWL4030_USB=y
|
CONFIG_TWL4030_USB=y
|
||||||
# CONFIG_NOP_USB_XCEIV is not set
|
# CONFIG_NOP_USB_XCEIV is not set
|
||||||
CONFIG_MMC=y
|
CONFIG_MMC=y
|
||||||
|
|
|
@ -444,7 +444,7 @@ static int __init rx51_i2c_init(void)
|
||||||
rx51_twldata.vaux3 = &rx51_vaux3_cam;
|
rx51_twldata.vaux3 = &rx51_vaux3_cam;
|
||||||
rx51_twldata.vmmc2 = &rx51_vmmc2;
|
rx51_twldata.vmmc2 = &rx51_vmmc2;
|
||||||
}
|
}
|
||||||
omap_register_i2c_bus(1, 2600, rx51_peripherals_i2c_board_info_1,
|
omap_register_i2c_bus(1, 2200, rx51_peripherals_i2c_board_info_1,
|
||||||
ARRAY_SIZE(rx51_peripherals_i2c_board_info_1));
|
ARRAY_SIZE(rx51_peripherals_i2c_board_info_1));
|
||||||
omap_register_i2c_bus(2, 100, NULL, 0);
|
omap_register_i2c_bus(2, 100, NULL, 0);
|
||||||
omap_register_i2c_bus(3, 400, NULL, 0);
|
omap_register_i2c_bus(3, 400, NULL, 0);
|
||||||
|
|
|
@ -25,6 +25,7 @@
|
||||||
#include <mach/keypad.h>
|
#include <mach/keypad.h>
|
||||||
|
|
||||||
#include "mmc-twl4030.h"
|
#include "mmc-twl4030.h"
|
||||||
|
#include "sdram-micron-mt46h32m32lf-6.h"
|
||||||
|
|
||||||
/* Zoom2 has Qwerty keyboard*/
|
/* Zoom2 has Qwerty keyboard*/
|
||||||
static int board_keymap[] = {
|
static int board_keymap[] = {
|
||||||
|
@ -213,7 +214,8 @@ static void __init omap_zoom2_init_irq(void)
|
||||||
{
|
{
|
||||||
omap_board_config = zoom2_config;
|
omap_board_config = zoom2_config;
|
||||||
omap_board_config_size = ARRAY_SIZE(zoom2_config);
|
omap_board_config_size = ARRAY_SIZE(zoom2_config);
|
||||||
omap2_init_common_hw(NULL, NULL);
|
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
|
||||||
|
mt46h32m32lf6_sdrc_params);
|
||||||
omap_init_irq();
|
omap_init_irq();
|
||||||
omap_gpio_init();
|
omap_gpio_init();
|
||||||
}
|
}
|
||||||
|
|
|
@ -769,6 +769,7 @@ int __init omap2_clk_init(void)
|
||||||
if (c->cpu & cpu_mask) {
|
if (c->cpu & cpu_mask) {
|
||||||
clkdev_add(&c->lk);
|
clkdev_add(&c->lk);
|
||||||
clk_register(c->lk.clk);
|
clk_register(c->lk.clk);
|
||||||
|
omap2_init_clk_clkdm(c->lk.clk);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Check the MPU rate set by bootloader */
|
/* Check the MPU rate set by bootloader */
|
||||||
|
|
|
@ -137,6 +137,36 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* _omap2_clkdm_set_hwsup - set the hwsup idle transition bit
|
||||||
|
* @clkdm: struct clockdomain *
|
||||||
|
* @enable: int 0 to disable, 1 to enable
|
||||||
|
*
|
||||||
|
* Internal helper for actually switching the bit that controls hwsup
|
||||||
|
* idle transitions for clkdm.
|
||||||
|
*/
|
||||||
|
static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable)
|
||||||
|
{
|
||||||
|
u32 v;
|
||||||
|
|
||||||
|
if (cpu_is_omap24xx()) {
|
||||||
|
if (enable)
|
||||||
|
v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
|
||||||
|
else
|
||||||
|
v = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
|
||||||
|
} else if (cpu_is_omap34xx()) {
|
||||||
|
if (enable)
|
||||||
|
v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
|
||||||
|
else
|
||||||
|
v = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
|
||||||
|
} else {
|
||||||
|
BUG();
|
||||||
|
}
|
||||||
|
|
||||||
|
cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
|
||||||
|
v << __ffs(clkdm->clktrctrl_mask),
|
||||||
|
clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
|
||||||
|
}
|
||||||
|
|
||||||
static struct clockdomain *_clkdm_lookup(const char *name)
|
static struct clockdomain *_clkdm_lookup(const char *name)
|
||||||
{
|
{
|
||||||
|
@ -456,8 +486,6 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
|
||||||
*/
|
*/
|
||||||
void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
|
void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
|
||||||
{
|
{
|
||||||
u32 v;
|
|
||||||
|
|
||||||
if (!clkdm)
|
if (!clkdm)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
|
@ -473,18 +501,7 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
|
||||||
if (atomic_read(&clkdm->usecount) > 0)
|
if (atomic_read(&clkdm->usecount) > 0)
|
||||||
_clkdm_add_autodeps(clkdm);
|
_clkdm_add_autodeps(clkdm);
|
||||||
|
|
||||||
if (cpu_is_omap24xx())
|
_omap2_clkdm_set_hwsup(clkdm, 1);
|
||||||
v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
|
|
||||||
else if (cpu_is_omap34xx())
|
|
||||||
v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
|
|
||||||
else
|
|
||||||
BUG();
|
|
||||||
|
|
||||||
|
|
||||||
cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
|
|
||||||
v << __ffs(clkdm->clktrctrl_mask),
|
|
||||||
clkdm->pwrdm.ptr->prcm_offs,
|
|
||||||
CM_CLKSTCTRL);
|
|
||||||
|
|
||||||
pwrdm_clkdm_state_switch(clkdm);
|
pwrdm_clkdm_state_switch(clkdm);
|
||||||
}
|
}
|
||||||
|
@ -500,8 +517,6 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
|
||||||
*/
|
*/
|
||||||
void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
|
void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
|
||||||
{
|
{
|
||||||
u32 v;
|
|
||||||
|
|
||||||
if (!clkdm)
|
if (!clkdm)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
|
@ -514,16 +529,7 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
|
||||||
pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
|
pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
|
||||||
clkdm->name);
|
clkdm->name);
|
||||||
|
|
||||||
if (cpu_is_omap24xx())
|
_omap2_clkdm_set_hwsup(clkdm, 0);
|
||||||
v = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
|
|
||||||
else if (cpu_is_omap34xx())
|
|
||||||
v = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
|
|
||||||
else
|
|
||||||
BUG();
|
|
||||||
|
|
||||||
cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
|
|
||||||
v << __ffs(clkdm->clktrctrl_mask),
|
|
||||||
clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
|
|
||||||
|
|
||||||
if (atomic_read(&clkdm->usecount) > 0)
|
if (atomic_read(&clkdm->usecount) > 0)
|
||||||
_clkdm_del_autodeps(clkdm);
|
_clkdm_del_autodeps(clkdm);
|
||||||
|
@ -569,10 +575,14 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
|
||||||
v = omap2_clkdm_clktrctrl_read(clkdm);
|
v = omap2_clkdm_clktrctrl_read(clkdm);
|
||||||
|
|
||||||
if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
|
if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
|
||||||
(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO))
|
(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) {
|
||||||
|
/* Disable HW transitions when we are changing deps */
|
||||||
|
_omap2_clkdm_set_hwsup(clkdm, 0);
|
||||||
_clkdm_add_autodeps(clkdm);
|
_clkdm_add_autodeps(clkdm);
|
||||||
else
|
_omap2_clkdm_set_hwsup(clkdm, 1);
|
||||||
|
} else {
|
||||||
omap2_clkdm_wakeup(clkdm);
|
omap2_clkdm_wakeup(clkdm);
|
||||||
|
}
|
||||||
|
|
||||||
pwrdm_wait_transition(clkdm->pwrdm.ptr);
|
pwrdm_wait_transition(clkdm->pwrdm.ptr);
|
||||||
pwrdm_clkdm_state_switch(clkdm);
|
pwrdm_clkdm_state_switch(clkdm);
|
||||||
|
@ -623,10 +633,14 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
|
||||||
v = omap2_clkdm_clktrctrl_read(clkdm);
|
v = omap2_clkdm_clktrctrl_read(clkdm);
|
||||||
|
|
||||||
if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
|
if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
|
||||||
(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO))
|
(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) {
|
||||||
|
/* Disable HW transitions when we are changing deps */
|
||||||
|
_omap2_clkdm_set_hwsup(clkdm, 0);
|
||||||
_clkdm_del_autodeps(clkdm);
|
_clkdm_del_autodeps(clkdm);
|
||||||
else
|
_omap2_clkdm_set_hwsup(clkdm, 1);
|
||||||
|
} else {
|
||||||
omap2_clkdm_sleep(clkdm);
|
omap2_clkdm_sleep(clkdm);
|
||||||
|
}
|
||||||
|
|
||||||
pwrdm_clkdm_state_switch(clkdm);
|
pwrdm_clkdm_state_switch(clkdm);
|
||||||
|
|
||||||
|
|
|
@ -43,10 +43,10 @@
|
||||||
|
|
||||||
#define CM_X300_ETH_PHYS 0x08000010
|
#define CM_X300_ETH_PHYS 0x08000010
|
||||||
|
|
||||||
#define GPIO82_MMC2_IRQ (82)
|
#define GPIO82_MMC_IRQ (82)
|
||||||
#define GPIO85_MMC2_WP (85)
|
#define GPIO85_MMC_WP (85)
|
||||||
|
|
||||||
#define CM_X300_MMC2_IRQ IRQ_GPIO(GPIO82_MMC2_IRQ)
|
#define CM_X300_MMC_IRQ IRQ_GPIO(GPIO82_MMC_IRQ)
|
||||||
|
|
||||||
#define GPIO95_RTC_CS (95)
|
#define GPIO95_RTC_CS (95)
|
||||||
#define GPIO96_RTC_WR (96)
|
#define GPIO96_RTC_WR (96)
|
||||||
|
@ -292,34 +292,34 @@ static inline void cm_x300_init_nand(void) {}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE)
|
#if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE)
|
||||||
/* The first MMC slot of CM-X300 is hardwired to Libertas card and has
|
static struct pxamci_platform_data cm_x300_mci_platform_data = {
|
||||||
|
.detect_delay = 20,
|
||||||
|
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
|
||||||
|
.gpio_card_detect = GPIO82_MMC_IRQ,
|
||||||
|
.gpio_card_ro = GPIO85_MMC_WP,
|
||||||
|
.gpio_power = -1,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* The second MMC slot of CM-X300 is hardwired to Libertas card and has
|
||||||
no detection/ro pins */
|
no detection/ro pins */
|
||||||
static int cm_x300_mci_init(struct device *dev,
|
static int cm_x300_mci2_init(struct device *dev,
|
||||||
irq_handler_t cm_x300_detect_int,
|
irq_handler_t cm_x300_detect_int,
|
||||||
void *data)
|
void *data)
|
||||||
{
|
{
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void cm_x300_mci_exit(struct device *dev, void *data)
|
static void cm_x300_mci2_exit(struct device *dev, void *data)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct pxamci_platform_data cm_x300_mci_platform_data = {
|
|
||||||
.detect_delay = 20,
|
|
||||||
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
|
|
||||||
.init = cm_x300_mci_init,
|
|
||||||
.exit = cm_x300_mci_exit,
|
|
||||||
.gpio_card_detect = -1,
|
|
||||||
.gpio_card_ro = -1,
|
|
||||||
.gpio_power = -1,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct pxamci_platform_data cm_x300_mci2_platform_data = {
|
static struct pxamci_platform_data cm_x300_mci2_platform_data = {
|
||||||
.detect_delay = 20,
|
.detect_delay = 20,
|
||||||
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
|
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
|
||||||
.gpio_card_detect = GPIO82_MMC2_IRQ,
|
.init = cm_x300_mci2_init,
|
||||||
.gpio_card_ro = GPIO85_MMC2_WP,
|
.exit = cm_x300_mci2_exit,
|
||||||
|
.gpio_card_detect = -1,
|
||||||
|
.gpio_card_ro = -1,
|
||||||
.gpio_power = -1,
|
.gpio_power = -1,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -15,6 +15,7 @@
|
||||||
#include <linux/kernel.h>
|
#include <linux/kernel.h>
|
||||||
#include <linux/platform_device.h>
|
#include <linux/platform_device.h>
|
||||||
#include <linux/delay.h>
|
#include <linux/delay.h>
|
||||||
|
#include <linux/gpio_keys.h>
|
||||||
#include <linux/gpio.h>
|
#include <linux/gpio.h>
|
||||||
#include <linux/leds.h>
|
#include <linux/leds.h>
|
||||||
#include <linux/mtd/physmap.h>
|
#include <linux/mtd/physmap.h>
|
||||||
|
@ -375,6 +376,43 @@ static struct platform_device spitzkbd_device = {
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
|
static struct gpio_keys_button spitz_gpio_keys[] = {
|
||||||
|
{
|
||||||
|
.type = EV_PWR,
|
||||||
|
.code = KEY_SUSPEND,
|
||||||
|
.gpio = SPITZ_GPIO_ON_KEY,
|
||||||
|
.desc = "On/Off",
|
||||||
|
.wakeup = 1,
|
||||||
|
},
|
||||||
|
/* Two buttons detecting the lid state */
|
||||||
|
{
|
||||||
|
.type = EV_SW,
|
||||||
|
.code = 0,
|
||||||
|
.gpio = SPITZ_GPIO_SWA,
|
||||||
|
.desc = "Display Down",
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.type = EV_SW,
|
||||||
|
.code = 1,
|
||||||
|
.gpio = SPITZ_GPIO_SWB,
|
||||||
|
.desc = "Lid Closed",
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct gpio_keys_platform_data spitz_gpio_keys_platform_data = {
|
||||||
|
.buttons = spitz_gpio_keys,
|
||||||
|
.nbuttons = ARRAY_SIZE(spitz_gpio_keys),
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_device spitz_gpio_keys_device = {
|
||||||
|
.name = "gpio-keys",
|
||||||
|
.id = -1,
|
||||||
|
.dev = {
|
||||||
|
.platform_data = &spitz_gpio_keys_platform_data,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Spitz LEDs
|
* Spitz LEDs
|
||||||
*/
|
*/
|
||||||
|
@ -689,6 +727,7 @@ static struct platform_device sharpsl_rom_device = {
|
||||||
static struct platform_device *devices[] __initdata = {
|
static struct platform_device *devices[] __initdata = {
|
||||||
&spitzscoop_device,
|
&spitzscoop_device,
|
||||||
&spitzkbd_device,
|
&spitzkbd_device,
|
||||||
|
&spitz_gpio_keys_device,
|
||||||
&spitzled_device,
|
&spitzled_device,
|
||||||
&sharpsl_nand_device,
|
&sharpsl_nand_device,
|
||||||
&sharpsl_rom_device,
|
&sharpsl_rom_device,
|
||||||
|
|
|
@ -829,10 +829,10 @@ EXPORT_SYMBOL(omap_free_dma);
|
||||||
*
|
*
|
||||||
* @param arb_rate
|
* @param arb_rate
|
||||||
* @param max_fifo_depth
|
* @param max_fifo_depth
|
||||||
* @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
|
* @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
|
||||||
* DMA_THREAD_RESERVE_ONET
|
* DMA_THREAD_RESERVE_ONET
|
||||||
* DMA_THREAD_RESERVE_TWOT
|
* DMA_THREAD_RESERVE_TWOT
|
||||||
* DMA_THREAD_RESERVE_THREET
|
* DMA_THREAD_RESERVE_THREET
|
||||||
*/
|
*/
|
||||||
void
|
void
|
||||||
omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
|
omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
|
||||||
|
@ -844,11 +844,14 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (max_fifo_depth == 0)
|
||||||
|
max_fifo_depth = 1;
|
||||||
if (arb_rate == 0)
|
if (arb_rate == 0)
|
||||||
arb_rate = 1;
|
arb_rate = 1;
|
||||||
|
|
||||||
reg = (arb_rate & 0xff) << 16;
|
reg = 0xff & max_fifo_depth;
|
||||||
reg |= (0xff & max_fifo_depth);
|
reg |= (0x3 & tparams) << 12;
|
||||||
|
reg |= (arb_rate & 0xff) << 16;
|
||||||
|
|
||||||
dma_write(reg, GCR);
|
dma_write(reg, GCR);
|
||||||
}
|
}
|
||||||
|
|
|
@ -595,7 +595,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
|
||||||
rx &= 1;
|
rx &= 1;
|
||||||
if (cpu_is_omap2430() || cpu_is_omap34xx()) {
|
if (cpu_is_omap2430() || cpu_is_omap34xx()) {
|
||||||
w = OMAP_MCBSP_READ(io_base, RCCR);
|
w = OMAP_MCBSP_READ(io_base, RCCR);
|
||||||
w |= (tx ? RDISABLE : 0);
|
w |= (rx ? RDISABLE : 0);
|
||||||
OMAP_MCBSP_WRITE(io_base, RCCR, w);
|
OMAP_MCBSP_WRITE(io_base, RCCR, w);
|
||||||
}
|
}
|
||||||
w = OMAP_MCBSP_READ(io_base, SPCR1);
|
w = OMAP_MCBSP_READ(io_base, SPCR1);
|
||||||
|
|
|
@ -37,7 +37,7 @@
|
||||||
#define FW_FEATURE_VIO ASM_CONST(0x0000000000004000)
|
#define FW_FEATURE_VIO ASM_CONST(0x0000000000004000)
|
||||||
#define FW_FEATURE_RDMA ASM_CONST(0x0000000000008000)
|
#define FW_FEATURE_RDMA ASM_CONST(0x0000000000008000)
|
||||||
#define FW_FEATURE_LLAN ASM_CONST(0x0000000000010000)
|
#define FW_FEATURE_LLAN ASM_CONST(0x0000000000010000)
|
||||||
#define FW_FEATURE_BULK ASM_CONST(0x0000000000020000)
|
#define FW_FEATURE_BULK_REMOVE ASM_CONST(0x0000000000020000)
|
||||||
#define FW_FEATURE_XDABR ASM_CONST(0x0000000000040000)
|
#define FW_FEATURE_XDABR ASM_CONST(0x0000000000040000)
|
||||||
#define FW_FEATURE_MULTITCE ASM_CONST(0x0000000000080000)
|
#define FW_FEATURE_MULTITCE ASM_CONST(0x0000000000080000)
|
||||||
#define FW_FEATURE_SPLPAR ASM_CONST(0x0000000000100000)
|
#define FW_FEATURE_SPLPAR ASM_CONST(0x0000000000100000)
|
||||||
|
@ -45,8 +45,7 @@
|
||||||
#define FW_FEATURE_LPAR ASM_CONST(0x0000000000400000)
|
#define FW_FEATURE_LPAR ASM_CONST(0x0000000000400000)
|
||||||
#define FW_FEATURE_PS3_LV1 ASM_CONST(0x0000000000800000)
|
#define FW_FEATURE_PS3_LV1 ASM_CONST(0x0000000000800000)
|
||||||
#define FW_FEATURE_BEAT ASM_CONST(0x0000000001000000)
|
#define FW_FEATURE_BEAT ASM_CONST(0x0000000001000000)
|
||||||
#define FW_FEATURE_BULK_REMOVE ASM_CONST(0x0000000002000000)
|
#define FW_FEATURE_CMO ASM_CONST(0x0000000002000000)
|
||||||
#define FW_FEATURE_CMO ASM_CONST(0x0000000004000000)
|
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
#ifndef __ASSEMBLY__
|
||||||
|
|
||||||
|
@ -58,8 +57,9 @@ enum {
|
||||||
FW_FEATURE_PERF | FW_FEATURE_DUMP | FW_FEATURE_INTERRUPT |
|
FW_FEATURE_PERF | FW_FEATURE_DUMP | FW_FEATURE_INTERRUPT |
|
||||||
FW_FEATURE_MIGRATE | FW_FEATURE_PERFMON | FW_FEATURE_CRQ |
|
FW_FEATURE_MIGRATE | FW_FEATURE_PERFMON | FW_FEATURE_CRQ |
|
||||||
FW_FEATURE_VIO | FW_FEATURE_RDMA | FW_FEATURE_LLAN |
|
FW_FEATURE_VIO | FW_FEATURE_RDMA | FW_FEATURE_LLAN |
|
||||||
FW_FEATURE_BULK | FW_FEATURE_XDABR | FW_FEATURE_MULTITCE |
|
FW_FEATURE_BULK_REMOVE | FW_FEATURE_XDABR |
|
||||||
FW_FEATURE_SPLPAR | FW_FEATURE_LPAR | FW_FEATURE_CMO,
|
FW_FEATURE_MULTITCE | FW_FEATURE_SPLPAR | FW_FEATURE_LPAR |
|
||||||
|
FW_FEATURE_CMO,
|
||||||
FW_FEATURE_PSERIES_ALWAYS = 0,
|
FW_FEATURE_PSERIES_ALWAYS = 0,
|
||||||
FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
|
FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
|
||||||
FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
|
FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
|
||||||
|
|
|
@ -711,6 +711,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||||
.cpu_setup = __setup_cpu_750,
|
.cpu_setup = __setup_cpu_750,
|
||||||
.machine_check = machine_check_generic,
|
.machine_check = machine_check_generic,
|
||||||
.platform = "ppc750",
|
.platform = "ppc750",
|
||||||
|
.oprofile_cpu_type = "ppc/750",
|
||||||
|
.oprofile_type = PPC_OPROFILE_G4,
|
||||||
},
|
},
|
||||||
{ /* 745/755 */
|
{ /* 745/755 */
|
||||||
.pvr_mask = 0xfffff000,
|
.pvr_mask = 0xfffff000,
|
||||||
|
|
|
@ -1038,8 +1038,7 @@ _GLOBAL(mod_return_to_handler)
|
||||||
* We are in a module using the module's TOC.
|
* We are in a module using the module's TOC.
|
||||||
* Switch to our TOC to run inside the core kernel.
|
* Switch to our TOC to run inside the core kernel.
|
||||||
*/
|
*/
|
||||||
LOAD_REG_IMMEDIATE(r4,ftrace_return_to_handler)
|
ld r2, PACATOC(r13)
|
||||||
ld r2, 8(r4)
|
|
||||||
|
|
||||||
bl .ftrace_return_to_handler
|
bl .ftrace_return_to_handler
|
||||||
nop
|
nop
|
||||||
|
|
|
@ -282,12 +282,6 @@ void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
|
||||||
{
|
{
|
||||||
unsigned long *ptr = gdb_regs;
|
unsigned long *ptr = gdb_regs;
|
||||||
int reg;
|
int reg;
|
||||||
#ifdef CONFIG_SPE
|
|
||||||
union {
|
|
||||||
u32 v32[2];
|
|
||||||
u64 v64;
|
|
||||||
} acc;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
for (reg = 0; reg < 32; reg++)
|
for (reg = 0; reg < 32; reg++)
|
||||||
UNPACK64(regs->gpr[reg], ptr);
|
UNPACK64(regs->gpr[reg], ptr);
|
||||||
|
|
|
@ -1190,7 +1190,7 @@ EXPORT_SYMBOL(pcibios_align_resource);
|
||||||
* Reparent resource children of pr that conflict with res
|
* Reparent resource children of pr that conflict with res
|
||||||
* under res, and make res replace those children.
|
* under res, and make res replace those children.
|
||||||
*/
|
*/
|
||||||
static int __init reparent_resources(struct resource *parent,
|
static int reparent_resources(struct resource *parent,
|
||||||
struct resource *res)
|
struct resource *res)
|
||||||
{
|
{
|
||||||
struct resource *p, **pp;
|
struct resource *p, **pp;
|
||||||
|
|
|
@ -1016,9 +1016,13 @@ void show_stack(struct task_struct *tsk, unsigned long *stack)
|
||||||
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
|
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
|
||||||
int curr_frame = current->curr_ret_stack;
|
int curr_frame = current->curr_ret_stack;
|
||||||
extern void return_to_handler(void);
|
extern void return_to_handler(void);
|
||||||
unsigned long addr = (unsigned long)return_to_handler;
|
unsigned long rth = (unsigned long)return_to_handler;
|
||||||
|
unsigned long mrth = -1;
|
||||||
#ifdef CONFIG_PPC64
|
#ifdef CONFIG_PPC64
|
||||||
addr = *(unsigned long*)addr;
|
extern void mod_return_to_handler(void);
|
||||||
|
rth = *(unsigned long *)rth;
|
||||||
|
mrth = (unsigned long)mod_return_to_handler;
|
||||||
|
mrth = *(unsigned long *)mrth;
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -1044,7 +1048,7 @@ void show_stack(struct task_struct *tsk, unsigned long *stack)
|
||||||
if (!firstframe || ip != lr) {
|
if (!firstframe || ip != lr) {
|
||||||
printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
|
printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
|
||||||
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
|
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
|
||||||
if (ip == addr && curr_frame >= 0) {
|
if ((ip == rth || ip == mrth) && curr_frame >= 0) {
|
||||||
printk(" (%pS)",
|
printk(" (%pS)",
|
||||||
(void *)current->ret_stack[curr_frame].ret);
|
(void *)current->ret_stack[curr_frame].ret);
|
||||||
curr_frame--;
|
curr_frame--;
|
||||||
|
|
|
@ -236,6 +236,7 @@ SECTIONS
|
||||||
READ_MOSTLY_DATA(L1_CACHE_BYTES)
|
READ_MOSTLY_DATA(L1_CACHE_BYTES)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
. = ALIGN(PAGE_SIZE);
|
||||||
.data_nosave : AT(ADDR(.data_nosave) - LOAD_OFFSET) {
|
.data_nosave : AT(ADDR(.data_nosave) - LOAD_OFFSET) {
|
||||||
NOSAVE_DATA
|
NOSAVE_DATA
|
||||||
}
|
}
|
||||||
|
|
|
@ -72,19 +72,17 @@ _GLOBAL(slb_miss_kernel_load_vmemmap)
|
||||||
1:
|
1:
|
||||||
#endif /* CONFIG_SPARSEMEM_VMEMMAP */
|
#endif /* CONFIG_SPARSEMEM_VMEMMAP */
|
||||||
|
|
||||||
/* vmalloc/ioremap mapping encoding bits, the "li" instructions below
|
/* vmalloc mapping gets the encoding from the PACA as the mapping
|
||||||
* will be patched by the kernel at boot
|
* can be demoted from 64K -> 4K dynamically on some machines
|
||||||
*/
|
*/
|
||||||
BEGIN_FTR_SECTION
|
|
||||||
/* check whether this is in vmalloc or ioremap space */
|
|
||||||
clrldi r11,r10,48
|
clrldi r11,r10,48
|
||||||
cmpldi r11,(VMALLOC_SIZE >> 28) - 1
|
cmpldi r11,(VMALLOC_SIZE >> 28) - 1
|
||||||
bgt 5f
|
bgt 5f
|
||||||
lhz r11,PACAVMALLOCSLLP(r13)
|
lhz r11,PACAVMALLOCSLLP(r13)
|
||||||
b 6f
|
b 6f
|
||||||
5:
|
5:
|
||||||
END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE)
|
/* IO mapping */
|
||||||
_GLOBAL(slb_miss_kernel_load_io)
|
_GLOBAL(slb_miss_kernel_load_io)
|
||||||
li r11,0
|
li r11,0
|
||||||
6:
|
6:
|
||||||
BEGIN_FTR_SECTION
|
BEGIN_FTR_SECTION
|
||||||
|
|
|
@ -365,7 +365,7 @@ static int axon_msi_probe(struct of_device *device,
|
||||||
printk(KERN_ERR
|
printk(KERN_ERR
|
||||||
"axon_msi: couldn't parse dcr properties on %s\n",
|
"axon_msi: couldn't parse dcr properties on %s\n",
|
||||||
dn->full_name);
|
dn->full_name);
|
||||||
goto out;
|
goto out_free_msic;
|
||||||
}
|
}
|
||||||
|
|
||||||
msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
|
msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
|
||||||
|
|
|
@ -540,8 +540,11 @@ static struct pmac_i2c_host_kw *__init kw_i2c_host_init(struct device_node *np)
|
||||||
/* Make sure IRQ is disabled */
|
/* Make sure IRQ is disabled */
|
||||||
kw_write_reg(reg_ier, 0);
|
kw_write_reg(reg_ier, 0);
|
||||||
|
|
||||||
/* Request chip interrupt */
|
/* Request chip interrupt. We set IRQF_TIMER because we don't
|
||||||
if (request_irq(host->irq, kw_i2c_irq, 0, "keywest i2c", host))
|
* want that interrupt disabled between the 2 passes of driver
|
||||||
|
* suspend or we'll have issues running the pfuncs
|
||||||
|
*/
|
||||||
|
if (request_irq(host->irq, kw_i2c_irq, IRQF_TIMER, "keywest i2c", host))
|
||||||
host->irq = NO_IRQ;
|
host->irq = NO_IRQ;
|
||||||
|
|
||||||
printk(KERN_INFO "KeyWest i2c @0x%08x irq %d %s\n",
|
printk(KERN_INFO "KeyWest i2c @0x%08x irq %d %s\n",
|
||||||
|
|
|
@ -51,11 +51,10 @@ firmware_features_table[FIRMWARE_MAX_FEATURES] = {
|
||||||
{FW_FEATURE_VIO, "hcall-vio"},
|
{FW_FEATURE_VIO, "hcall-vio"},
|
||||||
{FW_FEATURE_RDMA, "hcall-rdma"},
|
{FW_FEATURE_RDMA, "hcall-rdma"},
|
||||||
{FW_FEATURE_LLAN, "hcall-lLAN"},
|
{FW_FEATURE_LLAN, "hcall-lLAN"},
|
||||||
{FW_FEATURE_BULK, "hcall-bulk"},
|
{FW_FEATURE_BULK_REMOVE, "hcall-bulk"},
|
||||||
{FW_FEATURE_XDABR, "hcall-xdabr"},
|
{FW_FEATURE_XDABR, "hcall-xdabr"},
|
||||||
{FW_FEATURE_MULTITCE, "hcall-multi-tce"},
|
{FW_FEATURE_MULTITCE, "hcall-multi-tce"},
|
||||||
{FW_FEATURE_SPLPAR, "hcall-splpar"},
|
{FW_FEATURE_SPLPAR, "hcall-splpar"},
|
||||||
{FW_FEATURE_BULK_REMOVE, "hcall-bulk"},
|
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Build up the firmware features bitmask using the contents of
|
/* Build up the firmware features bitmask using the contents of
|
||||||
|
|
|
@ -438,7 +438,7 @@ static int diag204_probe(void)
|
||||||
}
|
}
|
||||||
if (diag204((unsigned long)SUBC_STIB6 |
|
if (diag204((unsigned long)SUBC_STIB6 |
|
||||||
(unsigned long)INFO_EXT, pages, buf) >= 0) {
|
(unsigned long)INFO_EXT, pages, buf) >= 0) {
|
||||||
diag204_store_sc = SUBC_STIB7;
|
diag204_store_sc = SUBC_STIB6;
|
||||||
diag204_info_type = INFO_EXT;
|
diag204_info_type = INFO_EXT;
|
||||||
goto out;
|
goto out;
|
||||||
}
|
}
|
||||||
|
|
|
@ -31,9 +31,9 @@ void __cpuinit print_cpu_info(void)
|
||||||
|
|
||||||
static int show_cpuinfo(struct seq_file *m, void *v)
|
static int show_cpuinfo(struct seq_file *m, void *v)
|
||||||
{
|
{
|
||||||
static const char *hwcap_str[9] = {
|
static const char *hwcap_str[10] = {
|
||||||
"esan3", "zarch", "stfle", "msa", "ldisp", "eimm", "dfp",
|
"esan3", "zarch", "stfle", "msa", "ldisp", "eimm", "dfp",
|
||||||
"edat", "etf3eh"
|
"edat", "etf3eh", "highgprs"
|
||||||
};
|
};
|
||||||
struct _lowcore *lc;
|
struct _lowcore *lc;
|
||||||
unsigned long n = (unsigned long) v - 1;
|
unsigned long n = (unsigned long) v - 1;
|
||||||
|
@ -48,7 +48,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
|
||||||
num_online_cpus(), loops_per_jiffy/(500000/HZ),
|
num_online_cpus(), loops_per_jiffy/(500000/HZ),
|
||||||
(loops_per_jiffy/(5000/HZ))%100);
|
(loops_per_jiffy/(5000/HZ))%100);
|
||||||
seq_puts(m, "features\t: ");
|
seq_puts(m, "features\t: ");
|
||||||
for (i = 0; i < 9; i++)
|
for (i = 0; i < 10; i++)
|
||||||
if (hwcap_str[i] && (elf_hwcap & (1UL << i)))
|
if (hwcap_str[i] && (elf_hwcap & (1UL << i)))
|
||||||
seq_printf(m, "%s ", hwcap_str[i]);
|
seq_printf(m, "%s ", hwcap_str[i]);
|
||||||
seq_puts(m, "\n");
|
seq_puts(m, "\n");
|
||||||
|
|
|
@ -121,7 +121,7 @@ noresched:
|
||||||
ENTRY(resume_userspace)
|
ENTRY(resume_userspace)
|
||||||
! r8: current_thread_info
|
! r8: current_thread_info
|
||||||
cli
|
cli
|
||||||
TRACE_IRQS_OfF
|
TRACE_IRQS_OFF
|
||||||
mov.l @(TI_FLAGS,r8), r0 ! current_thread_info->flags
|
mov.l @(TI_FLAGS,r8), r0 ! current_thread_info->flags
|
||||||
tst #(_TIF_WORK_MASK & 0xff), r0
|
tst #(_TIF_WORK_MASK & 0xff), r0
|
||||||
bt/s __restore_all
|
bt/s __restore_all
|
||||||
|
|
|
@ -291,31 +291,48 @@ struct syscall_metadata *syscall_nr_to_meta(int nr)
|
||||||
return syscalls_metadata[nr];
|
return syscalls_metadata[nr];
|
||||||
}
|
}
|
||||||
|
|
||||||
void arch_init_ftrace_syscalls(void)
|
int syscall_name_to_nr(char *name)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
if (!syscalls_metadata)
|
||||||
|
return -1;
|
||||||
|
for (i = 0; i < NR_syscalls; i++)
|
||||||
|
if (syscalls_metadata[i])
|
||||||
|
if (!strcmp(syscalls_metadata[i]->name, name))
|
||||||
|
return i;
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void set_syscall_enter_id(int num, int id)
|
||||||
|
{
|
||||||
|
syscalls_metadata[num]->enter_id = id;
|
||||||
|
}
|
||||||
|
|
||||||
|
void set_syscall_exit_id(int num, int id)
|
||||||
|
{
|
||||||
|
syscalls_metadata[num]->exit_id = id;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int __init arch_init_ftrace_syscalls(void)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
struct syscall_metadata *meta;
|
struct syscall_metadata *meta;
|
||||||
unsigned long **psys_syscall_table = &sys_call_table;
|
unsigned long **psys_syscall_table = &sys_call_table;
|
||||||
static atomic_t refs;
|
|
||||||
|
|
||||||
if (atomic_inc_return(&refs) != 1)
|
|
||||||
goto end;
|
|
||||||
|
|
||||||
syscalls_metadata = kzalloc(sizeof(*syscalls_metadata) *
|
syscalls_metadata = kzalloc(sizeof(*syscalls_metadata) *
|
||||||
FTRACE_SYSCALL_MAX, GFP_KERNEL);
|
FTRACE_SYSCALL_MAX, GFP_KERNEL);
|
||||||
if (!syscalls_metadata) {
|
if (!syscalls_metadata) {
|
||||||
WARN_ON(1);
|
WARN_ON(1);
|
||||||
return;
|
return -ENOMEM;
|
||||||
}
|
}
|
||||||
|
|
||||||
for (i = 0; i < FTRACE_SYSCALL_MAX; i++) {
|
for (i = 0; i < FTRACE_SYSCALL_MAX; i++) {
|
||||||
meta = find_syscall_meta(psys_syscall_table[i]);
|
meta = find_syscall_meta(psys_syscall_table[i]);
|
||||||
syscalls_metadata[i] = meta;
|
syscalls_metadata[i] = meta;
|
||||||
}
|
}
|
||||||
return;
|
|
||||||
|
|
||||||
/* Paranoid: avoid overflow */
|
return 0;
|
||||||
end:
|
|
||||||
atomic_dec(&refs);
|
|
||||||
}
|
}
|
||||||
|
arch_initcall(arch_init_ftrace_syscalls);
|
||||||
#endif /* CONFIG_FTRACE_SYSCALLS */
|
#endif /* CONFIG_FTRACE_SYSCALLS */
|
||||||
|
|
|
@ -549,6 +549,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
|
||||||
|
|
||||||
if (cpu == 0)
|
if (cpu == 0)
|
||||||
seq_printf(m, "machine\t\t: %s\n", get_system_type());
|
seq_printf(m, "machine\t\t: %s\n", get_system_type());
|
||||||
|
else
|
||||||
|
seq_printf(m, "\n");
|
||||||
|
|
||||||
seq_printf(m, "processor\t: %d\n", cpu);
|
seq_printf(m, "processor\t: %d\n", cpu);
|
||||||
seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
|
seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
|
||||||
|
|
|
@ -145,7 +145,7 @@ static inline int restore_sigcontext_fpu(struct sigcontext __user *sc)
|
||||||
{
|
{
|
||||||
struct task_struct *tsk = current;
|
struct task_struct *tsk = current;
|
||||||
|
|
||||||
if (!(current_cpu_data.flags & CPU_HAS_FPU))
|
if (!(boot_cpu_data.flags & CPU_HAS_FPU))
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
set_used_math();
|
set_used_math();
|
||||||
|
@ -158,7 +158,7 @@ static inline int save_sigcontext_fpu(struct sigcontext __user *sc,
|
||||||
{
|
{
|
||||||
struct task_struct *tsk = current;
|
struct task_struct *tsk = current;
|
||||||
|
|
||||||
if (!(current_cpu_data.flags & CPU_HAS_FPU))
|
if (!(boot_cpu_data.flags & CPU_HAS_FPU))
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
if (!used_math()) {
|
if (!used_math()) {
|
||||||
|
@ -199,7 +199,7 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc, int *r0_p
|
||||||
#undef COPY
|
#undef COPY
|
||||||
|
|
||||||
#ifdef CONFIG_SH_FPU
|
#ifdef CONFIG_SH_FPU
|
||||||
if (current_cpu_data.flags & CPU_HAS_FPU) {
|
if (boot_cpu_data.flags & CPU_HAS_FPU) {
|
||||||
int owned_fp;
|
int owned_fp;
|
||||||
struct task_struct *tsk = current;
|
struct task_struct *tsk = current;
|
||||||
|
|
||||||
|
@ -472,6 +472,7 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
|
||||||
err |= __put_user(OR_R0_R0, &frame->retcode[6]);
|
err |= __put_user(OR_R0_R0, &frame->retcode[6]);
|
||||||
err |= __put_user((__NR_rt_sigreturn), &frame->retcode[7]);
|
err |= __put_user((__NR_rt_sigreturn), &frame->retcode[7]);
|
||||||
regs->pr = (unsigned long) frame->retcode;
|
regs->pr = (unsigned long) frame->retcode;
|
||||||
|
flush_icache_range(regs->pr, regs->pr + sizeof(frame->retcode));
|
||||||
}
|
}
|
||||||
|
|
||||||
if (err)
|
if (err)
|
||||||
|
@ -497,8 +498,6 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
|
||||||
pr_debug("SIG deliver (%s:%d): sp=%p pc=%08lx pr=%08lx\n",
|
pr_debug("SIG deliver (%s:%d): sp=%p pc=%08lx pr=%08lx\n",
|
||||||
current->comm, task_pid_nr(current), frame, regs->pc, regs->pr);
|
current->comm, task_pid_nr(current), frame, regs->pc, regs->pr);
|
||||||
|
|
||||||
flush_icache_range(regs->pr, regs->pr + sizeof(frame->retcode));
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
give_sigsegv:
|
give_sigsegv:
|
||||||
|
|
|
@ -35,6 +35,8 @@ static inline void __init smp_store_cpu_info(unsigned int cpu)
|
||||||
{
|
{
|
||||||
struct sh_cpuinfo *c = cpu_data + cpu;
|
struct sh_cpuinfo *c = cpu_data + cpu;
|
||||||
|
|
||||||
|
memcpy(c, &boot_cpu_data, sizeof(struct sh_cpuinfo));
|
||||||
|
|
||||||
c->loops_per_jiffy = loops_per_jiffy;
|
c->loops_per_jiffy = loops_per_jiffy;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -25,6 +25,7 @@
|
||||||
#include <linux/kexec.h>
|
#include <linux/kexec.h>
|
||||||
#include <linux/limits.h>
|
#include <linux/limits.h>
|
||||||
#include <linux/proc_fs.h>
|
#include <linux/proc_fs.h>
|
||||||
|
#include <linux/sysfs.h>
|
||||||
#include <asm/system.h>
|
#include <asm/system.h>
|
||||||
#include <asm/uaccess.h>
|
#include <asm/uaccess.h>
|
||||||
#include <asm/fpu.h>
|
#include <asm/fpu.h>
|
||||||
|
@ -159,12 +160,12 @@ void die(const char * str, struct pt_regs * regs, long err)
|
||||||
|
|
||||||
oops_enter();
|
oops_enter();
|
||||||
|
|
||||||
console_verbose();
|
|
||||||
spin_lock_irq(&die_lock);
|
spin_lock_irq(&die_lock);
|
||||||
|
console_verbose();
|
||||||
bust_spinlocks(1);
|
bust_spinlocks(1);
|
||||||
|
|
||||||
printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
|
printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
|
||||||
|
sysfs_printk_last_file();
|
||||||
print_modules();
|
print_modules();
|
||||||
show_regs(regs);
|
show_regs(regs);
|
||||||
|
|
||||||
|
@ -180,6 +181,7 @@ void die(const char * str, struct pt_regs * regs, long err)
|
||||||
bust_spinlocks(0);
|
bust_spinlocks(0);
|
||||||
add_taint(TAINT_DIE);
|
add_taint(TAINT_DIE);
|
||||||
spin_unlock_irq(&die_lock);
|
spin_unlock_irq(&die_lock);
|
||||||
|
oops_exit();
|
||||||
|
|
||||||
if (kexec_should_crash(current))
|
if (kexec_should_crash(current))
|
||||||
crash_kexec(regs);
|
crash_kexec(regs);
|
||||||
|
@ -190,7 +192,6 @@ void die(const char * str, struct pt_regs * regs, long err)
|
||||||
if (panic_on_oops)
|
if (panic_on_oops)
|
||||||
panic("Fatal exception");
|
panic("Fatal exception");
|
||||||
|
|
||||||
oops_exit();
|
|
||||||
do_exit(SIGSEGV);
|
do_exit(SIGSEGV);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -128,7 +128,7 @@ void __update_cache(struct vm_area_struct *vma,
|
||||||
return;
|
return;
|
||||||
|
|
||||||
page = pfn_to_page(pfn);
|
page = pfn_to_page(pfn);
|
||||||
if (pfn_valid(pfn) && page_mapping(page)) {
|
if (pfn_valid(pfn)) {
|
||||||
int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
|
int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
|
||||||
if (dirty) {
|
if (dirty) {
|
||||||
unsigned long addr = (unsigned long)page_address(page);
|
unsigned long addr = (unsigned long)page_address(page);
|
||||||
|
|
|
@ -1242,13 +1242,13 @@ int ldc_bind(struct ldc_channel *lp, const char *name)
|
||||||
snprintf(lp->tx_irq_name, LDC_IRQ_NAME_MAX, "%s TX", name);
|
snprintf(lp->tx_irq_name, LDC_IRQ_NAME_MAX, "%s TX", name);
|
||||||
|
|
||||||
err = request_irq(lp->cfg.rx_irq, ldc_rx,
|
err = request_irq(lp->cfg.rx_irq, ldc_rx,
|
||||||
IRQF_SAMPLE_RANDOM | IRQF_SHARED,
|
IRQF_SAMPLE_RANDOM | IRQF_DISABLED | IRQF_SHARED,
|
||||||
lp->rx_irq_name, lp);
|
lp->rx_irq_name, lp);
|
||||||
if (err)
|
if (err)
|
||||||
return err;
|
return err;
|
||||||
|
|
||||||
err = request_irq(lp->cfg.tx_irq, ldc_tx,
|
err = request_irq(lp->cfg.tx_irq, ldc_tx,
|
||||||
IRQF_SAMPLE_RANDOM | IRQF_SHARED,
|
IRQF_SAMPLE_RANDOM | IRQF_DISABLED | IRQF_SHARED,
|
||||||
lp->tx_irq_name, lp);
|
lp->tx_irq_name, lp);
|
||||||
if (err) {
|
if (err) {
|
||||||
free_irq(lp->cfg.rx_irq, lp);
|
free_irq(lp->cfg.rx_irq, lp);
|
||||||
|
|
|
@ -437,7 +437,7 @@ static const struct sparc_pmu niagara2_pmu = {
|
||||||
.lower_shift = 6,
|
.lower_shift = 6,
|
||||||
.event_mask = 0xfff,
|
.event_mask = 0xfff,
|
||||||
.hv_bit = 0x8,
|
.hv_bit = 0x8,
|
||||||
.irq_bit = 0x03,
|
.irq_bit = 0x30,
|
||||||
.upper_nop = 0x220,
|
.upper_nop = 0x220,
|
||||||
.lower_nop = 0x220,
|
.lower_nop = 0x220,
|
||||||
};
|
};
|
||||||
|
|
|
@ -265,7 +265,7 @@ static void flush_dcache(unsigned long pfn)
|
||||||
struct page *page;
|
struct page *page;
|
||||||
|
|
||||||
page = pfn_to_page(pfn);
|
page = pfn_to_page(pfn);
|
||||||
if (page && page_mapping(page)) {
|
if (page) {
|
||||||
unsigned long pg_flags;
|
unsigned long pg_flags;
|
||||||
|
|
||||||
pg_flags = page->flags;
|
pg_flags = page->flags;
|
||||||
|
|
|
@ -491,7 +491,7 @@ if PARAVIRT_GUEST
|
||||||
source "arch/x86/xen/Kconfig"
|
source "arch/x86/xen/Kconfig"
|
||||||
|
|
||||||
config VMI
|
config VMI
|
||||||
bool "VMI Guest support"
|
bool "VMI Guest support (DEPRECATED)"
|
||||||
select PARAVIRT
|
select PARAVIRT
|
||||||
depends on X86_32
|
depends on X86_32
|
||||||
---help---
|
---help---
|
||||||
|
@ -500,6 +500,15 @@ config VMI
|
||||||
at the moment), by linking the kernel to a GPL-ed ROM module
|
at the moment), by linking the kernel to a GPL-ed ROM module
|
||||||
provided by the hypervisor.
|
provided by the hypervisor.
|
||||||
|
|
||||||
|
As of September 2009, VMware has started a phased retirement
|
||||||
|
of this feature from VMware's products. Please see
|
||||||
|
feature-removal-schedule.txt for details. If you are
|
||||||
|
planning to enable this option, please note that you cannot
|
||||||
|
live migrate a VMI enabled VM to a future VMware product,
|
||||||
|
which doesn't support VMI. So if you expect your kernel to
|
||||||
|
seamlessly migrate to newer VMware products, keep this
|
||||||
|
disabled.
|
||||||
|
|
||||||
config KVM_CLOCK
|
config KVM_CLOCK
|
||||||
bool "KVM paravirtualized clock"
|
bool "KVM paravirtualized clock"
|
||||||
select PARAVIRT
|
select PARAVIRT
|
||||||
|
|
|
@ -840,42 +840,22 @@ static __always_inline void __raw_spin_unlock(struct raw_spinlock *lock)
|
||||||
|
|
||||||
static inline unsigned long __raw_local_save_flags(void)
|
static inline unsigned long __raw_local_save_flags(void)
|
||||||
{
|
{
|
||||||
unsigned long f;
|
return PVOP_CALLEE0(unsigned long, pv_irq_ops.save_fl);
|
||||||
|
|
||||||
asm volatile(paravirt_alt(PARAVIRT_CALL)
|
|
||||||
: "=a"(f)
|
|
||||||
: paravirt_type(pv_irq_ops.save_fl),
|
|
||||||
paravirt_clobber(CLBR_EAX)
|
|
||||||
: "memory", "cc");
|
|
||||||
return f;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void raw_local_irq_restore(unsigned long f)
|
static inline void raw_local_irq_restore(unsigned long f)
|
||||||
{
|
{
|
||||||
asm volatile(paravirt_alt(PARAVIRT_CALL)
|
PVOP_VCALLEE1(pv_irq_ops.restore_fl, f);
|
||||||
: "=a"(f)
|
|
||||||
: PV_FLAGS_ARG(f),
|
|
||||||
paravirt_type(pv_irq_ops.restore_fl),
|
|
||||||
paravirt_clobber(CLBR_EAX)
|
|
||||||
: "memory", "cc");
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void raw_local_irq_disable(void)
|
static inline void raw_local_irq_disable(void)
|
||||||
{
|
{
|
||||||
asm volatile(paravirt_alt(PARAVIRT_CALL)
|
PVOP_VCALLEE0(pv_irq_ops.irq_disable);
|
||||||
:
|
|
||||||
: paravirt_type(pv_irq_ops.irq_disable),
|
|
||||||
paravirt_clobber(CLBR_EAX)
|
|
||||||
: "memory", "eax", "cc");
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void raw_local_irq_enable(void)
|
static inline void raw_local_irq_enable(void)
|
||||||
{
|
{
|
||||||
asm volatile(paravirt_alt(PARAVIRT_CALL)
|
PVOP_VCALLEE0(pv_irq_ops.irq_enable);
|
||||||
:
|
|
||||||
: paravirt_type(pv_irq_ops.irq_enable),
|
|
||||||
paravirt_clobber(CLBR_EAX)
|
|
||||||
: "memory", "eax", "cc");
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline unsigned long __raw_local_irq_save(void)
|
static inline unsigned long __raw_local_irq_save(void)
|
||||||
|
|
|
@ -494,10 +494,11 @@ int paravirt_disable_iospace(void);
|
||||||
#define EXTRA_CLOBBERS
|
#define EXTRA_CLOBBERS
|
||||||
#define VEXTRA_CLOBBERS
|
#define VEXTRA_CLOBBERS
|
||||||
#else /* CONFIG_X86_64 */
|
#else /* CONFIG_X86_64 */
|
||||||
|
/* [re]ax isn't an arg, but the return val */
|
||||||
#define PVOP_VCALL_ARGS \
|
#define PVOP_VCALL_ARGS \
|
||||||
unsigned long __edi = __edi, __esi = __esi, \
|
unsigned long __edi = __edi, __esi = __esi, \
|
||||||
__edx = __edx, __ecx = __ecx
|
__edx = __edx, __ecx = __ecx, __eax = __eax
|
||||||
#define PVOP_CALL_ARGS PVOP_VCALL_ARGS, __eax
|
#define PVOP_CALL_ARGS PVOP_VCALL_ARGS
|
||||||
|
|
||||||
#define PVOP_CALL_ARG1(x) "D" ((unsigned long)(x))
|
#define PVOP_CALL_ARG1(x) "D" ((unsigned long)(x))
|
||||||
#define PVOP_CALL_ARG2(x) "S" ((unsigned long)(x))
|
#define PVOP_CALL_ARG2(x) "S" ((unsigned long)(x))
|
||||||
|
@ -509,6 +510,7 @@ int paravirt_disable_iospace(void);
|
||||||
"=c" (__ecx)
|
"=c" (__ecx)
|
||||||
#define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS, "=a" (__eax)
|
#define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS, "=a" (__eax)
|
||||||
|
|
||||||
|
/* void functions are still allowed [re]ax for scratch */
|
||||||
#define PVOP_VCALLEE_CLOBBERS "=a" (__eax)
|
#define PVOP_VCALLEE_CLOBBERS "=a" (__eax)
|
||||||
#define PVOP_CALLEE_CLOBBERS PVOP_VCALLEE_CLOBBERS
|
#define PVOP_CALLEE_CLOBBERS PVOP_VCALLEE_CLOBBERS
|
||||||
|
|
||||||
|
@ -583,8 +585,8 @@ int paravirt_disable_iospace(void);
|
||||||
VEXTRA_CLOBBERS, \
|
VEXTRA_CLOBBERS, \
|
||||||
pre, post, ##__VA_ARGS__)
|
pre, post, ##__VA_ARGS__)
|
||||||
|
|
||||||
#define __PVOP_VCALLEESAVE(rettype, op, pre, post, ...) \
|
#define __PVOP_VCALLEESAVE(op, pre, post, ...) \
|
||||||
____PVOP_CALL(rettype, op.func, CLBR_RET_REG, \
|
____PVOP_VCALL(op.func, CLBR_RET_REG, \
|
||||||
PVOP_VCALLEE_CLOBBERS, , \
|
PVOP_VCALLEE_CLOBBERS, , \
|
||||||
pre, post, ##__VA_ARGS__)
|
pre, post, ##__VA_ARGS__)
|
||||||
|
|
||||||
|
|
|
@ -63,10 +63,10 @@ static int show_other_interrupts(struct seq_file *p, int prec)
|
||||||
for_each_online_cpu(j)
|
for_each_online_cpu(j)
|
||||||
seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
|
seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
|
||||||
seq_printf(p, " Spurious interrupts\n");
|
seq_printf(p, " Spurious interrupts\n");
|
||||||
seq_printf(p, "%*s: ", prec, "CNT");
|
seq_printf(p, "%*s: ", prec, "PMI");
|
||||||
for_each_online_cpu(j)
|
for_each_online_cpu(j)
|
||||||
seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
|
seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
|
||||||
seq_printf(p, " Performance counter interrupts\n");
|
seq_printf(p, " Performance monitoring interrupts\n");
|
||||||
seq_printf(p, "%*s: ", prec, "PND");
|
seq_printf(p, "%*s: ", prec, "PND");
|
||||||
for_each_online_cpu(j)
|
for_each_online_cpu(j)
|
||||||
seq_printf(p, "%10u ", irq_stats(j)->apic_pending_irqs);
|
seq_printf(p, "%10u ", irq_stats(j)->apic_pending_irqs);
|
||||||
|
@ -244,7 +244,6 @@ unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
|
||||||
__func__, smp_processor_id(), vector, irq);
|
__func__, smp_processor_id(), vector, irq);
|
||||||
}
|
}
|
||||||
|
|
||||||
run_local_timers();
|
|
||||||
irq_exit();
|
irq_exit();
|
||||||
|
|
||||||
set_irq_regs(old_regs);
|
set_irq_regs(old_regs);
|
||||||
|
@ -269,7 +268,6 @@ void smp_generic_interrupt(struct pt_regs *regs)
|
||||||
if (generic_interrupt_extension)
|
if (generic_interrupt_extension)
|
||||||
generic_interrupt_extension();
|
generic_interrupt_extension();
|
||||||
|
|
||||||
run_local_timers();
|
|
||||||
irq_exit();
|
irq_exit();
|
||||||
|
|
||||||
set_irq_regs(old_regs);
|
set_irq_regs(old_regs);
|
||||||
|
|
|
@ -198,7 +198,6 @@ void smp_reschedule_interrupt(struct pt_regs *regs)
|
||||||
{
|
{
|
||||||
ack_APIC_irq();
|
ack_APIC_irq();
|
||||||
inc_irq_stat(irq_resched_count);
|
inc_irq_stat(irq_resched_count);
|
||||||
run_local_timers();
|
|
||||||
/*
|
/*
|
||||||
* KVM uses this interrupt to force a cpu out of guest mode
|
* KVM uses this interrupt to force a cpu out of guest mode
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -38,7 +38,8 @@ unsigned long profile_pc(struct pt_regs *regs)
|
||||||
#ifdef CONFIG_FRAME_POINTER
|
#ifdef CONFIG_FRAME_POINTER
|
||||||
return *(unsigned long *)(regs->bp + sizeof(long));
|
return *(unsigned long *)(regs->bp + sizeof(long));
|
||||||
#else
|
#else
|
||||||
unsigned long *sp = (unsigned long *)regs->sp;
|
unsigned long *sp =
|
||||||
|
(unsigned long *)kernel_stack_pointer(regs);
|
||||||
/*
|
/*
|
||||||
* Return address is either directly at stack pointer
|
* Return address is either directly at stack pointer
|
||||||
* or above a saved flags. Eflags has bits 22-31 zero,
|
* or above a saved flags. Eflags has bits 22-31 zero,
|
||||||
|
|
|
@ -3,8 +3,16 @@
|
||||||
#include <asm/trampoline.h>
|
#include <asm/trampoline.h>
|
||||||
#include <asm/e820.h>
|
#include <asm/e820.h>
|
||||||
|
|
||||||
|
#if defined(CONFIG_X86_64) && defined(CONFIG_ACPI_SLEEP)
|
||||||
|
#define __trampinit
|
||||||
|
#define __trampinitdata
|
||||||
|
#else
|
||||||
|
#define __trampinit __cpuinit
|
||||||
|
#define __trampinitdata __cpuinitdata
|
||||||
|
#endif
|
||||||
|
|
||||||
/* ready for x86_64 and x86 */
|
/* ready for x86_64 and x86 */
|
||||||
unsigned char *__cpuinitdata trampoline_base = __va(TRAMPOLINE_BASE);
|
unsigned char *__trampinitdata trampoline_base = __va(TRAMPOLINE_BASE);
|
||||||
|
|
||||||
void __init reserve_trampoline_memory(void)
|
void __init reserve_trampoline_memory(void)
|
||||||
{
|
{
|
||||||
|
@ -26,7 +34,7 @@ void __init reserve_trampoline_memory(void)
|
||||||
* bootstrap into the page concerned. The caller
|
* bootstrap into the page concerned. The caller
|
||||||
* has made sure it's suitably aligned.
|
* has made sure it's suitably aligned.
|
||||||
*/
|
*/
|
||||||
unsigned long __cpuinit setup_trampoline(void)
|
unsigned long __trampinit setup_trampoline(void)
|
||||||
{
|
{
|
||||||
memcpy(trampoline_base, trampoline_data, TRAMPOLINE_SIZE);
|
memcpy(trampoline_base, trampoline_data, TRAMPOLINE_SIZE);
|
||||||
return virt_to_phys(trampoline_base);
|
return virt_to_phys(trampoline_base);
|
||||||
|
|
|
@ -32,8 +32,12 @@
|
||||||
#include <asm/segment.h>
|
#include <asm/segment.h>
|
||||||
#include <asm/processor-flags.h>
|
#include <asm/processor-flags.h>
|
||||||
|
|
||||||
|
#ifdef CONFIG_ACPI_SLEEP
|
||||||
|
.section .rodata, "a", @progbits
|
||||||
|
#else
|
||||||
/* We can free up the trampoline after bootup if cpu hotplug is not supported. */
|
/* We can free up the trampoline after bootup if cpu hotplug is not supported. */
|
||||||
__CPUINITRODATA
|
__CPUINITRODATA
|
||||||
|
#endif
|
||||||
.code16
|
.code16
|
||||||
|
|
||||||
ENTRY(trampoline_data)
|
ENTRY(trampoline_data)
|
||||||
|
|
|
@ -648,7 +648,7 @@ static inline int __init activate_vmi(void)
|
||||||
|
|
||||||
pv_info.paravirt_enabled = 1;
|
pv_info.paravirt_enabled = 1;
|
||||||
pv_info.kernel_rpl = kernel_cs & SEGMENT_RPL_MASK;
|
pv_info.kernel_rpl = kernel_cs & SEGMENT_RPL_MASK;
|
||||||
pv_info.name = "vmi";
|
pv_info.name = "vmi [deprecated]";
|
||||||
|
|
||||||
pv_init_ops.patch = vmi_patch;
|
pv_init_ops.patch = vmi_patch;
|
||||||
|
|
||||||
|
|
|
@ -218,10 +218,10 @@ config ACPI_PROCESSOR_AGGREGATOR
|
||||||
depends on X86
|
depends on X86
|
||||||
help
|
help
|
||||||
ACPI 4.0 defines processor Aggregator, which enables OS to perform
|
ACPI 4.0 defines processor Aggregator, which enables OS to perform
|
||||||
specfic processor configuration and control that applies to all
|
specific processor configuration and control that applies to all
|
||||||
processors in the platform. Currently only logical processor idling
|
processors in the platform. Currently only logical processor idling
|
||||||
is defined, which is to reduce power consumption. This driver
|
is defined, which is to reduce power consumption. This driver
|
||||||
support the new device.
|
supports the new device.
|
||||||
|
|
||||||
config ACPI_THERMAL
|
config ACPI_THERMAL
|
||||||
tristate "Thermal Zone"
|
tristate "Thermal Zone"
|
||||||
|
|
|
@ -245,6 +245,7 @@ static void acpi_ac_notify(struct acpi_device *device, u32 event)
|
||||||
acpi_bus_generate_netlink_event(device->pnp.device_class,
|
acpi_bus_generate_netlink_event(device->pnp.device_class,
|
||||||
dev_name(&device->dev), event,
|
dev_name(&device->dev), event,
|
||||||
(u32) ac->state);
|
(u32) ac->state);
|
||||||
|
acpi_notifier_call_chain(device, event, (u32) ac->state);
|
||||||
#ifdef CONFIG_ACPI_SYSFS_POWER
|
#ifdef CONFIG_ACPI_SYSFS_POWER
|
||||||
kobject_uevent(&ac->charger.dev->kobj, KOBJ_CHANGE);
|
kobject_uevent(&ac->charger.dev->kobj, KOBJ_CHANGE);
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -251,6 +251,9 @@ int acpi_lid_open(void)
|
||||||
acpi_status status;
|
acpi_status status;
|
||||||
unsigned long long state;
|
unsigned long long state;
|
||||||
|
|
||||||
|
if (!lid_device)
|
||||||
|
return -ENODEV;
|
||||||
|
|
||||||
status = acpi_evaluate_integer(lid_device->handle, "_LID", NULL,
|
status = acpi_evaluate_integer(lid_device->handle, "_LID", NULL,
|
||||||
&state);
|
&state);
|
||||||
if (ACPI_FAILURE(status))
|
if (ACPI_FAILURE(status))
|
||||||
|
|
|
@ -389,6 +389,17 @@ struct pci_dev *acpi_get_pci_dev(acpi_handle handle)
|
||||||
|
|
||||||
pbus = pdev->subordinate;
|
pbus = pdev->subordinate;
|
||||||
pci_dev_put(pdev);
|
pci_dev_put(pdev);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This function may be called for a non-PCI device that has a
|
||||||
|
* PCI parent (eg. a disk under a PCI SATA controller). In that
|
||||||
|
* case pdev->subordinate will be NULL for the parent.
|
||||||
|
*/
|
||||||
|
if (!pbus) {
|
||||||
|
dev_dbg(&pdev->dev, "Not a PCI-to-PCI bridge\n");
|
||||||
|
pdev = NULL;
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
out:
|
out:
|
||||||
list_for_each_entry_safe(node, tmp, &device_list, node)
|
list_for_each_entry_safe(node, tmp, &device_list, node)
|
||||||
|
|
|
@ -1109,7 +1109,12 @@ static int acpi_video_bus_check(struct acpi_video_bus *video)
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Does this device support video switching? */
|
/* Does this device support video switching? */
|
||||||
if (video->cap._DOS) {
|
if (video->cap._DOS || video->cap._DOD) {
|
||||||
|
if (!video->cap._DOS) {
|
||||||
|
printk(KERN_WARNING FW_BUG
|
||||||
|
"ACPI(%s) defines _DOD but not _DOS\n",
|
||||||
|
acpi_device_bid(video->device));
|
||||||
|
}
|
||||||
video->flags.multihead = 1;
|
video->flags.multihead = 1;
|
||||||
status = 0;
|
status = 0;
|
||||||
}
|
}
|
||||||
|
|
|
@ -84,7 +84,7 @@ long acpi_is_video_device(struct acpi_device *device)
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
/* Does this device able to support video switching ? */
|
/* Does this device able to support video switching ? */
|
||||||
if (ACPI_SUCCESS(acpi_get_handle(device->handle, "_DOD", &h_dummy)) &&
|
if (ACPI_SUCCESS(acpi_get_handle(device->handle, "_DOD", &h_dummy)) ||
|
||||||
ACPI_SUCCESS(acpi_get_handle(device->handle, "_DOS", &h_dummy)))
|
ACPI_SUCCESS(acpi_get_handle(device->handle, "_DOS", &h_dummy)))
|
||||||
video_caps |= ACPI_VIDEO_OUTPUT_SWITCHING;
|
video_caps |= ACPI_VIDEO_OUTPUT_SWITCHING;
|
||||||
|
|
||||||
|
|
|
@ -402,28 +402,26 @@ static void flush_to_ldisc(struct work_struct *work)
|
||||||
container_of(work, struct tty_struct, buf.work.work);
|
container_of(work, struct tty_struct, buf.work.work);
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
struct tty_ldisc *disc;
|
struct tty_ldisc *disc;
|
||||||
struct tty_buffer *tbuf, *head;
|
|
||||||
char *char_buf;
|
|
||||||
unsigned char *flag_buf;
|
|
||||||
|
|
||||||
disc = tty_ldisc_ref(tty);
|
disc = tty_ldisc_ref(tty);
|
||||||
if (disc == NULL) /* !TTY_LDISC */
|
if (disc == NULL) /* !TTY_LDISC */
|
||||||
return;
|
return;
|
||||||
|
|
||||||
spin_lock_irqsave(&tty->buf.lock, flags);
|
spin_lock_irqsave(&tty->buf.lock, flags);
|
||||||
/* So we know a flush is running */
|
|
||||||
set_bit(TTY_FLUSHING, &tty->flags);
|
if (!test_and_set_bit(TTY_FLUSHING, &tty->flags)) {
|
||||||
head = tty->buf.head;
|
struct tty_buffer *head;
|
||||||
if (head != NULL) {
|
while ((head = tty->buf.head) != NULL) {
|
||||||
tty->buf.head = NULL;
|
int count;
|
||||||
for (;;) {
|
char *char_buf;
|
||||||
int count = head->commit - head->read;
|
unsigned char *flag_buf;
|
||||||
|
|
||||||
|
count = head->commit - head->read;
|
||||||
if (!count) {
|
if (!count) {
|
||||||
if (head->next == NULL)
|
if (head->next == NULL)
|
||||||
break;
|
break;
|
||||||
tbuf = head;
|
tty->buf.head = head->next;
|
||||||
head = head->next;
|
tty_buffer_free(tty, head);
|
||||||
tty_buffer_free(tty, tbuf);
|
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
/* Ldisc or user is trying to flush the buffers
|
/* Ldisc or user is trying to flush the buffers
|
||||||
|
@ -445,9 +443,9 @@ static void flush_to_ldisc(struct work_struct *work)
|
||||||
flag_buf, count);
|
flag_buf, count);
|
||||||
spin_lock_irqsave(&tty->buf.lock, flags);
|
spin_lock_irqsave(&tty->buf.lock, flags);
|
||||||
}
|
}
|
||||||
/* Restore the queue head */
|
clear_bit(TTY_FLUSHING, &tty->flags);
|
||||||
tty->buf.head = head;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* We may have a deferred request to flush the input buffer,
|
/* We may have a deferred request to flush the input buffer,
|
||||||
if so pull the chain under the lock and empty the queue */
|
if so pull the chain under the lock and empty the queue */
|
||||||
if (test_bit(TTY_FLUSHPENDING, &tty->flags)) {
|
if (test_bit(TTY_FLUSHPENDING, &tty->flags)) {
|
||||||
|
@ -455,7 +453,6 @@ static void flush_to_ldisc(struct work_struct *work)
|
||||||
clear_bit(TTY_FLUSHPENDING, &tty->flags);
|
clear_bit(TTY_FLUSHPENDING, &tty->flags);
|
||||||
wake_up(&tty->read_wait);
|
wake_up(&tty->read_wait);
|
||||||
}
|
}
|
||||||
clear_bit(TTY_FLUSHING, &tty->flags);
|
|
||||||
spin_unlock_irqrestore(&tty->buf.lock, flags);
|
spin_unlock_irqrestore(&tty->buf.lock, flags);
|
||||||
|
|
||||||
tty_ldisc_deref(disc);
|
tty_ldisc_deref(disc);
|
||||||
|
@ -471,7 +468,7 @@ static void flush_to_ldisc(struct work_struct *work)
|
||||||
*/
|
*/
|
||||||
void tty_flush_to_ldisc(struct tty_struct *tty)
|
void tty_flush_to_ldisc(struct tty_struct *tty)
|
||||||
{
|
{
|
||||||
flush_to_ldisc(&tty->buf.work.work);
|
flush_delayed_work(&tty->buf.work);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
@ -1532,7 +1532,7 @@ long vt_compat_ioctl(struct tty_struct *tty, struct file * file,
|
||||||
|
|
||||||
case PIO_UNIMAP:
|
case PIO_UNIMAP:
|
||||||
case GIO_UNIMAP:
|
case GIO_UNIMAP:
|
||||||
ret = do_unimap_ioctl(cmd, up, perm, vc);
|
ret = compat_unimap_ioctl(cmd, up, perm, vc);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -188,14 +188,7 @@ static struct fw_device *target_device(struct sbp2_target *tgt)
|
||||||
/* Impossible login_id, to detect logout attempt before successful login */
|
/* Impossible login_id, to detect logout attempt before successful login */
|
||||||
#define INVALID_LOGIN_ID 0x10000
|
#define INVALID_LOGIN_ID 0x10000
|
||||||
|
|
||||||
/*
|
#define SBP2_ORB_TIMEOUT 2000U /* Timeout in ms */
|
||||||
* Per section 7.4.8 of the SBP-2 spec, a mgt_ORB_timeout value can be
|
|
||||||
* provided in the config rom. Most devices do provide a value, which
|
|
||||||
* we'll use for login management orbs, but with some sane limits.
|
|
||||||
*/
|
|
||||||
#define SBP2_MIN_LOGIN_ORB_TIMEOUT 5000U /* Timeout in ms */
|
|
||||||
#define SBP2_MAX_LOGIN_ORB_TIMEOUT 40000U /* Timeout in ms */
|
|
||||||
#define SBP2_ORB_TIMEOUT 2000U /* Timeout in ms */
|
|
||||||
#define SBP2_ORB_NULL 0x80000000
|
#define SBP2_ORB_NULL 0x80000000
|
||||||
#define SBP2_RETRY_LIMIT 0xf /* 15 retries */
|
#define SBP2_RETRY_LIMIT 0xf /* 15 retries */
|
||||||
#define SBP2_CYCLE_LIMIT (0xc8 << 12) /* 200 125us cycles */
|
#define SBP2_CYCLE_LIMIT (0xc8 << 12) /* 200 125us cycles */
|
||||||
|
@ -1034,7 +1027,6 @@ static int sbp2_scan_unit_dir(struct sbp2_target *tgt, u32 *directory,
|
||||||
{
|
{
|
||||||
struct fw_csr_iterator ci;
|
struct fw_csr_iterator ci;
|
||||||
int key, value;
|
int key, value;
|
||||||
unsigned int timeout;
|
|
||||||
|
|
||||||
fw_csr_iterator_init(&ci, directory);
|
fw_csr_iterator_init(&ci, directory);
|
||||||
while (fw_csr_iterator_next(&ci, &key, &value)) {
|
while (fw_csr_iterator_next(&ci, &key, &value)) {
|
||||||
|
@ -1059,17 +1051,7 @@ static int sbp2_scan_unit_dir(struct sbp2_target *tgt, u32 *directory,
|
||||||
|
|
||||||
case SBP2_CSR_UNIT_CHARACTERISTICS:
|
case SBP2_CSR_UNIT_CHARACTERISTICS:
|
||||||
/* the timeout value is stored in 500ms units */
|
/* the timeout value is stored in 500ms units */
|
||||||
timeout = ((unsigned int) value >> 8 & 0xff) * 500;
|
tgt->mgt_orb_timeout = (value >> 8 & 0xff) * 500;
|
||||||
timeout = max(timeout, SBP2_MIN_LOGIN_ORB_TIMEOUT);
|
|
||||||
tgt->mgt_orb_timeout =
|
|
||||||
min(timeout, SBP2_MAX_LOGIN_ORB_TIMEOUT);
|
|
||||||
|
|
||||||
if (timeout > tgt->mgt_orb_timeout)
|
|
||||||
fw_notify("%s: config rom contains %ds "
|
|
||||||
"management ORB timeout, limiting "
|
|
||||||
"to %ds\n", tgt->bus_id,
|
|
||||||
timeout / 1000,
|
|
||||||
tgt->mgt_orb_timeout / 1000);
|
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case SBP2_CSR_LOGICAL_UNIT_NUMBER:
|
case SBP2_CSR_LOGICAL_UNIT_NUMBER:
|
||||||
|
@ -1087,6 +1069,22 @@ static int sbp2_scan_unit_dir(struct sbp2_target *tgt, u32 *directory,
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Per section 7.4.8 of the SBP-2 spec, a mgt_ORB_timeout value can be
|
||||||
|
* provided in the config rom. Most devices do provide a value, which
|
||||||
|
* we'll use for login management orbs, but with some sane limits.
|
||||||
|
*/
|
||||||
|
static void sbp2_clamp_management_orb_timeout(struct sbp2_target *tgt)
|
||||||
|
{
|
||||||
|
unsigned int timeout = tgt->mgt_orb_timeout;
|
||||||
|
|
||||||
|
if (timeout > 40000)
|
||||||
|
fw_notify("%s: %ds mgt_ORB_timeout limited to 40s\n",
|
||||||
|
tgt->bus_id, timeout / 1000);
|
||||||
|
|
||||||
|
tgt->mgt_orb_timeout = clamp_val(timeout, 5000, 40000);
|
||||||
|
}
|
||||||
|
|
||||||
static void sbp2_init_workarounds(struct sbp2_target *tgt, u32 model,
|
static void sbp2_init_workarounds(struct sbp2_target *tgt, u32 model,
|
||||||
u32 firmware_revision)
|
u32 firmware_revision)
|
||||||
{
|
{
|
||||||
|
@ -1171,6 +1169,7 @@ static int sbp2_probe(struct device *dev)
|
||||||
&firmware_revision) < 0)
|
&firmware_revision) < 0)
|
||||||
goto fail_tgt_put;
|
goto fail_tgt_put;
|
||||||
|
|
||||||
|
sbp2_clamp_management_orb_timeout(tgt);
|
||||||
sbp2_init_workarounds(tgt, model, firmware_revision);
|
sbp2_init_workarounds(tgt, model, firmware_revision);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -405,7 +405,11 @@ static int __init via_pmu_start(void)
|
||||||
printk(KERN_ERR "via-pmu: can't map interrupt\n");
|
printk(KERN_ERR "via-pmu: can't map interrupt\n");
|
||||||
return -ENODEV;
|
return -ENODEV;
|
||||||
}
|
}
|
||||||
if (request_irq(irq, via_pmu_interrupt, 0, "VIA-PMU", (void *)0)) {
|
/* We set IRQF_TIMER because we don't want the interrupt to be disabled
|
||||||
|
* between the 2 passes of driver suspend, we control our own disabling
|
||||||
|
* for that one
|
||||||
|
*/
|
||||||
|
if (request_irq(irq, via_pmu_interrupt, IRQF_TIMER, "VIA-PMU", (void *)0)) {
|
||||||
printk(KERN_ERR "via-pmu: can't request irq %d\n", irq);
|
printk(KERN_ERR "via-pmu: can't request irq %d\n", irq);
|
||||||
return -ENODEV;
|
return -ENODEV;
|
||||||
}
|
}
|
||||||
|
@ -419,7 +423,7 @@ static int __init via_pmu_start(void)
|
||||||
gpio_irq = irq_of_parse_and_map(gpio_node, 0);
|
gpio_irq = irq_of_parse_and_map(gpio_node, 0);
|
||||||
|
|
||||||
if (gpio_irq != NO_IRQ) {
|
if (gpio_irq != NO_IRQ) {
|
||||||
if (request_irq(gpio_irq, gpio1_interrupt, 0,
|
if (request_irq(gpio_irq, gpio1_interrupt, IRQF_TIMER,
|
||||||
"GPIO1 ADB", (void *)0))
|
"GPIO1 ADB", (void *)0))
|
||||||
printk(KERN_ERR "pmu: can't get irq %d"
|
printk(KERN_ERR "pmu: can't get irq %d"
|
||||||
" (GPIO1)\n", gpio_irq);
|
" (GPIO1)\n", gpio_irq);
|
||||||
|
@ -925,8 +929,7 @@ proc_write_options(struct file *file, const char __user *buffer,
|
||||||
|
|
||||||
#ifdef CONFIG_ADB
|
#ifdef CONFIG_ADB
|
||||||
/* Send an ADB command */
|
/* Send an ADB command */
|
||||||
static int
|
static int pmu_send_request(struct adb_request *req, int sync)
|
||||||
pmu_send_request(struct adb_request *req, int sync)
|
|
||||||
{
|
{
|
||||||
int i, ret;
|
int i, ret;
|
||||||
|
|
||||||
|
@ -1005,16 +1008,11 @@ pmu_send_request(struct adb_request *req, int sync)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Enable/disable autopolling */
|
/* Enable/disable autopolling */
|
||||||
static int
|
static int __pmu_adb_autopoll(int devs)
|
||||||
pmu_adb_autopoll(int devs)
|
|
||||||
{
|
{
|
||||||
struct adb_request req;
|
struct adb_request req;
|
||||||
|
|
||||||
if ((vias == NULL) || (!pmu_fully_inited) || !pmu_has_adb)
|
|
||||||
return -ENXIO;
|
|
||||||
|
|
||||||
if (devs) {
|
if (devs) {
|
||||||
adb_dev_map = devs;
|
|
||||||
pmu_request(&req, NULL, 5, PMU_ADB_CMD, 0, 0x86,
|
pmu_request(&req, NULL, 5, PMU_ADB_CMD, 0, 0x86,
|
||||||
adb_dev_map >> 8, adb_dev_map);
|
adb_dev_map >> 8, adb_dev_map);
|
||||||
pmu_adb_flags = 2;
|
pmu_adb_flags = 2;
|
||||||
|
@ -1027,9 +1025,17 @@ pmu_adb_autopoll(int devs)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int pmu_adb_autopoll(int devs)
|
||||||
|
{
|
||||||
|
if ((vias == NULL) || (!pmu_fully_inited) || !pmu_has_adb)
|
||||||
|
return -ENXIO;
|
||||||
|
|
||||||
|
adb_dev_map = devs;
|
||||||
|
return __pmu_adb_autopoll(devs);
|
||||||
|
}
|
||||||
|
|
||||||
/* Reset the ADB bus */
|
/* Reset the ADB bus */
|
||||||
static int
|
static int pmu_adb_reset_bus(void)
|
||||||
pmu_adb_reset_bus(void)
|
|
||||||
{
|
{
|
||||||
struct adb_request req;
|
struct adb_request req;
|
||||||
int save_autopoll = adb_dev_map;
|
int save_autopoll = adb_dev_map;
|
||||||
|
@ -1038,13 +1044,13 @@ pmu_adb_reset_bus(void)
|
||||||
return -ENXIO;
|
return -ENXIO;
|
||||||
|
|
||||||
/* anyone got a better idea?? */
|
/* anyone got a better idea?? */
|
||||||
pmu_adb_autopoll(0);
|
__pmu_adb_autopoll(0);
|
||||||
|
|
||||||
req.nbytes = 5;
|
req.nbytes = 4;
|
||||||
req.done = NULL;
|
req.done = NULL;
|
||||||
req.data[0] = PMU_ADB_CMD;
|
req.data[0] = PMU_ADB_CMD;
|
||||||
req.data[1] = 0;
|
req.data[1] = ADB_BUSRESET;
|
||||||
req.data[2] = ADB_BUSRESET;
|
req.data[2] = 0;
|
||||||
req.data[3] = 0;
|
req.data[3] = 0;
|
||||||
req.data[4] = 0;
|
req.data[4] = 0;
|
||||||
req.reply_len = 0;
|
req.reply_len = 0;
|
||||||
|
@ -1056,7 +1062,7 @@ pmu_adb_reset_bus(void)
|
||||||
pmu_wait_complete(&req);
|
pmu_wait_complete(&req);
|
||||||
|
|
||||||
if (save_autopoll != 0)
|
if (save_autopoll != 0)
|
||||||
pmu_adb_autopoll(save_autopoll);
|
__pmu_adb_autopoll(save_autopoll);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
@ -1741,6 +1741,7 @@ config KS8851
|
||||||
config KS8851_MLL
|
config KS8851_MLL
|
||||||
tristate "Micrel KS8851 MLL"
|
tristate "Micrel KS8851 MLL"
|
||||||
depends on HAS_IOMEM
|
depends on HAS_IOMEM
|
||||||
|
select MII
|
||||||
help
|
help
|
||||||
This platform driver is for Micrel KS8851 Address/data bus
|
This platform driver is for Micrel KS8851 Address/data bus
|
||||||
multiplexed network chip.
|
multiplexed network chip.
|
||||||
|
@ -2482,6 +2483,8 @@ config S6GMAC
|
||||||
To compile this driver as a module, choose M here. The module
|
To compile this driver as a module, choose M here. The module
|
||||||
will be called s6gmac.
|
will be called s6gmac.
|
||||||
|
|
||||||
|
source "drivers/net/stmmac/Kconfig"
|
||||||
|
|
||||||
endif # NETDEV_1000
|
endif # NETDEV_1000
|
||||||
|
|
||||||
#
|
#
|
||||||
|
@ -3230,4 +3233,12 @@ config VIRTIO_NET
|
||||||
This is the virtual network driver for virtio. It can be used with
|
This is the virtual network driver for virtio. It can be used with
|
||||||
lguest or QEMU based VMMs (like KVM or Xen). Say Y or M.
|
lguest or QEMU based VMMs (like KVM or Xen). Say Y or M.
|
||||||
|
|
||||||
|
config VMXNET3
|
||||||
|
tristate "VMware VMXNET3 ethernet driver"
|
||||||
|
depends on PCI && X86 && INET
|
||||||
|
help
|
||||||
|
This driver supports VMware's vmxnet3 virtual ethernet NIC.
|
||||||
|
To compile this driver as a module, choose M here: the
|
||||||
|
module will be called vmxnet3.
|
||||||
|
|
||||||
endif # NETDEVICES
|
endif # NETDEVICES
|
||||||
|
|
|
@ -2,6 +2,10 @@
|
||||||
# Makefile for the Linux network (ethercard) device drivers.
|
# Makefile for the Linux network (ethercard) device drivers.
|
||||||
#
|
#
|
||||||
|
|
||||||
|
obj-$(CONFIG_MII) += mii.o
|
||||||
|
obj-$(CONFIG_MDIO) += mdio.o
|
||||||
|
obj-$(CONFIG_PHYLIB) += phy/
|
||||||
|
|
||||||
obj-$(CONFIG_TI_DAVINCI_EMAC) += davinci_emac.o
|
obj-$(CONFIG_TI_DAVINCI_EMAC) += davinci_emac.o
|
||||||
|
|
||||||
obj-$(CONFIG_E1000) += e1000/
|
obj-$(CONFIG_E1000) += e1000/
|
||||||
|
@ -26,6 +30,7 @@ obj-$(CONFIG_TEHUTI) += tehuti.o
|
||||||
obj-$(CONFIG_ENIC) += enic/
|
obj-$(CONFIG_ENIC) += enic/
|
||||||
obj-$(CONFIG_JME) += jme.o
|
obj-$(CONFIG_JME) += jme.o
|
||||||
obj-$(CONFIG_BE2NET) += benet/
|
obj-$(CONFIG_BE2NET) += benet/
|
||||||
|
obj-$(CONFIG_VMXNET3) += vmxnet3/
|
||||||
|
|
||||||
gianfar_driver-objs := gianfar.o \
|
gianfar_driver-objs := gianfar.o \
|
||||||
gianfar_ethtool.o \
|
gianfar_ethtool.o \
|
||||||
|
@ -95,15 +100,12 @@ obj-$(CONFIG_VIA_VELOCITY) += via-velocity.o
|
||||||
obj-$(CONFIG_ADAPTEC_STARFIRE) += starfire.o
|
obj-$(CONFIG_ADAPTEC_STARFIRE) += starfire.o
|
||||||
obj-$(CONFIG_RIONET) += rionet.o
|
obj-$(CONFIG_RIONET) += rionet.o
|
||||||
obj-$(CONFIG_SH_ETH) += sh_eth.o
|
obj-$(CONFIG_SH_ETH) += sh_eth.o
|
||||||
|
obj-$(CONFIG_STMMAC_ETH) += stmmac/
|
||||||
|
|
||||||
#
|
#
|
||||||
# end link order section
|
# end link order section
|
||||||
#
|
#
|
||||||
|
|
||||||
obj-$(CONFIG_MII) += mii.o
|
|
||||||
obj-$(CONFIG_MDIO) += mdio.o
|
|
||||||
obj-$(CONFIG_PHYLIB) += phy/
|
|
||||||
|
|
||||||
obj-$(CONFIG_SUNDANCE) += sundance.o
|
obj-$(CONFIG_SUNDANCE) += sundance.o
|
||||||
obj-$(CONFIG_HAMACHI) += hamachi.o
|
obj-$(CONFIG_HAMACHI) += hamachi.o
|
||||||
obj-$(CONFIG_NET) += Space.o loopback.o
|
obj-$(CONFIG_NET) += Space.o loopback.o
|
||||||
|
|
|
@ -1209,7 +1209,8 @@ static int __devinit ace_init(struct net_device *dev)
|
||||||
memset(ap->info, 0, sizeof(struct ace_info));
|
memset(ap->info, 0, sizeof(struct ace_info));
|
||||||
memset(ap->skb, 0, sizeof(struct ace_skb));
|
memset(ap->skb, 0, sizeof(struct ace_skb));
|
||||||
|
|
||||||
if (ace_load_firmware(dev))
|
ecode = ace_load_firmware(dev);
|
||||||
|
if (ecode)
|
||||||
goto init_error;
|
goto init_error;
|
||||||
|
|
||||||
ap->fw_running = 0;
|
ap->fw_running = 0;
|
||||||
|
|
|
@ -213,6 +213,7 @@ static struct of_device_id __devinitdata sja1000_ofp_table[] = {
|
||||||
{.compatible = "nxp,sja1000"},
|
{.compatible = "nxp,sja1000"},
|
||||||
{},
|
{},
|
||||||
};
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, sja1000_ofp_table);
|
||||||
|
|
||||||
static struct of_platform_driver sja1000_ofp_driver = {
|
static struct of_platform_driver sja1000_ofp_driver = {
|
||||||
.owner = THIS_MODULE,
|
.owner = THIS_MODULE,
|
||||||
|
|
|
@ -333,6 +333,9 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
|
||||||
#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
|
#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
|
||||||
#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
|
#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
|
||||||
|
|
||||||
|
/* EMAC Stats Clear Mask */
|
||||||
|
#define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
|
||||||
|
|
||||||
/** net_buf_obj: EMAC network bufferdata structure
|
/** net_buf_obj: EMAC network bufferdata structure
|
||||||
*
|
*
|
||||||
* EMAC network buffer data structure
|
* EMAC network buffer data structure
|
||||||
|
@ -2548,40 +2551,49 @@ static int emac_dev_stop(struct net_device *ndev)
|
||||||
static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
|
static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
|
||||||
{
|
{
|
||||||
struct emac_priv *priv = netdev_priv(ndev);
|
struct emac_priv *priv = netdev_priv(ndev);
|
||||||
|
u32 mac_control;
|
||||||
|
u32 stats_clear_mask;
|
||||||
|
|
||||||
/* update emac hardware stats and reset the registers*/
|
/* update emac hardware stats and reset the registers*/
|
||||||
|
|
||||||
|
mac_control = emac_read(EMAC_MACCONTROL);
|
||||||
|
|
||||||
|
if (mac_control & EMAC_MACCONTROL_GMIIEN)
|
||||||
|
stats_clear_mask = EMAC_STATS_CLR_MASK;
|
||||||
|
else
|
||||||
|
stats_clear_mask = 0;
|
||||||
|
|
||||||
priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
|
priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
|
||||||
emac_write(EMAC_RXMCASTFRAMES, EMAC_ALL_MULTI_REG_VALUE);
|
emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
|
||||||
|
|
||||||
priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) +
|
priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) +
|
||||||
emac_read(EMAC_TXSINGLECOLL) +
|
emac_read(EMAC_TXSINGLECOLL) +
|
||||||
emac_read(EMAC_TXMULTICOLL));
|
emac_read(EMAC_TXMULTICOLL));
|
||||||
emac_write(EMAC_TXCOLLISION, EMAC_ALL_MULTI_REG_VALUE);
|
emac_write(EMAC_TXCOLLISION, stats_clear_mask);
|
||||||
emac_write(EMAC_TXSINGLECOLL, EMAC_ALL_MULTI_REG_VALUE);
|
emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
|
||||||
emac_write(EMAC_TXMULTICOLL, EMAC_ALL_MULTI_REG_VALUE);
|
emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
|
||||||
|
|
||||||
priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
|
priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
|
||||||
emac_read(EMAC_RXJABBER) +
|
emac_read(EMAC_RXJABBER) +
|
||||||
emac_read(EMAC_RXUNDERSIZED));
|
emac_read(EMAC_RXUNDERSIZED));
|
||||||
emac_write(EMAC_RXOVERSIZED, EMAC_ALL_MULTI_REG_VALUE);
|
emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
|
||||||
emac_write(EMAC_RXJABBER, EMAC_ALL_MULTI_REG_VALUE);
|
emac_write(EMAC_RXJABBER, stats_clear_mask);
|
||||||
emac_write(EMAC_RXUNDERSIZED, EMAC_ALL_MULTI_REG_VALUE);
|
emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
|
||||||
|
|
||||||
priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
|
priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
|
||||||
emac_read(EMAC_RXMOFOVERRUNS));
|
emac_read(EMAC_RXMOFOVERRUNS));
|
||||||
emac_write(EMAC_RXSOFOVERRUNS, EMAC_ALL_MULTI_REG_VALUE);
|
emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
|
||||||
emac_write(EMAC_RXMOFOVERRUNS, EMAC_ALL_MULTI_REG_VALUE);
|
emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
|
||||||
|
|
||||||
priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
|
priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
|
||||||
emac_write(EMAC_RXDMAOVERRUNS, EMAC_ALL_MULTI_REG_VALUE);
|
emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
|
||||||
|
|
||||||
priv->net_dev_stats.tx_carrier_errors +=
|
priv->net_dev_stats.tx_carrier_errors +=
|
||||||
emac_read(EMAC_TXCARRIERSENSE);
|
emac_read(EMAC_TXCARRIERSENSE);
|
||||||
emac_write(EMAC_TXCARRIERSENSE, EMAC_ALL_MULTI_REG_VALUE);
|
emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
|
||||||
|
|
||||||
priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN);
|
priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN);
|
||||||
emac_write(EMAC_TXUNDERRUN, EMAC_ALL_MULTI_REG_VALUE);
|
emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
|
||||||
|
|
||||||
return &priv->net_dev_stats;
|
return &priv->net_dev_stats;
|
||||||
}
|
}
|
||||||
|
|
|
@ -664,7 +664,8 @@ static int ethoc_open(struct net_device *dev)
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
/* calculate the number of TX/RX buffers, maximum 128 supported */
|
/* calculate the number of TX/RX buffers, maximum 128 supported */
|
||||||
num_bd = min(128, (dev->mem_end - dev->mem_start + 1) / ETHOC_BUFSIZ);
|
num_bd = min_t(unsigned int,
|
||||||
|
128, (dev->mem_end - dev->mem_start + 1) / ETHOC_BUFSIZ);
|
||||||
priv->num_tx = max(min_tx, num_bd / 4);
|
priv->num_tx = max(min_tx, num_bd / 4);
|
||||||
priv->num_rx = num_bd - priv->num_tx;
|
priv->num_rx = num_bd - priv->num_tx;
|
||||||
ethoc_write(priv, TX_BD_NUM, priv->num_tx);
|
ethoc_write(priv, TX_BD_NUM, priv->num_tx);
|
||||||
|
|
|
@ -759,12 +759,6 @@ static void mpc52xx_fec_reset(struct net_device *dev)
|
||||||
|
|
||||||
mpc52xx_fec_hw_init(dev);
|
mpc52xx_fec_hw_init(dev);
|
||||||
|
|
||||||
if (priv->phydev) {
|
|
||||||
phy_stop(priv->phydev);
|
|
||||||
phy_write(priv->phydev, MII_BMCR, BMCR_RESET);
|
|
||||||
phy_start(priv->phydev);
|
|
||||||
}
|
|
||||||
|
|
||||||
bcom_fec_rx_reset(priv->rx_dmatsk);
|
bcom_fec_rx_reset(priv->rx_dmatsk);
|
||||||
bcom_fec_tx_reset(priv->tx_dmatsk);
|
bcom_fec_tx_reset(priv->tx_dmatsk);
|
||||||
|
|
||||||
|
|
|
@ -155,6 +155,7 @@ static struct of_device_id mpc52xx_fec_mdio_match[] = {
|
||||||
{ .compatible = "mpc5200b-fec-phy", },
|
{ .compatible = "mpc5200b-fec-phy", },
|
||||||
{}
|
{}
|
||||||
};
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, mpc52xx_fec_mdio_match);
|
||||||
|
|
||||||
struct of_platform_driver mpc52xx_fec_mdio_driver = {
|
struct of_platform_driver mpc52xx_fec_mdio_driver = {
|
||||||
.name = "mpc5200b-fec-phy",
|
.name = "mpc5200b-fec-phy",
|
||||||
|
|
|
@ -1110,6 +1110,7 @@ static struct of_device_id fs_enet_match[] = {
|
||||||
#endif
|
#endif
|
||||||
{}
|
{}
|
||||||
};
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, fs_enet_match);
|
||||||
|
|
||||||
static struct of_platform_driver fs_enet_driver = {
|
static struct of_platform_driver fs_enet_driver = {
|
||||||
.name = "fs_enet",
|
.name = "fs_enet",
|
||||||
|
|
|
@ -221,6 +221,7 @@ static struct of_device_id fs_enet_mdio_bb_match[] = {
|
||||||
},
|
},
|
||||||
{},
|
{},
|
||||||
};
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, fs_enet_mdio_bb_match);
|
||||||
|
|
||||||
static struct of_platform_driver fs_enet_bb_mdio_driver = {
|
static struct of_platform_driver fs_enet_bb_mdio_driver = {
|
||||||
.name = "fsl-bb-mdio",
|
.name = "fsl-bb-mdio",
|
||||||
|
|
|
@ -219,6 +219,7 @@ static struct of_device_id fs_enet_mdio_fec_match[] = {
|
||||||
#endif
|
#endif
|
||||||
{},
|
{},
|
||||||
};
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, fs_enet_mdio_fec_match);
|
||||||
|
|
||||||
static struct of_platform_driver fs_enet_fec_mdio_driver = {
|
static struct of_platform_driver fs_enet_fec_mdio_driver = {
|
||||||
.name = "fsl-fec-mdio",
|
.name = "fsl-fec-mdio",
|
||||||
|
|
|
@ -407,6 +407,7 @@ static struct of_device_id fsl_pq_mdio_match[] = {
|
||||||
},
|
},
|
||||||
{},
|
{},
|
||||||
};
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
|
||||||
|
|
||||||
static struct of_platform_driver fsl_pq_mdio_driver = {
|
static struct of_platform_driver fsl_pq_mdio_driver = {
|
||||||
.name = "fsl-pq_mdio",
|
.name = "fsl-pq_mdio",
|
||||||
|
|
|
@ -2325,9 +2325,6 @@ static irqreturn_t gfar_error(int irq, void *dev_id)
|
||||||
return IRQ_HANDLED;
|
return IRQ_HANDLED;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* work with hotplug and coldplug */
|
|
||||||
MODULE_ALIAS("platform:fsl-gianfar");
|
|
||||||
|
|
||||||
static struct of_device_id gfar_match[] =
|
static struct of_device_id gfar_match[] =
|
||||||
{
|
{
|
||||||
{
|
{
|
||||||
|
@ -2336,6 +2333,7 @@ static struct of_device_id gfar_match[] =
|
||||||
},
|
},
|
||||||
{},
|
{},
|
||||||
};
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, gfar_match);
|
||||||
|
|
||||||
/* Structure for a device driver */
|
/* Structure for a device driver */
|
||||||
static struct of_platform_driver gfar_driver = {
|
static struct of_platform_driver gfar_driver = {
|
||||||
|
|
|
@ -24,6 +24,7 @@
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include <linux/module.h>
|
||||||
#include <linux/sched.h>
|
#include <linux/sched.h>
|
||||||
#include <linux/string.h>
|
#include <linux/string.h>
|
||||||
#include <linux/errno.h>
|
#include <linux/errno.h>
|
||||||
|
@ -443,7 +444,7 @@ static u32 __emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_s
|
||||||
ret |= EMAC_MR1_TFS_2K;
|
ret |= EMAC_MR1_TFS_2K;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
|
printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
|
||||||
dev->ndev->name, tx_size);
|
dev->ndev->name, tx_size);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -470,6 +471,9 @@ static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_
|
||||||
DBG2(dev, "__emac4_calc_base_mr1" NL);
|
DBG2(dev, "__emac4_calc_base_mr1" NL);
|
||||||
|
|
||||||
switch(tx_size) {
|
switch(tx_size) {
|
||||||
|
case 16384:
|
||||||
|
ret |= EMAC4_MR1_TFS_16K;
|
||||||
|
break;
|
||||||
case 4096:
|
case 4096:
|
||||||
ret |= EMAC4_MR1_TFS_4K;
|
ret |= EMAC4_MR1_TFS_4K;
|
||||||
break;
|
break;
|
||||||
|
@ -477,7 +481,7 @@ static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_
|
||||||
ret |= EMAC4_MR1_TFS_2K;
|
ret |= EMAC4_MR1_TFS_2K;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
|
printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
|
||||||
dev->ndev->name, tx_size);
|
dev->ndev->name, tx_size);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -2985,6 +2989,7 @@ static struct of_device_id emac_match[] =
|
||||||
},
|
},
|
||||||
{},
|
{},
|
||||||
};
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, emac_match);
|
||||||
|
|
||||||
static struct of_platform_driver emac_driver = {
|
static struct of_platform_driver emac_driver = {
|
||||||
.name = "emac",
|
.name = "emac",
|
||||||
|
|
|
@ -153,6 +153,7 @@ struct emac_regs {
|
||||||
#define EMAC4_MR1_RFS_16K 0x00280000
|
#define EMAC4_MR1_RFS_16K 0x00280000
|
||||||
#define EMAC4_MR1_TFS_2K 0x00020000
|
#define EMAC4_MR1_TFS_2K 0x00020000
|
||||||
#define EMAC4_MR1_TFS_4K 0x00030000
|
#define EMAC4_MR1_TFS_4K 0x00030000
|
||||||
|
#define EMAC4_MR1_TFS_16K 0x00050000
|
||||||
#define EMAC4_MR1_TR 0x00008000
|
#define EMAC4_MR1_TR 0x00008000
|
||||||
#define EMAC4_MR1_MWSW_001 0x00001000
|
#define EMAC4_MR1_MWSW_001 0x00001000
|
||||||
#define EMAC4_MR1_JPSM 0x00000800
|
#define EMAC4_MR1_JPSM 0x00000800
|
||||||
|
|
|
@ -232,8 +232,11 @@ static int sa1100_irda_startup(struct sa1100_irda *si)
|
||||||
/*
|
/*
|
||||||
* Ensure that the ports for this device are setup correctly.
|
* Ensure that the ports for this device are setup correctly.
|
||||||
*/
|
*/
|
||||||
if (si->pdata->startup)
|
if (si->pdata->startup) {
|
||||||
si->pdata->startup(si->dev);
|
ret = si->pdata->startup(si->dev);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Configure PPC for IRDA - we want to drive TXD2 low.
|
* Configure PPC for IRDA - we want to drive TXD2 low.
|
||||||
|
|
|
@ -119,24 +119,9 @@ static struct ixp2400_msf_parameters enp2611_msf_parameters =
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
struct enp2611_ixpdev_priv
|
|
||||||
{
|
|
||||||
struct ixpdev_priv ixpdev_priv;
|
|
||||||
struct net_device_stats stats;
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct net_device *nds[3];
|
static struct net_device *nds[3];
|
||||||
static struct timer_list link_check_timer;
|
static struct timer_list link_check_timer;
|
||||||
|
|
||||||
static struct net_device_stats *enp2611_get_stats(struct net_device *dev)
|
|
||||||
{
|
|
||||||
struct enp2611_ixpdev_priv *ip = netdev_priv(dev);
|
|
||||||
|
|
||||||
pm3386_get_stats(ip->ixpdev_priv.channel, &(ip->stats));
|
|
||||||
|
|
||||||
return &(ip->stats);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* @@@ Poll the SFP moddef0 line too. */
|
/* @@@ Poll the SFP moddef0 line too. */
|
||||||
/* @@@ Try to use the pm3386 DOOL interrupt as well. */
|
/* @@@ Try to use the pm3386 DOOL interrupt as well. */
|
||||||
static void enp2611_check_link_status(unsigned long __dummy)
|
static void enp2611_check_link_status(unsigned long __dummy)
|
||||||
|
@ -203,14 +188,13 @@ static int __init enp2611_init_module(void)
|
||||||
|
|
||||||
ports = pm3386_port_count();
|
ports = pm3386_port_count();
|
||||||
for (i = 0; i < ports; i++) {
|
for (i = 0; i < ports; i++) {
|
||||||
nds[i] = ixpdev_alloc(i, sizeof(struct enp2611_ixpdev_priv));
|
nds[i] = ixpdev_alloc(i, sizeof(struct ixpdev_priv));
|
||||||
if (nds[i] == NULL) {
|
if (nds[i] == NULL) {
|
||||||
while (--i >= 0)
|
while (--i >= 0)
|
||||||
free_netdev(nds[i]);
|
free_netdev(nds[i]);
|
||||||
return -ENOMEM;
|
return -ENOMEM;
|
||||||
}
|
}
|
||||||
|
|
||||||
nds[i]->get_stats = enp2611_get_stats;
|
|
||||||
pm3386_init_port(i);
|
pm3386_init_port(i);
|
||||||
pm3386_get_mac(i, nds[i]->dev_addr);
|
pm3386_get_mac(i, nds[i]->dev_addr);
|
||||||
}
|
}
|
||||||
|
|
|
@ -21,6 +21,7 @@
|
||||||
#include "ixp2400_tx.ucode"
|
#include "ixp2400_tx.ucode"
|
||||||
#include "ixpdev_priv.h"
|
#include "ixpdev_priv.h"
|
||||||
#include "ixpdev.h"
|
#include "ixpdev.h"
|
||||||
|
#include "pm3386.h"
|
||||||
|
|
||||||
#define DRV_MODULE_VERSION "0.2"
|
#define DRV_MODULE_VERSION "0.2"
|
||||||
|
|
||||||
|
@ -271,6 +272,15 @@ static int ixpdev_close(struct net_device *dev)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static struct net_device_stats *ixpdev_get_stats(struct net_device *dev)
|
||||||
|
{
|
||||||
|
struct ixpdev_priv *ip = netdev_priv(dev);
|
||||||
|
|
||||||
|
pm3386_get_stats(ip->channel, &(dev->stats));
|
||||||
|
|
||||||
|
return &(dev->stats);
|
||||||
|
}
|
||||||
|
|
||||||
static const struct net_device_ops ixpdev_netdev_ops = {
|
static const struct net_device_ops ixpdev_netdev_ops = {
|
||||||
.ndo_open = ixpdev_open,
|
.ndo_open = ixpdev_open,
|
||||||
.ndo_stop = ixpdev_close,
|
.ndo_stop = ixpdev_close,
|
||||||
|
@ -278,6 +288,7 @@ static const struct net_device_ops ixpdev_netdev_ops = {
|
||||||
.ndo_change_mtu = eth_change_mtu,
|
.ndo_change_mtu = eth_change_mtu,
|
||||||
.ndo_validate_addr = eth_validate_addr,
|
.ndo_validate_addr = eth_validate_addr,
|
||||||
.ndo_set_mac_address = eth_mac_addr,
|
.ndo_set_mac_address = eth_mac_addr,
|
||||||
|
.ndo_get_stats = ixpdev_get_stats,
|
||||||
#ifdef CONFIG_NET_POLL_CONTROLLER
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
||||||
.ndo_poll_controller = ixpdev_poll_controller,
|
.ndo_poll_controller = ixpdev_poll_controller,
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -595,7 +595,8 @@ netxen_setup_pci_map(struct netxen_adapter *adapter)
|
||||||
void __iomem *mem_ptr2 = NULL;
|
void __iomem *mem_ptr2 = NULL;
|
||||||
void __iomem *db_ptr = NULL;
|
void __iomem *db_ptr = NULL;
|
||||||
|
|
||||||
unsigned long mem_base, mem_len, db_base, db_len = 0, pci_len0 = 0;
|
resource_size_t mem_base, db_base;
|
||||||
|
unsigned long mem_len, db_len = 0, pci_len0 = 0;
|
||||||
|
|
||||||
struct pci_dev *pdev = adapter->pdev;
|
struct pci_dev *pdev = adapter->pdev;
|
||||||
int pci_func = adapter->ahw.pci_func;
|
int pci_func = adapter->ahw.pci_func;
|
||||||
|
|
|
@ -251,6 +251,7 @@ static void el3_tx_timeout(struct net_device *dev);
|
||||||
static int el3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
|
static int el3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
|
||||||
static const struct ethtool_ops netdev_ethtool_ops;
|
static const struct ethtool_ops netdev_ethtool_ops;
|
||||||
static void set_rx_mode(struct net_device *dev);
|
static void set_rx_mode(struct net_device *dev);
|
||||||
|
static void set_multicast_list(struct net_device *dev);
|
||||||
|
|
||||||
static void tc574_detach(struct pcmcia_device *p_dev);
|
static void tc574_detach(struct pcmcia_device *p_dev);
|
||||||
|
|
||||||
|
@ -266,7 +267,7 @@ static const struct net_device_ops el3_netdev_ops = {
|
||||||
.ndo_tx_timeout = el3_tx_timeout,
|
.ndo_tx_timeout = el3_tx_timeout,
|
||||||
.ndo_get_stats = el3_get_stats,
|
.ndo_get_stats = el3_get_stats,
|
||||||
.ndo_do_ioctl = el3_ioctl,
|
.ndo_do_ioctl = el3_ioctl,
|
||||||
.ndo_set_multicast_list = set_rx_mode,
|
.ndo_set_multicast_list = set_multicast_list,
|
||||||
.ndo_change_mtu = eth_change_mtu,
|
.ndo_change_mtu = eth_change_mtu,
|
||||||
.ndo_set_mac_address = eth_mac_addr,
|
.ndo_set_mac_address = eth_mac_addr,
|
||||||
.ndo_validate_addr = eth_validate_addr,
|
.ndo_validate_addr = eth_validate_addr,
|
||||||
|
@ -1161,6 +1162,16 @@ static void set_rx_mode(struct net_device *dev)
|
||||||
outw(SetRxFilter | RxStation | RxBroadcast, ioaddr + EL3_CMD);
|
outw(SetRxFilter | RxStation | RxBroadcast, ioaddr + EL3_CMD);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void set_multicast_list(struct net_device *dev)
|
||||||
|
{
|
||||||
|
struct el3_private *lp = netdev_priv(dev);
|
||||||
|
unsigned long flags;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&lp->window_lock, flags);
|
||||||
|
set_rx_mode(dev);
|
||||||
|
spin_unlock_irqrestore(&lp->window_lock, flags);
|
||||||
|
}
|
||||||
|
|
||||||
static int el3_close(struct net_device *dev)
|
static int el3_close(struct net_device *dev)
|
||||||
{
|
{
|
||||||
unsigned int ioaddr = dev->base_addr;
|
unsigned int ioaddr = dev->base_addr;
|
||||||
|
|
|
@ -238,6 +238,7 @@ static struct of_device_id mdio_ofgpio_match[] = {
|
||||||
},
|
},
|
||||||
{},
|
{},
|
||||||
};
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, mdio_ofgpio_match);
|
||||||
|
|
||||||
static struct of_platform_driver mdio_ofgpio_driver = {
|
static struct of_platform_driver mdio_ofgpio_driver = {
|
||||||
.name = "mdio-gpio",
|
.name = "mdio-gpio",
|
||||||
|
|
|
@ -803,6 +803,12 @@ enum {
|
||||||
MB_CMD_SET_PORT_CFG = 0x00000122,
|
MB_CMD_SET_PORT_CFG = 0x00000122,
|
||||||
MB_CMD_GET_PORT_CFG = 0x00000123,
|
MB_CMD_GET_PORT_CFG = 0x00000123,
|
||||||
MB_CMD_GET_LINK_STS = 0x00000124,
|
MB_CMD_GET_LINK_STS = 0x00000124,
|
||||||
|
MB_CMD_SET_MGMNT_TFK_CTL = 0x00000160, /* Set Mgmnt Traffic Control */
|
||||||
|
MB_SET_MPI_TFK_STOP = (1 << 0),
|
||||||
|
MB_SET_MPI_TFK_RESUME = (1 << 1),
|
||||||
|
MB_CMD_GET_MGMNT_TFK_CTL = 0x00000161, /* Get Mgmnt Traffic Control */
|
||||||
|
MB_GET_MPI_TFK_STOPPED = (1 << 0),
|
||||||
|
MB_GET_MPI_TFK_FIFO_EMPTY = (1 << 1),
|
||||||
|
|
||||||
/* Mailbox Command Status. */
|
/* Mailbox Command Status. */
|
||||||
MB_CMD_STS_GOOD = 0x00004000, /* Success. */
|
MB_CMD_STS_GOOD = 0x00004000, /* Success. */
|
||||||
|
@ -1168,7 +1174,7 @@ struct ricb {
|
||||||
#define RSS_RI6 0x40
|
#define RSS_RI6 0x40
|
||||||
#define RSS_RT6 0x80
|
#define RSS_RT6 0x80
|
||||||
__le16 mask;
|
__le16 mask;
|
||||||
__le32 hash_cq_id[256];
|
u8 hash_cq_id[1024];
|
||||||
__le32 ipv6_hash_key[10];
|
__le32 ipv6_hash_key[10];
|
||||||
__le32 ipv4_hash_key[4];
|
__le32 ipv4_hash_key[4];
|
||||||
} __attribute((packed));
|
} __attribute((packed));
|
||||||
|
@ -1606,6 +1612,8 @@ int ql_read_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
|
||||||
int ql_mb_about_fw(struct ql_adapter *qdev);
|
int ql_mb_about_fw(struct ql_adapter *qdev);
|
||||||
void ql_link_on(struct ql_adapter *qdev);
|
void ql_link_on(struct ql_adapter *qdev);
|
||||||
void ql_link_off(struct ql_adapter *qdev);
|
void ql_link_off(struct ql_adapter *qdev);
|
||||||
|
int ql_mb_set_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 control);
|
||||||
|
int ql_wait_fifo_empty(struct ql_adapter *qdev);
|
||||||
|
|
||||||
#if 1
|
#if 1
|
||||||
#define QL_ALL_DUMP
|
#define QL_ALL_DUMP
|
||||||
|
|
|
@ -320,6 +320,37 @@ static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
|
||||||
|
|
||||||
switch (type) {
|
switch (type) {
|
||||||
case MAC_ADDR_TYPE_MULTI_MAC:
|
case MAC_ADDR_TYPE_MULTI_MAC:
|
||||||
|
{
|
||||||
|
u32 upper = (addr[0] << 8) | addr[1];
|
||||||
|
u32 lower = (addr[2] << 24) | (addr[3] << 16) |
|
||||||
|
(addr[4] << 8) | (addr[5]);
|
||||||
|
|
||||||
|
status =
|
||||||
|
ql_wait_reg_rdy(qdev,
|
||||||
|
MAC_ADDR_IDX, MAC_ADDR_MW, 0);
|
||||||
|
if (status)
|
||||||
|
goto exit;
|
||||||
|
ql_write32(qdev, MAC_ADDR_IDX, (offset++) |
|
||||||
|
(index << MAC_ADDR_IDX_SHIFT) |
|
||||||
|
type | MAC_ADDR_E);
|
||||||
|
ql_write32(qdev, MAC_ADDR_DATA, lower);
|
||||||
|
status =
|
||||||
|
ql_wait_reg_rdy(qdev,
|
||||||
|
MAC_ADDR_IDX, MAC_ADDR_MW, 0);
|
||||||
|
if (status)
|
||||||
|
goto exit;
|
||||||
|
ql_write32(qdev, MAC_ADDR_IDX, (offset++) |
|
||||||
|
(index << MAC_ADDR_IDX_SHIFT) |
|
||||||
|
type | MAC_ADDR_E);
|
||||||
|
|
||||||
|
ql_write32(qdev, MAC_ADDR_DATA, upper);
|
||||||
|
status =
|
||||||
|
ql_wait_reg_rdy(qdev,
|
||||||
|
MAC_ADDR_IDX, MAC_ADDR_MW, 0);
|
||||||
|
if (status)
|
||||||
|
goto exit;
|
||||||
|
break;
|
||||||
|
}
|
||||||
case MAC_ADDR_TYPE_CAM_MAC:
|
case MAC_ADDR_TYPE_CAM_MAC:
|
||||||
{
|
{
|
||||||
u32 cam_output;
|
u32 cam_output;
|
||||||
|
@ -365,16 +396,14 @@ static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
|
||||||
and possibly the function id. Right now we hardcode
|
and possibly the function id. Right now we hardcode
|
||||||
the route field to NIC core.
|
the route field to NIC core.
|
||||||
*/
|
*/
|
||||||
if (type == MAC_ADDR_TYPE_CAM_MAC) {
|
cam_output = (CAM_OUT_ROUTE_NIC |
|
||||||
cam_output = (CAM_OUT_ROUTE_NIC |
|
(qdev->
|
||||||
(qdev->
|
func << CAM_OUT_FUNC_SHIFT) |
|
||||||
func << CAM_OUT_FUNC_SHIFT) |
|
(0 << CAM_OUT_CQ_ID_SHIFT));
|
||||||
(0 << CAM_OUT_CQ_ID_SHIFT));
|
if (qdev->vlgrp)
|
||||||
if (qdev->vlgrp)
|
cam_output |= CAM_OUT_RV;
|
||||||
cam_output |= CAM_OUT_RV;
|
/* route to NIC core */
|
||||||
/* route to NIC core */
|
ql_write32(qdev, MAC_ADDR_DATA, cam_output);
|
||||||
ql_write32(qdev, MAC_ADDR_DATA, cam_output);
|
|
||||||
}
|
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case MAC_ADDR_TYPE_VLAN:
|
case MAC_ADDR_TYPE_VLAN:
|
||||||
|
@ -546,14 +575,14 @@ static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
|
||||||
}
|
}
|
||||||
case RT_IDX_MCAST: /* Pass up All Multicast frames. */
|
case RT_IDX_MCAST: /* Pass up All Multicast frames. */
|
||||||
{
|
{
|
||||||
value = RT_IDX_DST_CAM_Q | /* dest */
|
value = RT_IDX_DST_DFLT_Q | /* dest */
|
||||||
RT_IDX_TYPE_NICQ | /* type */
|
RT_IDX_TYPE_NICQ | /* type */
|
||||||
(RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
|
(RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case RT_IDX_MCAST_MATCH: /* Pass up matched Multicast frames. */
|
case RT_IDX_MCAST_MATCH: /* Pass up matched Multicast frames. */
|
||||||
{
|
{
|
||||||
value = RT_IDX_DST_CAM_Q | /* dest */
|
value = RT_IDX_DST_DFLT_Q | /* dest */
|
||||||
RT_IDX_TYPE_NICQ | /* type */
|
RT_IDX_TYPE_NICQ | /* type */
|
||||||
(RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
|
(RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
|
||||||
break;
|
break;
|
||||||
|
@ -3077,6 +3106,12 @@ static int ql_request_irq(struct ql_adapter *qdev)
|
||||||
|
|
||||||
static int ql_start_rss(struct ql_adapter *qdev)
|
static int ql_start_rss(struct ql_adapter *qdev)
|
||||||
{
|
{
|
||||||
|
u8 init_hash_seed[] = {0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2,
|
||||||
|
0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f,
|
||||||
|
0xb0, 0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b,
|
||||||
|
0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80,
|
||||||
|
0x30, 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b,
|
||||||
|
0xbe, 0xac, 0x01, 0xfa};
|
||||||
struct ricb *ricb = &qdev->ricb;
|
struct ricb *ricb = &qdev->ricb;
|
||||||
int status = 0;
|
int status = 0;
|
||||||
int i;
|
int i;
|
||||||
|
@ -3086,21 +3121,17 @@ static int ql_start_rss(struct ql_adapter *qdev)
|
||||||
|
|
||||||
ricb->base_cq = RSS_L4K;
|
ricb->base_cq = RSS_L4K;
|
||||||
ricb->flags =
|
ricb->flags =
|
||||||
(RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
|
(RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RT4 | RSS_RT6);
|
||||||
RSS_RT6);
|
ricb->mask = cpu_to_le16((u16)(0x3ff));
|
||||||
ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Fill out the Indirection Table.
|
* Fill out the Indirection Table.
|
||||||
*/
|
*/
|
||||||
for (i = 0; i < 256; i++)
|
for (i = 0; i < 1024; i++)
|
||||||
hash_id[i] = i & (qdev->rss_ring_count - 1);
|
hash_id[i] = (i & (qdev->rss_ring_count - 1));
|
||||||
|
|
||||||
/*
|
memcpy((void *)&ricb->ipv6_hash_key[0], init_hash_seed, 40);
|
||||||
* Random values for the IPv6 and IPv4 Hash Keys.
|
memcpy((void *)&ricb->ipv4_hash_key[0], init_hash_seed, 16);
|
||||||
*/
|
|
||||||
get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
|
|
||||||
get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
|
|
||||||
|
|
||||||
QPRINTK(qdev, IFUP, DEBUG, "Initializing RSS.\n");
|
QPRINTK(qdev, IFUP, DEBUG, "Initializing RSS.\n");
|
||||||
|
|
||||||
|
@ -3239,6 +3270,13 @@ static int ql_adapter_initialize(struct ql_adapter *qdev)
|
||||||
ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
|
ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
|
||||||
min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
|
min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
|
||||||
|
|
||||||
|
/* Set RX packet routing to use port/pci function on which the
|
||||||
|
* packet arrived on in addition to usual frame routing.
|
||||||
|
* This is helpful on bonding where both interfaces can have
|
||||||
|
* the same MAC address.
|
||||||
|
*/
|
||||||
|
ql_write32(qdev, RST_FO, RST_FO_RR_MASK | RST_FO_RR_RCV_FUNC_CQ);
|
||||||
|
|
||||||
/* Start up the rx queues. */
|
/* Start up the rx queues. */
|
||||||
for (i = 0; i < qdev->rx_ring_count; i++) {
|
for (i = 0; i < qdev->rx_ring_count; i++) {
|
||||||
status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
|
status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
|
||||||
|
@ -3311,6 +3349,13 @@ static int ql_adapter_reset(struct ql_adapter *qdev)
|
||||||
|
|
||||||
end_jiffies = jiffies +
|
end_jiffies = jiffies +
|
||||||
max((unsigned long)1, usecs_to_jiffies(30));
|
max((unsigned long)1, usecs_to_jiffies(30));
|
||||||
|
|
||||||
|
/* Stop management traffic. */
|
||||||
|
ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_STOP);
|
||||||
|
|
||||||
|
/* Wait for the NIC and MGMNT FIFOs to empty. */
|
||||||
|
ql_wait_fifo_empty(qdev);
|
||||||
|
|
||||||
ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
|
ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
|
||||||
|
|
||||||
do {
|
do {
|
||||||
|
@ -3326,6 +3371,8 @@ static int ql_adapter_reset(struct ql_adapter *qdev)
|
||||||
status = -ETIMEDOUT;
|
status = -ETIMEDOUT;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* Resume management traffic. */
|
||||||
|
ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_RESUME);
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -3704,6 +3751,12 @@ static void ql_asic_reset_work(struct work_struct *work)
|
||||||
status = ql_adapter_up(qdev);
|
status = ql_adapter_up(qdev);
|
||||||
if (status)
|
if (status)
|
||||||
goto error;
|
goto error;
|
||||||
|
|
||||||
|
/* Restore rx mode. */
|
||||||
|
clear_bit(QL_ALLMULTI, &qdev->flags);
|
||||||
|
clear_bit(QL_PROMISCUOUS, &qdev->flags);
|
||||||
|
qlge_set_multicast_list(qdev->ndev);
|
||||||
|
|
||||||
rtnl_unlock();
|
rtnl_unlock();
|
||||||
return;
|
return;
|
||||||
error:
|
error:
|
||||||
|
|
|
@ -768,6 +768,95 @@ static int ql_idc_wait(struct ql_adapter *qdev)
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
int ql_mb_set_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 control)
|
||||||
|
{
|
||||||
|
struct mbox_params mbc;
|
||||||
|
struct mbox_params *mbcp = &mbc;
|
||||||
|
int status;
|
||||||
|
|
||||||
|
memset(mbcp, 0, sizeof(struct mbox_params));
|
||||||
|
|
||||||
|
mbcp->in_count = 1;
|
||||||
|
mbcp->out_count = 2;
|
||||||
|
|
||||||
|
mbcp->mbox_in[0] = MB_CMD_SET_MGMNT_TFK_CTL;
|
||||||
|
mbcp->mbox_in[1] = control;
|
||||||
|
|
||||||
|
status = ql_mailbox_command(qdev, mbcp);
|
||||||
|
if (status)
|
||||||
|
return status;
|
||||||
|
|
||||||
|
if (mbcp->mbox_out[0] == MB_CMD_STS_GOOD)
|
||||||
|
return status;
|
||||||
|
|
||||||
|
if (mbcp->mbox_out[0] == MB_CMD_STS_INVLD_CMD) {
|
||||||
|
QPRINTK(qdev, DRV, ERR,
|
||||||
|
"Command not supported by firmware.\n");
|
||||||
|
status = -EINVAL;
|
||||||
|
} else if (mbcp->mbox_out[0] == MB_CMD_STS_ERR) {
|
||||||
|
/* This indicates that the firmware is
|
||||||
|
* already in the state we are trying to
|
||||||
|
* change it to.
|
||||||
|
*/
|
||||||
|
QPRINTK(qdev, DRV, ERR,
|
||||||
|
"Command parameters make no change.\n");
|
||||||
|
}
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Returns a negative error code or the mailbox command status. */
|
||||||
|
static int ql_mb_get_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 *control)
|
||||||
|
{
|
||||||
|
struct mbox_params mbc;
|
||||||
|
struct mbox_params *mbcp = &mbc;
|
||||||
|
int status;
|
||||||
|
|
||||||
|
memset(mbcp, 0, sizeof(struct mbox_params));
|
||||||
|
*control = 0;
|
||||||
|
|
||||||
|
mbcp->in_count = 1;
|
||||||
|
mbcp->out_count = 1;
|
||||||
|
|
||||||
|
mbcp->mbox_in[0] = MB_CMD_GET_MGMNT_TFK_CTL;
|
||||||
|
|
||||||
|
status = ql_mailbox_command(qdev, mbcp);
|
||||||
|
if (status)
|
||||||
|
return status;
|
||||||
|
|
||||||
|
if (mbcp->mbox_out[0] == MB_CMD_STS_GOOD) {
|
||||||
|
*control = mbcp->mbox_in[1];
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (mbcp->mbox_out[0] == MB_CMD_STS_INVLD_CMD) {
|
||||||
|
QPRINTK(qdev, DRV, ERR,
|
||||||
|
"Command not supported by firmware.\n");
|
||||||
|
status = -EINVAL;
|
||||||
|
} else if (mbcp->mbox_out[0] == MB_CMD_STS_ERR) {
|
||||||
|
QPRINTK(qdev, DRV, ERR,
|
||||||
|
"Failed to get MPI traffic control.\n");
|
||||||
|
status = -EIO;
|
||||||
|
}
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
int ql_wait_fifo_empty(struct ql_adapter *qdev)
|
||||||
|
{
|
||||||
|
int count = 5;
|
||||||
|
u32 mgmnt_fifo_empty;
|
||||||
|
u32 nic_fifo_empty;
|
||||||
|
|
||||||
|
do {
|
||||||
|
nic_fifo_empty = ql_read32(qdev, STS) & STS_NFE;
|
||||||
|
ql_mb_get_mgmnt_traffic_ctl(qdev, &mgmnt_fifo_empty);
|
||||||
|
mgmnt_fifo_empty &= MB_GET_MPI_TFK_FIFO_EMPTY;
|
||||||
|
if (nic_fifo_empty && mgmnt_fifo_empty)
|
||||||
|
return 0;
|
||||||
|
msleep(100);
|
||||||
|
} while (count-- > 0);
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
}
|
||||||
|
|
||||||
/* API called in work thread context to set new TX/RX
|
/* API called in work thread context to set new TX/RX
|
||||||
* maximum frame size values to match MTU.
|
* maximum frame size values to match MTU.
|
||||||
*/
|
*/
|
||||||
|
@ -876,6 +965,8 @@ void ql_mpi_work(struct work_struct *work)
|
||||||
int err = 0;
|
int err = 0;
|
||||||
|
|
||||||
rtnl_lock();
|
rtnl_lock();
|
||||||
|
/* Begin polled mode for MPI */
|
||||||
|
ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
|
||||||
|
|
||||||
while (ql_read32(qdev, STS) & STS_PI) {
|
while (ql_read32(qdev, STS) & STS_PI) {
|
||||||
memset(mbcp, 0, sizeof(struct mbox_params));
|
memset(mbcp, 0, sizeof(struct mbox_params));
|
||||||
|
@ -888,6 +979,8 @@ void ql_mpi_work(struct work_struct *work)
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* End polled mode for MPI */
|
||||||
|
ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
|
||||||
rtnl_unlock();
|
rtnl_unlock();
|
||||||
ql_enable_completion_interrupt(qdev, 0);
|
ql_enable_completion_interrupt(qdev, 0);
|
||||||
}
|
}
|
||||||
|
|
File diff suppressed because it is too large
Load diff
53
drivers/net/stmmac/Kconfig
Normal file
53
drivers/net/stmmac/Kconfig
Normal file
|
@ -0,0 +1,53 @@
|
||||||
|
config STMMAC_ETH
|
||||||
|
tristate "STMicroelectronics 10/100/1000 Ethernet driver"
|
||||||
|
select MII
|
||||||
|
select PHYLIB
|
||||||
|
depends on NETDEVICES && CPU_SUBTYPE_ST40
|
||||||
|
help
|
||||||
|
This is the driver for the ST MAC 10/100/1000 on-chip Ethernet
|
||||||
|
controllers. ST Ethernet IPs are built around a Synopsys IP Core.
|
||||||
|
|
||||||
|
if STMMAC_ETH
|
||||||
|
|
||||||
|
config STMMAC_DA
|
||||||
|
bool "STMMAC DMA arbitration scheme"
|
||||||
|
default n
|
||||||
|
help
|
||||||
|
Selecting this option, rx has priority over Tx (only for Giga
|
||||||
|
Ethernet device).
|
||||||
|
By default, the DMA arbitration scheme is based on Round-robin
|
||||||
|
(rx:tx priority is 1:1).
|
||||||
|
|
||||||
|
config STMMAC_DUAL_MAC
|
||||||
|
bool "STMMAC: dual mac support (EXPERIMENTAL)"
|
||||||
|
default n
|
||||||
|
depends on EXPERIMENTAL && STMMAC_ETH && !STMMAC_TIMER
|
||||||
|
help
|
||||||
|
Some ST SoCs (for example the stx7141 and stx7200c2) have two
|
||||||
|
Ethernet Controllers. This option turns on the second Ethernet
|
||||||
|
device on this kind of platforms.
|
||||||
|
|
||||||
|
config STMMAC_TIMER
|
||||||
|
bool "STMMAC Timer optimisation"
|
||||||
|
default n
|
||||||
|
help
|
||||||
|
Use an external timer for mitigating the number of network
|
||||||
|
interrupts.
|
||||||
|
|
||||||
|
choice
|
||||||
|
prompt "Select Timer device"
|
||||||
|
depends on STMMAC_TIMER
|
||||||
|
|
||||||
|
config STMMAC_TMU_TIMER
|
||||||
|
bool "TMU channel 2"
|
||||||
|
depends on CPU_SH4
|
||||||
|
help
|
||||||
|
|
||||||
|
config STMMAC_RTC_TIMER
|
||||||
|
bool "Real time clock"
|
||||||
|
depends on RTC_CLASS
|
||||||
|
help
|
||||||
|
|
||||||
|
endchoice
|
||||||
|
|
||||||
|
endif
|
4
drivers/net/stmmac/Makefile
Normal file
4
drivers/net/stmmac/Makefile
Normal file
|
@ -0,0 +1,4 @@
|
||||||
|
obj-$(CONFIG_STMMAC_ETH) += stmmac.o
|
||||||
|
stmmac-$(CONFIG_STMMAC_TIMER) += stmmac_timer.o
|
||||||
|
stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o \
|
||||||
|
mac100.o gmac.o $(stmmac-y)
|
330
drivers/net/stmmac/common.h
Normal file
330
drivers/net/stmmac/common.h
Normal file
|
@ -0,0 +1,330 @@
|
||||||
|
/*******************************************************************************
|
||||||
|
STMMAC Common Header File
|
||||||
|
|
||||||
|
Copyright (C) 2007-2009 STMicroelectronics Ltd
|
||||||
|
|
||||||
|
This program is free software; you can redistribute it and/or modify it
|
||||||
|
under the terms and conditions of the GNU General Public License,
|
||||||
|
version 2, as published by the Free Software Foundation.
|
||||||
|
|
||||||
|
This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License along with
|
||||||
|
this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||||
|
|
||||||
|
The full GNU General Public License is included in this distribution in
|
||||||
|
the file called "COPYING".
|
||||||
|
|
||||||
|
Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
#include "descs.h"
|
||||||
|
#include <linux/io.h>
|
||||||
|
|
||||||
|
/* *********************************************
|
||||||
|
DMA CRS Control and Status Register Mapping
|
||||||
|
* *********************************************/
|
||||||
|
#define DMA_BUS_MODE 0x00001000 /* Bus Mode */
|
||||||
|
#define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */
|
||||||
|
#define DMA_RCV_POLL_DEMAND 0x00001008 /* Received Poll Demand */
|
||||||
|
#define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */
|
||||||
|
#define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */
|
||||||
|
#define DMA_STATUS 0x00001014 /* Status Register */
|
||||||
|
#define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */
|
||||||
|
#define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */
|
||||||
|
#define DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */
|
||||||
|
#define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */
|
||||||
|
#define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */
|
||||||
|
|
||||||
|
/* ********************************
|
||||||
|
DMA Control register defines
|
||||||
|
* ********************************/
|
||||||
|
#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
|
||||||
|
#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
|
||||||
|
|
||||||
|
/* **************************************
|
||||||
|
DMA Interrupt Enable register defines
|
||||||
|
* **************************************/
|
||||||
|
/**** NORMAL INTERRUPT ****/
|
||||||
|
#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
|
||||||
|
#define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
|
||||||
|
#define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */
|
||||||
|
#define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
|
||||||
|
#define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
|
||||||
|
|
||||||
|
#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
|
||||||
|
DMA_INTR_ENA_TIE)
|
||||||
|
|
||||||
|
/**** ABNORMAL INTERRUPT ****/
|
||||||
|
#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
|
||||||
|
#define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
|
||||||
|
#define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
|
||||||
|
#define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
|
||||||
|
#define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
|
||||||
|
#define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
|
||||||
|
#define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */
|
||||||
|
#define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
|
||||||
|
#define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
|
||||||
|
#define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
|
||||||
|
|
||||||
|
#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
|
||||||
|
DMA_INTR_ENA_UNE)
|
||||||
|
|
||||||
|
/* DMA default interrupt mask */
|
||||||
|
#define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
|
||||||
|
|
||||||
|
/* ****************************
|
||||||
|
* DMA Status register defines
|
||||||
|
* ****************************/
|
||||||
|
#define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */
|
||||||
|
#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
|
||||||
|
#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int. */
|
||||||
|
#define DMA_STATUS_GMI 0x08000000
|
||||||
|
#define DMA_STATUS_GLI 0x04000000
|
||||||
|
#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
|
||||||
|
#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
|
||||||
|
#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
|
||||||
|
#define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
|
||||||
|
#define DMA_STATUS_TS_SHIFT 20
|
||||||
|
#define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
|
||||||
|
#define DMA_STATUS_RS_SHIFT 17
|
||||||
|
#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
|
||||||
|
#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
|
||||||
|
#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
|
||||||
|
#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
|
||||||
|
#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
|
||||||
|
#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
|
||||||
|
#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
|
||||||
|
#define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
|
||||||
|
#define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
|
||||||
|
#define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
|
||||||
|
#define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
|
||||||
|
#define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
|
||||||
|
#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
|
||||||
|
#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
|
||||||
|
#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
|
||||||
|
|
||||||
|
/* Other defines */
|
||||||
|
#define HASH_TABLE_SIZE 64
|
||||||
|
#define PAUSE_TIME 0x200
|
||||||
|
|
||||||
|
/* Flow Control defines */
|
||||||
|
#define FLOW_OFF 0
|
||||||
|
#define FLOW_RX 1
|
||||||
|
#define FLOW_TX 2
|
||||||
|
#define FLOW_AUTO (FLOW_TX | FLOW_RX)
|
||||||
|
|
||||||
|
/* DMA STORE-AND-FORWARD Operation Mode */
|
||||||
|
#define SF_DMA_MODE 1
|
||||||
|
|
||||||
|
#define HW_CSUM 1
|
||||||
|
#define NO_HW_CSUM 0
|
||||||
|
|
||||||
|
/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
|
||||||
|
#define BUF_SIZE_16KiB 16384
|
||||||
|
#define BUF_SIZE_8KiB 8192
|
||||||
|
#define BUF_SIZE_4KiB 4096
|
||||||
|
#define BUF_SIZE_2KiB 2048
|
||||||
|
|
||||||
|
/* Power Down and WOL */
|
||||||
|
#define PMT_NOT_SUPPORTED 0
|
||||||
|
#define PMT_SUPPORTED 1
|
||||||
|
|
||||||
|
/* Common MAC defines */
|
||||||
|
#define MAC_CTRL_REG 0x00000000 /* MAC Control */
|
||||||
|
#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
|
||||||
|
#define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
|
||||||
|
|
||||||
|
/* MAC Management Counters register */
|
||||||
|
#define MMC_CONTROL 0x00000100 /* MMC Control */
|
||||||
|
#define MMC_HIGH_INTR 0x00000104 /* MMC High Interrupt */
|
||||||
|
#define MMC_LOW_INTR 0x00000108 /* MMC Low Interrupt */
|
||||||
|
#define MMC_HIGH_INTR_MASK 0x0000010c /* MMC High Interrupt Mask */
|
||||||
|
#define MMC_LOW_INTR_MASK 0x00000110 /* MMC Low Interrupt Mask */
|
||||||
|
|
||||||
|
#define MMC_CONTROL_MAX_FRM_MASK 0x0003ff8 /* Maximum Frame Size */
|
||||||
|
#define MMC_CONTROL_MAX_FRM_SHIFT 3
|
||||||
|
#define MMC_CONTROL_MAX_FRAME 0x7FF
|
||||||
|
|
||||||
|
struct stmmac_extra_stats {
|
||||||
|
/* Transmit errors */
|
||||||
|
unsigned long tx_underflow ____cacheline_aligned;
|
||||||
|
unsigned long tx_carrier;
|
||||||
|
unsigned long tx_losscarrier;
|
||||||
|
unsigned long tx_heartbeat;
|
||||||
|
unsigned long tx_deferred;
|
||||||
|
unsigned long tx_vlan;
|
||||||
|
unsigned long tx_jabber;
|
||||||
|
unsigned long tx_frame_flushed;
|
||||||
|
unsigned long tx_payload_error;
|
||||||
|
unsigned long tx_ip_header_error;
|
||||||
|
/* Receive errors */
|
||||||
|
unsigned long rx_desc;
|
||||||
|
unsigned long rx_partial;
|
||||||
|
unsigned long rx_runt;
|
||||||
|
unsigned long rx_toolong;
|
||||||
|
unsigned long rx_collision;
|
||||||
|
unsigned long rx_crc;
|
||||||
|
unsigned long rx_lenght;
|
||||||
|
unsigned long rx_mii;
|
||||||
|
unsigned long rx_multicast;
|
||||||
|
unsigned long rx_gmac_overflow;
|
||||||
|
unsigned long rx_watchdog;
|
||||||
|
unsigned long da_rx_filter_fail;
|
||||||
|
unsigned long sa_rx_filter_fail;
|
||||||
|
unsigned long rx_missed_cntr;
|
||||||
|
unsigned long rx_overflow_cntr;
|
||||||
|
unsigned long rx_vlan;
|
||||||
|
/* Tx/Rx IRQ errors */
|
||||||
|
unsigned long tx_undeflow_irq;
|
||||||
|
unsigned long tx_process_stopped_irq;
|
||||||
|
unsigned long tx_jabber_irq;
|
||||||
|
unsigned long rx_overflow_irq;
|
||||||
|
unsigned long rx_buf_unav_irq;
|
||||||
|
unsigned long rx_process_stopped_irq;
|
||||||
|
unsigned long rx_watchdog_irq;
|
||||||
|
unsigned long tx_early_irq;
|
||||||
|
unsigned long fatal_bus_error_irq;
|
||||||
|
/* Extra info */
|
||||||
|
unsigned long threshold;
|
||||||
|
unsigned long tx_pkt_n;
|
||||||
|
unsigned long rx_pkt_n;
|
||||||
|
unsigned long poll_n;
|
||||||
|
unsigned long sched_timer_n;
|
||||||
|
unsigned long normal_irq_n;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* GMAC core can compute the checksums in HW. */
|
||||||
|
enum rx_frame_status {
|
||||||
|
good_frame = 0,
|
||||||
|
discard_frame = 1,
|
||||||
|
csum_none = 2,
|
||||||
|
};
|
||||||
|
|
||||||
|
static inline void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],
|
||||||
|
unsigned int high, unsigned int low)
|
||||||
|
{
|
||||||
|
unsigned long data;
|
||||||
|
|
||||||
|
data = (addr[5] << 8) | addr[4];
|
||||||
|
writel(data, ioaddr + high);
|
||||||
|
data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
|
||||||
|
writel(data, ioaddr + low);
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void stmmac_get_mac_addr(unsigned long ioaddr,
|
||||||
|
unsigned char *addr, unsigned int high,
|
||||||
|
unsigned int low)
|
||||||
|
{
|
||||||
|
unsigned int hi_addr, lo_addr;
|
||||||
|
|
||||||
|
/* Read the MAC address from the hardware */
|
||||||
|
hi_addr = readl(ioaddr + high);
|
||||||
|
lo_addr = readl(ioaddr + low);
|
||||||
|
|
||||||
|
/* Extract the MAC address from the high and low words */
|
||||||
|
addr[0] = lo_addr & 0xff;
|
||||||
|
addr[1] = (lo_addr >> 8) & 0xff;
|
||||||
|
addr[2] = (lo_addr >> 16) & 0xff;
|
||||||
|
addr[3] = (lo_addr >> 24) & 0xff;
|
||||||
|
addr[4] = hi_addr & 0xff;
|
||||||
|
addr[5] = (hi_addr >> 8) & 0xff;
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
struct stmmac_ops {
|
||||||
|
/* MAC core initialization */
|
||||||
|
void (*core_init) (unsigned long ioaddr) ____cacheline_aligned;
|
||||||
|
/* DMA core initialization */
|
||||||
|
int (*dma_init) (unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx);
|
||||||
|
/* Dump MAC registers */
|
||||||
|
void (*dump_mac_regs) (unsigned long ioaddr);
|
||||||
|
/* Dump DMA registers */
|
||||||
|
void (*dump_dma_regs) (unsigned long ioaddr);
|
||||||
|
/* Set tx/rx threshold in the csr6 register
|
||||||
|
* An invalid value enables the store-and-forward mode */
|
||||||
|
void (*dma_mode) (unsigned long ioaddr, int txmode, int rxmode);
|
||||||
|
/* To track extra statistic (if supported) */
|
||||||
|
void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
|
||||||
|
unsigned long ioaddr);
|
||||||
|
/* RX descriptor ring initialization */
|
||||||
|
void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size,
|
||||||
|
int disable_rx_ic);
|
||||||
|
/* TX descriptor ring initialization */
|
||||||
|
void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size);
|
||||||
|
|
||||||
|
/* Invoked by the xmit function to prepare the tx descriptor */
|
||||||
|
void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
|
||||||
|
int csum_flag);
|
||||||
|
/* Set/get the owner of the descriptor */
|
||||||
|
void (*set_tx_owner) (struct dma_desc *p);
|
||||||
|
int (*get_tx_owner) (struct dma_desc *p);
|
||||||
|
/* Invoked by the xmit function to close the tx descriptor */
|
||||||
|
void (*close_tx_desc) (struct dma_desc *p);
|
||||||
|
/* Clean the tx descriptor as soon as the tx irq is received */
|
||||||
|
void (*release_tx_desc) (struct dma_desc *p);
|
||||||
|
/* Clear interrupt on tx frame completion. When this bit is
|
||||||
|
* set an interrupt happens as soon as the frame is transmitted */
|
||||||
|
void (*clear_tx_ic) (struct dma_desc *p);
|
||||||
|
/* Last tx segment reports the transmit status */
|
||||||
|
int (*get_tx_ls) (struct dma_desc *p);
|
||||||
|
/* Return the transmit status looking at the TDES1 */
|
||||||
|
int (*tx_status) (void *data, struct stmmac_extra_stats *x,
|
||||||
|
struct dma_desc *p, unsigned long ioaddr);
|
||||||
|
/* Get the buffer size from the descriptor */
|
||||||
|
int (*get_tx_len) (struct dma_desc *p);
|
||||||
|
/* Handle extra events on specific interrupts hw dependent */
|
||||||
|
void (*host_irq_status) (unsigned long ioaddr);
|
||||||
|
int (*get_rx_owner) (struct dma_desc *p);
|
||||||
|
void (*set_rx_owner) (struct dma_desc *p);
|
||||||
|
/* Get the receive frame size */
|
||||||
|
int (*get_rx_frame_len) (struct dma_desc *p);
|
||||||
|
/* Return the reception status looking at the RDES1 */
|
||||||
|
int (*rx_status) (void *data, struct stmmac_extra_stats *x,
|
||||||
|
struct dma_desc *p);
|
||||||
|
/* Multicast filter setting */
|
||||||
|
void (*set_filter) (struct net_device *dev);
|
||||||
|
/* Flow control setting */
|
||||||
|
void (*flow_ctrl) (unsigned long ioaddr, unsigned int duplex,
|
||||||
|
unsigned int fc, unsigned int pause_time);
|
||||||
|
/* Set power management mode (e.g. magic frame) */
|
||||||
|
void (*pmt) (unsigned long ioaddr, unsigned long mode);
|
||||||
|
/* Set/Get Unicast MAC addresses */
|
||||||
|
void (*set_umac_addr) (unsigned long ioaddr, unsigned char *addr,
|
||||||
|
unsigned int reg_n);
|
||||||
|
void (*get_umac_addr) (unsigned long ioaddr, unsigned char *addr,
|
||||||
|
unsigned int reg_n);
|
||||||
|
};
|
||||||
|
|
||||||
|
struct mac_link {
|
||||||
|
int port;
|
||||||
|
int duplex;
|
||||||
|
int speed;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct mii_regs {
|
||||||
|
unsigned int addr; /* MII Address */
|
||||||
|
unsigned int data; /* MII Data */
|
||||||
|
};
|
||||||
|
|
||||||
|
struct hw_cap {
|
||||||
|
unsigned int version; /* Core Version register (GMAC) */
|
||||||
|
unsigned int pmt; /* Power-Down mode (GMAC) */
|
||||||
|
struct mac_link link;
|
||||||
|
struct mii_regs mii;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct mac_device_info {
|
||||||
|
struct hw_cap hw;
|
||||||
|
struct stmmac_ops *ops;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct mac_device_info *gmac_setup(unsigned long addr);
|
||||||
|
struct mac_device_info *mac100_setup(unsigned long addr);
|
163
drivers/net/stmmac/descs.h
Normal file
163
drivers/net/stmmac/descs.h
Normal file
|
@ -0,0 +1,163 @@
|
||||||
|
/*******************************************************************************
|
||||||
|
Header File to describe the DMA descriptors
|
||||||
|
Use enhanced descriptors in case of GMAC Cores.
|
||||||
|
|
||||||
|
This program is free software; you can redistribute it and/or modify it
|
||||||
|
under the terms and conditions of the GNU General Public License,
|
||||||
|
version 2, as published by the Free Software Foundation.
|
||||||
|
|
||||||
|
This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License along with
|
||||||
|
this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||||
|
|
||||||
|
The full GNU General Public License is included in this distribution in
|
||||||
|
the file called "COPYING".
|
||||||
|
|
||||||
|
Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
|
||||||
|
*******************************************************************************/
|
||||||
|
struct dma_desc {
|
||||||
|
/* Receive descriptor */
|
||||||
|
union {
|
||||||
|
struct {
|
||||||
|
/* RDES0 */
|
||||||
|
u32 reserved1:1;
|
||||||
|
u32 crc_error:1;
|
||||||
|
u32 dribbling:1;
|
||||||
|
u32 mii_error:1;
|
||||||
|
u32 receive_watchdog:1;
|
||||||
|
u32 frame_type:1;
|
||||||
|
u32 collision:1;
|
||||||
|
u32 frame_too_long:1;
|
||||||
|
u32 last_descriptor:1;
|
||||||
|
u32 first_descriptor:1;
|
||||||
|
u32 multicast_frame:1;
|
||||||
|
u32 run_frame:1;
|
||||||
|
u32 length_error:1;
|
||||||
|
u32 partial_frame_error:1;
|
||||||
|
u32 descriptor_error:1;
|
||||||
|
u32 error_summary:1;
|
||||||
|
u32 frame_length:14;
|
||||||
|
u32 filtering_fail:1;
|
||||||
|
u32 own:1;
|
||||||
|
/* RDES1 */
|
||||||
|
u32 buffer1_size:11;
|
||||||
|
u32 buffer2_size:11;
|
||||||
|
u32 reserved2:2;
|
||||||
|
u32 second_address_chained:1;
|
||||||
|
u32 end_ring:1;
|
||||||
|
u32 reserved3:5;
|
||||||
|
u32 disable_ic:1;
|
||||||
|
} rx;
|
||||||
|
struct {
|
||||||
|
/* RDES0 */
|
||||||
|
u32 payload_csum_error:1;
|
||||||
|
u32 crc_error:1;
|
||||||
|
u32 dribbling:1;
|
||||||
|
u32 error_gmii:1;
|
||||||
|
u32 receive_watchdog:1;
|
||||||
|
u32 frame_type:1;
|
||||||
|
u32 late_collision:1;
|
||||||
|
u32 ipc_csum_error:1;
|
||||||
|
u32 last_descriptor:1;
|
||||||
|
u32 first_descriptor:1;
|
||||||
|
u32 vlan_tag:1;
|
||||||
|
u32 overflow_error:1;
|
||||||
|
u32 length_error:1;
|
||||||
|
u32 sa_filter_fail:1;
|
||||||
|
u32 descriptor_error:1;
|
||||||
|
u32 error_summary:1;
|
||||||
|
u32 frame_length:14;
|
||||||
|
u32 da_filter_fail:1;
|
||||||
|
u32 own:1;
|
||||||
|
/* RDES1 */
|
||||||
|
u32 buffer1_size:13;
|
||||||
|
u32 reserved1:1;
|
||||||
|
u32 second_address_chained:1;
|
||||||
|
u32 end_ring:1;
|
||||||
|
u32 buffer2_size:13;
|
||||||
|
u32 reserved2:2;
|
||||||
|
u32 disable_ic:1;
|
||||||
|
} erx; /* -- enhanced -- */
|
||||||
|
|
||||||
|
/* Transmit descriptor */
|
||||||
|
struct {
|
||||||
|
/* TDES0 */
|
||||||
|
u32 deferred:1;
|
||||||
|
u32 underflow_error:1;
|
||||||
|
u32 excessive_deferral:1;
|
||||||
|
u32 collision_count:4;
|
||||||
|
u32 heartbeat_fail:1;
|
||||||
|
u32 excessive_collisions:1;
|
||||||
|
u32 late_collision:1;
|
||||||
|
u32 no_carrier:1;
|
||||||
|
u32 loss_carrier:1;
|
||||||
|
u32 reserved1:3;
|
||||||
|
u32 error_summary:1;
|
||||||
|
u32 reserved2:15;
|
||||||
|
u32 own:1;
|
||||||
|
/* TDES1 */
|
||||||
|
u32 buffer1_size:11;
|
||||||
|
u32 buffer2_size:11;
|
||||||
|
u32 reserved3:1;
|
||||||
|
u32 disable_padding:1;
|
||||||
|
u32 second_address_chained:1;
|
||||||
|
u32 end_ring:1;
|
||||||
|
u32 crc_disable:1;
|
||||||
|
u32 reserved4:2;
|
||||||
|
u32 first_segment:1;
|
||||||
|
u32 last_segment:1;
|
||||||
|
u32 interrupt:1;
|
||||||
|
} tx;
|
||||||
|
struct {
|
||||||
|
/* TDES0 */
|
||||||
|
u32 deferred:1;
|
||||||
|
u32 underflow_error:1;
|
||||||
|
u32 excessive_deferral:1;
|
||||||
|
u32 collision_count:4;
|
||||||
|
u32 vlan_frame:1;
|
||||||
|
u32 excessive_collisions:1;
|
||||||
|
u32 late_collision:1;
|
||||||
|
u32 no_carrier:1;
|
||||||
|
u32 loss_carrier:1;
|
||||||
|
u32 payload_error:1;
|
||||||
|
u32 frame_flushed:1;
|
||||||
|
u32 jabber_timeout:1;
|
||||||
|
u32 error_summary:1;
|
||||||
|
u32 ip_header_error:1;
|
||||||
|
u32 time_stamp_status:1;
|
||||||
|
u32 reserved1:2;
|
||||||
|
u32 second_address_chained:1;
|
||||||
|
u32 end_ring:1;
|
||||||
|
u32 checksum_insertion:2;
|
||||||
|
u32 reserved2:1;
|
||||||
|
u32 time_stamp_enable:1;
|
||||||
|
u32 disable_padding:1;
|
||||||
|
u32 crc_disable:1;
|
||||||
|
u32 first_segment:1;
|
||||||
|
u32 last_segment:1;
|
||||||
|
u32 interrupt:1;
|
||||||
|
u32 own:1;
|
||||||
|
/* TDES1 */
|
||||||
|
u32 buffer1_size:13;
|
||||||
|
u32 reserved3:3;
|
||||||
|
u32 buffer2_size:13;
|
||||||
|
u32 reserved4:3;
|
||||||
|
} etx; /* -- enhanced -- */
|
||||||
|
} des01;
|
||||||
|
unsigned int des2;
|
||||||
|
unsigned int des3;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Transmit checksum insertion control */
|
||||||
|
enum tdes_csum_insertion {
|
||||||
|
cic_disabled = 0, /* Checksum Insertion Control */
|
||||||
|
cic_only_ip = 1, /* Only IP header */
|
||||||
|
cic_no_pseudoheader = 2, /* IP header but pseudoheader
|
||||||
|
* is not calculated */
|
||||||
|
cic_full = 3, /* IP header and pseudoheader */
|
||||||
|
};
|
693
drivers/net/stmmac/gmac.c
Normal file
693
drivers/net/stmmac/gmac.c
Normal file
|
@ -0,0 +1,693 @@
|
||||||
|
/*******************************************************************************
|
||||||
|
This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
|
||||||
|
DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
|
||||||
|
developing this code.
|
||||||
|
|
||||||
|
Copyright (C) 2007-2009 STMicroelectronics Ltd
|
||||||
|
|
||||||
|
This program is free software; you can redistribute it and/or modify it
|
||||||
|
under the terms and conditions of the GNU General Public License,
|
||||||
|
version 2, as published by the Free Software Foundation.
|
||||||
|
|
||||||
|
This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License along with
|
||||||
|
this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||||
|
|
||||||
|
The full GNU General Public License is included in this distribution in
|
||||||
|
the file called "COPYING".
|
||||||
|
|
||||||
|
Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
#include <linux/netdevice.h>
|
||||||
|
#include <linux/crc32.h>
|
||||||
|
#include <linux/mii.h>
|
||||||
|
#include <linux/phy.h>
|
||||||
|
|
||||||
|
#include "stmmac.h"
|
||||||
|
#include "gmac.h"
|
||||||
|
|
||||||
|
#undef GMAC_DEBUG
|
||||||
|
/*#define GMAC_DEBUG*/
|
||||||
|
#undef FRAME_FILTER_DEBUG
|
||||||
|
/*#define FRAME_FILTER_DEBUG*/
|
||||||
|
#ifdef GMAC_DEBUG
|
||||||
|
#define DBG(fmt, args...) printk(fmt, ## args)
|
||||||
|
#else
|
||||||
|
#define DBG(fmt, args...) do { } while (0)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static void gmac_dump_regs(unsigned long ioaddr)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
pr_info("\t----------------------------------------------\n"
|
||||||
|
"\t GMAC registers (base addr = 0x%8x)\n"
|
||||||
|
"\t----------------------------------------------\n",
|
||||||
|
(unsigned int)ioaddr);
|
||||||
|
|
||||||
|
for (i = 0; i < 55; i++) {
|
||||||
|
int offset = i * 4;
|
||||||
|
pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
|
||||||
|
offset, readl(ioaddr + offset));
|
||||||
|
}
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int gmac_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx)
|
||||||
|
{
|
||||||
|
u32 value = readl(ioaddr + DMA_BUS_MODE);
|
||||||
|
/* DMA SW reset */
|
||||||
|
value |= DMA_BUS_MODE_SFT_RESET;
|
||||||
|
writel(value, ioaddr + DMA_BUS_MODE);
|
||||||
|
do {} while ((readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET));
|
||||||
|
|
||||||
|
value = /* DMA_BUS_MODE_FB | */ DMA_BUS_MODE_4PBL |
|
||||||
|
((pbl << DMA_BUS_MODE_PBL_SHIFT) |
|
||||||
|
(pbl << DMA_BUS_MODE_RPBL_SHIFT));
|
||||||
|
|
||||||
|
#ifdef CONFIG_STMMAC_DA
|
||||||
|
value |= DMA_BUS_MODE_DA; /* Rx has priority over tx */
|
||||||
|
#endif
|
||||||
|
writel(value, ioaddr + DMA_BUS_MODE);
|
||||||
|
|
||||||
|
/* Mask interrupts by writing to CSR7 */
|
||||||
|
writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
|
||||||
|
|
||||||
|
/* The base address of the RX/TX descriptor lists must be written into
|
||||||
|
* DMA CSR3 and CSR4, respectively. */
|
||||||
|
writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
|
||||||
|
writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Transmit FIFO flush operation */
|
||||||
|
static void gmac_flush_tx_fifo(unsigned long ioaddr)
|
||||||
|
{
|
||||||
|
u32 csr6 = readl(ioaddr + DMA_CONTROL);
|
||||||
|
writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
|
||||||
|
|
||||||
|
do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gmac_dma_operation_mode(unsigned long ioaddr, int txmode,
|
||||||
|
int rxmode)
|
||||||
|
{
|
||||||
|
u32 csr6 = readl(ioaddr + DMA_CONTROL);
|
||||||
|
|
||||||
|
if (txmode == SF_DMA_MODE) {
|
||||||
|
DBG(KERN_DEBUG "GMAC: enabling TX store and forward mode\n");
|
||||||
|
/* Transmit COE type 2 cannot be done in cut-through mode. */
|
||||||
|
csr6 |= DMA_CONTROL_TSF;
|
||||||
|
/* Operating on second frame increase the performance
|
||||||
|
* especially when transmit store-and-forward is used.*/
|
||||||
|
csr6 |= DMA_CONTROL_OSF;
|
||||||
|
} else {
|
||||||
|
DBG(KERN_DEBUG "GMAC: disabling TX store and forward mode"
|
||||||
|
" (threshold = %d)\n", txmode);
|
||||||
|
csr6 &= ~DMA_CONTROL_TSF;
|
||||||
|
csr6 &= DMA_CONTROL_TC_TX_MASK;
|
||||||
|
/* Set the transmit threashold */
|
||||||
|
if (txmode <= 32)
|
||||||
|
csr6 |= DMA_CONTROL_TTC_32;
|
||||||
|
else if (txmode <= 64)
|
||||||
|
csr6 |= DMA_CONTROL_TTC_64;
|
||||||
|
else if (txmode <= 128)
|
||||||
|
csr6 |= DMA_CONTROL_TTC_128;
|
||||||
|
else if (txmode <= 192)
|
||||||
|
csr6 |= DMA_CONTROL_TTC_192;
|
||||||
|
else
|
||||||
|
csr6 |= DMA_CONTROL_TTC_256;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (rxmode == SF_DMA_MODE) {
|
||||||
|
DBG(KERN_DEBUG "GMAC: enabling RX store and forward mode\n");
|
||||||
|
csr6 |= DMA_CONTROL_RSF;
|
||||||
|
} else {
|
||||||
|
DBG(KERN_DEBUG "GMAC: disabling RX store and forward mode"
|
||||||
|
" (threshold = %d)\n", rxmode);
|
||||||
|
csr6 &= ~DMA_CONTROL_RSF;
|
||||||
|
csr6 &= DMA_CONTROL_TC_RX_MASK;
|
||||||
|
if (rxmode <= 32)
|
||||||
|
csr6 |= DMA_CONTROL_RTC_32;
|
||||||
|
else if (rxmode <= 64)
|
||||||
|
csr6 |= DMA_CONTROL_RTC_64;
|
||||||
|
else if (rxmode <= 96)
|
||||||
|
csr6 |= DMA_CONTROL_RTC_96;
|
||||||
|
else
|
||||||
|
csr6 |= DMA_CONTROL_RTC_128;
|
||||||
|
}
|
||||||
|
|
||||||
|
writel(csr6, ioaddr + DMA_CONTROL);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Not yet implemented --- no RMON module */
|
||||||
|
static void gmac_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x,
|
||||||
|
unsigned long ioaddr)
|
||||||
|
{
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gmac_dump_dma_regs(unsigned long ioaddr)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
pr_info(" DMA registers\n");
|
||||||
|
for (i = 0; i < 22; i++) {
|
||||||
|
if ((i < 9) || (i > 17)) {
|
||||||
|
int offset = i * 4;
|
||||||
|
pr_err("\t Reg No. %d (offset 0x%x): 0x%08x\n", i,
|
||||||
|
(DMA_BUS_MODE + offset),
|
||||||
|
readl(ioaddr + DMA_BUS_MODE + offset));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int gmac_get_tx_frame_status(void *data, struct stmmac_extra_stats *x,
|
||||||
|
struct dma_desc *p, unsigned long ioaddr)
|
||||||
|
{
|
||||||
|
int ret = 0;
|
||||||
|
struct net_device_stats *stats = (struct net_device_stats *)data;
|
||||||
|
|
||||||
|
if (unlikely(p->des01.etx.error_summary)) {
|
||||||
|
DBG(KERN_ERR "GMAC TX error... 0x%08x\n", p->des01.etx);
|
||||||
|
if (unlikely(p->des01.etx.jabber_timeout)) {
|
||||||
|
DBG(KERN_ERR "\tjabber_timeout error\n");
|
||||||
|
x->tx_jabber++;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (unlikely(p->des01.etx.frame_flushed)) {
|
||||||
|
DBG(KERN_ERR "\tframe_flushed error\n");
|
||||||
|
x->tx_frame_flushed++;
|
||||||
|
gmac_flush_tx_fifo(ioaddr);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (unlikely(p->des01.etx.loss_carrier)) {
|
||||||
|
DBG(KERN_ERR "\tloss_carrier error\n");
|
||||||
|
x->tx_losscarrier++;
|
||||||
|
stats->tx_carrier_errors++;
|
||||||
|
}
|
||||||
|
if (unlikely(p->des01.etx.no_carrier)) {
|
||||||
|
DBG(KERN_ERR "\tno_carrier error\n");
|
||||||
|
x->tx_carrier++;
|
||||||
|
stats->tx_carrier_errors++;
|
||||||
|
}
|
||||||
|
if (unlikely(p->des01.etx.late_collision)) {
|
||||||
|
DBG(KERN_ERR "\tlate_collision error\n");
|
||||||
|
stats->collisions += p->des01.etx.collision_count;
|
||||||
|
}
|
||||||
|
if (unlikely(p->des01.etx.excessive_collisions)) {
|
||||||
|
DBG(KERN_ERR "\texcessive_collisions\n");
|
||||||
|
stats->collisions += p->des01.etx.collision_count;
|
||||||
|
}
|
||||||
|
if (unlikely(p->des01.etx.excessive_deferral)) {
|
||||||
|
DBG(KERN_INFO "\texcessive tx_deferral\n");
|
||||||
|
x->tx_deferred++;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (unlikely(p->des01.etx.underflow_error)) {
|
||||||
|
DBG(KERN_ERR "\tunderflow error\n");
|
||||||
|
gmac_flush_tx_fifo(ioaddr);
|
||||||
|
x->tx_underflow++;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (unlikely(p->des01.etx.ip_header_error)) {
|
||||||
|
DBG(KERN_ERR "\tTX IP header csum error\n");
|
||||||
|
x->tx_ip_header_error++;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (unlikely(p->des01.etx.payload_error)) {
|
||||||
|
DBG(KERN_ERR "\tAddr/Payload csum error\n");
|
||||||
|
x->tx_payload_error++;
|
||||||
|
gmac_flush_tx_fifo(ioaddr);
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (unlikely(p->des01.etx.deferred)) {
|
||||||
|
DBG(KERN_INFO "GMAC TX status: tx deferred\n");
|
||||||
|
x->tx_deferred++;
|
||||||
|
}
|
||||||
|
#ifdef STMMAC_VLAN_TAG_USED
|
||||||
|
if (p->des01.etx.vlan_frame) {
|
||||||
|
DBG(KERN_INFO "GMAC TX status: VLAN frame\n");
|
||||||
|
x->tx_vlan++;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int gmac_get_tx_len(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
return p->des01.etx.buffer1_size;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int gmac_coe_rdes0(int ipc_err, int type, int payload_err)
|
||||||
|
{
|
||||||
|
int ret = good_frame;
|
||||||
|
u32 status = (type << 2 | ipc_err << 1 | payload_err) & 0x7;
|
||||||
|
|
||||||
|
/* bits 5 7 0 | Frame status
|
||||||
|
* ----------------------------------------------------------
|
||||||
|
* 0 0 0 | IEEE 802.3 Type frame (lenght < 1536 octects)
|
||||||
|
* 1 0 0 | IPv4/6 No CSUM errorS.
|
||||||
|
* 1 0 1 | IPv4/6 CSUM PAYLOAD error
|
||||||
|
* 1 1 0 | IPv4/6 CSUM IP HR error
|
||||||
|
* 1 1 1 | IPv4/6 IP PAYLOAD AND HEADER errorS
|
||||||
|
* 0 0 1 | IPv4/6 unsupported IP PAYLOAD
|
||||||
|
* 0 1 1 | COE bypassed.. no IPv4/6 frame
|
||||||
|
* 0 1 0 | Reserved.
|
||||||
|
*/
|
||||||
|
if (status == 0x0) {
|
||||||
|
DBG(KERN_INFO "RX Des0 status: IEEE 802.3 Type frame.\n");
|
||||||
|
ret = good_frame;
|
||||||
|
} else if (status == 0x4) {
|
||||||
|
DBG(KERN_INFO "RX Des0 status: IPv4/6 No CSUM errorS.\n");
|
||||||
|
ret = good_frame;
|
||||||
|
} else if (status == 0x5) {
|
||||||
|
DBG(KERN_ERR "RX Des0 status: IPv4/6 Payload Error.\n");
|
||||||
|
ret = csum_none;
|
||||||
|
} else if (status == 0x6) {
|
||||||
|
DBG(KERN_ERR "RX Des0 status: IPv4/6 Header Error.\n");
|
||||||
|
ret = csum_none;
|
||||||
|
} else if (status == 0x7) {
|
||||||
|
DBG(KERN_ERR
|
||||||
|
"RX Des0 status: IPv4/6 Header and Payload Error.\n");
|
||||||
|
ret = csum_none;
|
||||||
|
} else if (status == 0x1) {
|
||||||
|
DBG(KERN_ERR
|
||||||
|
"RX Des0 status: IPv4/6 unsupported IP PAYLOAD.\n");
|
||||||
|
ret = discard_frame;
|
||||||
|
} else if (status == 0x3) {
|
||||||
|
DBG(KERN_ERR "RX Des0 status: No IPv4, IPv6 frame.\n");
|
||||||
|
ret = discard_frame;
|
||||||
|
}
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int gmac_get_rx_frame_status(void *data, struct stmmac_extra_stats *x,
|
||||||
|
struct dma_desc *p)
|
||||||
|
{
|
||||||
|
int ret = good_frame;
|
||||||
|
struct net_device_stats *stats = (struct net_device_stats *)data;
|
||||||
|
|
||||||
|
if (unlikely(p->des01.erx.error_summary)) {
|
||||||
|
DBG(KERN_ERR "GMAC RX Error Summary... 0x%08x\n", p->des01.erx);
|
||||||
|
if (unlikely(p->des01.erx.descriptor_error)) {
|
||||||
|
DBG(KERN_ERR "\tdescriptor error\n");
|
||||||
|
x->rx_desc++;
|
||||||
|
stats->rx_length_errors++;
|
||||||
|
}
|
||||||
|
if (unlikely(p->des01.erx.overflow_error)) {
|
||||||
|
DBG(KERN_ERR "\toverflow error\n");
|
||||||
|
x->rx_gmac_overflow++;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (unlikely(p->des01.erx.ipc_csum_error))
|
||||||
|
DBG(KERN_ERR "\tIPC Csum Error/Giant frame\n");
|
||||||
|
|
||||||
|
if (unlikely(p->des01.erx.late_collision)) {
|
||||||
|
DBG(KERN_ERR "\tlate_collision error\n");
|
||||||
|
stats->collisions++;
|
||||||
|
stats->collisions++;
|
||||||
|
}
|
||||||
|
if (unlikely(p->des01.erx.receive_watchdog)) {
|
||||||
|
DBG(KERN_ERR "\treceive_watchdog error\n");
|
||||||
|
x->rx_watchdog++;
|
||||||
|
}
|
||||||
|
if (unlikely(p->des01.erx.error_gmii)) {
|
||||||
|
DBG(KERN_ERR "\tReceive Error\n");
|
||||||
|
x->rx_mii++;
|
||||||
|
}
|
||||||
|
if (unlikely(p->des01.erx.crc_error)) {
|
||||||
|
DBG(KERN_ERR "\tCRC error\n");
|
||||||
|
x->rx_crc++;
|
||||||
|
stats->rx_crc_errors++;
|
||||||
|
}
|
||||||
|
ret = discard_frame;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* After a payload csum error, the ES bit is set.
|
||||||
|
* It doesn't match with the information reported into the databook.
|
||||||
|
* At any rate, we need to understand if the CSUM hw computation is ok
|
||||||
|
* and report this info to the upper layers. */
|
||||||
|
ret = gmac_coe_rdes0(p->des01.erx.ipc_csum_error,
|
||||||
|
p->des01.erx.frame_type, p->des01.erx.payload_csum_error);
|
||||||
|
|
||||||
|
if (unlikely(p->des01.erx.dribbling)) {
|
||||||
|
DBG(KERN_ERR "GMAC RX: dribbling error\n");
|
||||||
|
ret = discard_frame;
|
||||||
|
}
|
||||||
|
if (unlikely(p->des01.erx.sa_filter_fail)) {
|
||||||
|
DBG(KERN_ERR "GMAC RX : Source Address filter fail\n");
|
||||||
|
x->sa_rx_filter_fail++;
|
||||||
|
ret = discard_frame;
|
||||||
|
}
|
||||||
|
if (unlikely(p->des01.erx.da_filter_fail)) {
|
||||||
|
DBG(KERN_ERR "GMAC RX : Destination Address filter fail\n");
|
||||||
|
x->da_rx_filter_fail++;
|
||||||
|
ret = discard_frame;
|
||||||
|
}
|
||||||
|
if (unlikely(p->des01.erx.length_error)) {
|
||||||
|
DBG(KERN_ERR "GMAC RX: length_error error\n");
|
||||||
|
x->rx_lenght++;
|
||||||
|
ret = discard_frame;
|
||||||
|
}
|
||||||
|
#ifdef STMMAC_VLAN_TAG_USED
|
||||||
|
if (p->des01.erx.vlan_tag) {
|
||||||
|
DBG(KERN_INFO "GMAC RX: VLAN frame tagged\n");
|
||||||
|
x->rx_vlan++;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gmac_irq_status(unsigned long ioaddr)
|
||||||
|
{
|
||||||
|
u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
|
||||||
|
|
||||||
|
/* Not used events (e.g. MMC interrupts) are not handled. */
|
||||||
|
if ((intr_status & mmc_tx_irq))
|
||||||
|
DBG(KERN_DEBUG "GMAC: MMC tx interrupt: 0x%08x\n",
|
||||||
|
readl(ioaddr + GMAC_MMC_TX_INTR));
|
||||||
|
if (unlikely(intr_status & mmc_rx_irq))
|
||||||
|
DBG(KERN_DEBUG "GMAC: MMC rx interrupt: 0x%08x\n",
|
||||||
|
readl(ioaddr + GMAC_MMC_RX_INTR));
|
||||||
|
if (unlikely(intr_status & mmc_rx_csum_offload_irq))
|
||||||
|
DBG(KERN_DEBUG "GMAC: MMC rx csum offload: 0x%08x\n",
|
||||||
|
readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD));
|
||||||
|
if (unlikely(intr_status & pmt_irq)) {
|
||||||
|
DBG(KERN_DEBUG "GMAC: received Magic frame\n");
|
||||||
|
/* clear the PMT bits 5 and 6 by reading the PMT
|
||||||
|
* status register. */
|
||||||
|
readl(ioaddr + GMAC_PMT);
|
||||||
|
}
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gmac_core_init(unsigned long ioaddr)
|
||||||
|
{
|
||||||
|
u32 value = readl(ioaddr + GMAC_CONTROL);
|
||||||
|
value |= GMAC_CORE_INIT;
|
||||||
|
writel(value, ioaddr + GMAC_CONTROL);
|
||||||
|
|
||||||
|
/* STBus Bridge Configuration */
|
||||||
|
/*writel(0xc5608, ioaddr + 0x00007000);*/
|
||||||
|
|
||||||
|
/* Freeze MMC counters */
|
||||||
|
writel(0x8, ioaddr + GMAC_MMC_CTRL);
|
||||||
|
/* Mask GMAC interrupts */
|
||||||
|
writel(0x207, ioaddr + GMAC_INT_MASK);
|
||||||
|
|
||||||
|
#ifdef STMMAC_VLAN_TAG_USED
|
||||||
|
/* Tag detection without filtering */
|
||||||
|
writel(0x0, ioaddr + GMAC_VLAN_TAG);
|
||||||
|
#endif
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gmac_set_umac_addr(unsigned long ioaddr, unsigned char *addr,
|
||||||
|
unsigned int reg_n)
|
||||||
|
{
|
||||||
|
stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
|
||||||
|
GMAC_ADDR_LOW(reg_n));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gmac_get_umac_addr(unsigned long ioaddr, unsigned char *addr,
|
||||||
|
unsigned int reg_n)
|
||||||
|
{
|
||||||
|
stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
|
||||||
|
GMAC_ADDR_LOW(reg_n));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gmac_set_filter(struct net_device *dev)
|
||||||
|
{
|
||||||
|
unsigned long ioaddr = dev->base_addr;
|
||||||
|
unsigned int value = 0;
|
||||||
|
|
||||||
|
DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n",
|
||||||
|
__func__, dev->mc_count, dev->uc_count);
|
||||||
|
|
||||||
|
if (dev->flags & IFF_PROMISC)
|
||||||
|
value = GMAC_FRAME_FILTER_PR;
|
||||||
|
else if ((dev->mc_count > HASH_TABLE_SIZE)
|
||||||
|
|| (dev->flags & IFF_ALLMULTI)) {
|
||||||
|
value = GMAC_FRAME_FILTER_PM; /* pass all multi */
|
||||||
|
writel(0xffffffff, ioaddr + GMAC_HASH_HIGH);
|
||||||
|
writel(0xffffffff, ioaddr + GMAC_HASH_LOW);
|
||||||
|
} else if (dev->mc_count > 0) {
|
||||||
|
int i;
|
||||||
|
u32 mc_filter[2];
|
||||||
|
struct dev_mc_list *mclist;
|
||||||
|
|
||||||
|
/* Hash filter for multicast */
|
||||||
|
value = GMAC_FRAME_FILTER_HMC;
|
||||||
|
|
||||||
|
memset(mc_filter, 0, sizeof(mc_filter));
|
||||||
|
for (i = 0, mclist = dev->mc_list;
|
||||||
|
mclist && i < dev->mc_count; i++, mclist = mclist->next) {
|
||||||
|
/* The upper 6 bits of the calculated CRC are used to
|
||||||
|
index the contens of the hash table */
|
||||||
|
int bit_nr =
|
||||||
|
bitrev32(~crc32_le(~0, mclist->dmi_addr, 6)) >> 26;
|
||||||
|
/* The most significant bit determines the register to
|
||||||
|
* use (H/L) while the other 5 bits determine the bit
|
||||||
|
* within the register. */
|
||||||
|
mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
|
||||||
|
}
|
||||||
|
writel(mc_filter[0], ioaddr + GMAC_HASH_LOW);
|
||||||
|
writel(mc_filter[1], ioaddr + GMAC_HASH_HIGH);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Handle multiple unicast addresses (perfect filtering)*/
|
||||||
|
if (dev->uc_count > GMAC_MAX_UNICAST_ADDRESSES)
|
||||||
|
/* Switch to promiscuous mode is more than 16 addrs
|
||||||
|
are required */
|
||||||
|
value |= GMAC_FRAME_FILTER_PR;
|
||||||
|
else {
|
||||||
|
int i;
|
||||||
|
struct dev_addr_list *uc_ptr = dev->uc_list;
|
||||||
|
|
||||||
|
for (i = 0; i < dev->uc_count; i++) {
|
||||||
|
gmac_set_umac_addr(ioaddr, uc_ptr->da_addr,
|
||||||
|
i + 1);
|
||||||
|
|
||||||
|
DBG(KERN_INFO "\t%d "
|
||||||
|
"- Unicast addr %02x:%02x:%02x:%02x:%02x:"
|
||||||
|
"%02x\n", i + 1,
|
||||||
|
uc_ptr->da_addr[0], uc_ptr->da_addr[1],
|
||||||
|
uc_ptr->da_addr[2], uc_ptr->da_addr[3],
|
||||||
|
uc_ptr->da_addr[4], uc_ptr->da_addr[5]);
|
||||||
|
uc_ptr = uc_ptr->next;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef FRAME_FILTER_DEBUG
|
||||||
|
/* Enable Receive all mode (to debug filtering_fail errors) */
|
||||||
|
value |= GMAC_FRAME_FILTER_RA;
|
||||||
|
#endif
|
||||||
|
writel(value, ioaddr + GMAC_FRAME_FILTER);
|
||||||
|
|
||||||
|
DBG(KERN_INFO "\tFrame Filter reg: 0x%08x\n\tHash regs: "
|
||||||
|
"HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER),
|
||||||
|
readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gmac_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
|
||||||
|
unsigned int fc, unsigned int pause_time)
|
||||||
|
{
|
||||||
|
unsigned int flow = 0;
|
||||||
|
|
||||||
|
DBG(KERN_DEBUG "GMAC Flow-Control:\n");
|
||||||
|
if (fc & FLOW_RX) {
|
||||||
|
DBG(KERN_DEBUG "\tReceive Flow-Control ON\n");
|
||||||
|
flow |= GMAC_FLOW_CTRL_RFE;
|
||||||
|
}
|
||||||
|
if (fc & FLOW_TX) {
|
||||||
|
DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n");
|
||||||
|
flow |= GMAC_FLOW_CTRL_TFE;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (duplex) {
|
||||||
|
DBG(KERN_DEBUG "\tduplex mode: pause time: %d\n", pause_time);
|
||||||
|
flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
|
||||||
|
}
|
||||||
|
|
||||||
|
writel(flow, ioaddr + GMAC_FLOW_CTRL);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gmac_pmt(unsigned long ioaddr, unsigned long mode)
|
||||||
|
{
|
||||||
|
unsigned int pmt = 0;
|
||||||
|
|
||||||
|
if (mode == WAKE_MAGIC) {
|
||||||
|
DBG(KERN_DEBUG "GMAC: WOL Magic frame\n");
|
||||||
|
pmt |= power_down | magic_pkt_en;
|
||||||
|
} else if (mode == WAKE_UCAST) {
|
||||||
|
DBG(KERN_DEBUG "GMAC: WOL on global unicast\n");
|
||||||
|
pmt |= global_unicast;
|
||||||
|
}
|
||||||
|
|
||||||
|
writel(pmt, ioaddr + GMAC_PMT);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gmac_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
|
||||||
|
int disable_rx_ic)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
for (i = 0; i < ring_size; i++) {
|
||||||
|
p->des01.erx.own = 1;
|
||||||
|
p->des01.erx.buffer1_size = BUF_SIZE_8KiB - 1;
|
||||||
|
/* To support jumbo frames */
|
||||||
|
p->des01.erx.buffer2_size = BUF_SIZE_8KiB - 1;
|
||||||
|
if (i == ring_size - 1)
|
||||||
|
p->des01.erx.end_ring = 1;
|
||||||
|
if (disable_rx_ic)
|
||||||
|
p->des01.erx.disable_ic = 1;
|
||||||
|
p++;
|
||||||
|
}
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gmac_init_tx_desc(struct dma_desc *p, unsigned int ring_size)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < ring_size; i++) {
|
||||||
|
p->des01.etx.own = 0;
|
||||||
|
if (i == ring_size - 1)
|
||||||
|
p->des01.etx.end_ring = 1;
|
||||||
|
p++;
|
||||||
|
}
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int gmac_get_tx_owner(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
return p->des01.etx.own;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int gmac_get_rx_owner(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
return p->des01.erx.own;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gmac_set_tx_owner(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
p->des01.etx.own = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gmac_set_rx_owner(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
p->des01.erx.own = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int gmac_get_tx_ls(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
return p->des01.etx.last_segment;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gmac_release_tx_desc(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
int ter = p->des01.etx.end_ring;
|
||||||
|
|
||||||
|
memset(p, 0, sizeof(struct dma_desc));
|
||||||
|
p->des01.etx.end_ring = ter;
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gmac_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
|
||||||
|
int csum_flag)
|
||||||
|
{
|
||||||
|
p->des01.etx.first_segment = is_fs;
|
||||||
|
if (unlikely(len > BUF_SIZE_4KiB)) {
|
||||||
|
p->des01.etx.buffer1_size = BUF_SIZE_4KiB;
|
||||||
|
p->des01.etx.buffer2_size = len - BUF_SIZE_4KiB;
|
||||||
|
} else {
|
||||||
|
p->des01.etx.buffer1_size = len;
|
||||||
|
}
|
||||||
|
if (likely(csum_flag))
|
||||||
|
p->des01.etx.checksum_insertion = cic_full;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gmac_clear_tx_ic(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
p->des01.etx.interrupt = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gmac_close_tx_desc(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
p->des01.etx.last_segment = 1;
|
||||||
|
p->des01.etx.interrupt = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int gmac_get_rx_frame_len(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
return p->des01.erx.frame_length;
|
||||||
|
}
|
||||||
|
|
||||||
|
struct stmmac_ops gmac_driver = {
|
||||||
|
.core_init = gmac_core_init,
|
||||||
|
.dump_mac_regs = gmac_dump_regs,
|
||||||
|
.dma_init = gmac_dma_init,
|
||||||
|
.dump_dma_regs = gmac_dump_dma_regs,
|
||||||
|
.dma_mode = gmac_dma_operation_mode,
|
||||||
|
.dma_diagnostic_fr = gmac_dma_diagnostic_fr,
|
||||||
|
.tx_status = gmac_get_tx_frame_status,
|
||||||
|
.rx_status = gmac_get_rx_frame_status,
|
||||||
|
.get_tx_len = gmac_get_tx_len,
|
||||||
|
.set_filter = gmac_set_filter,
|
||||||
|
.flow_ctrl = gmac_flow_ctrl,
|
||||||
|
.pmt = gmac_pmt,
|
||||||
|
.init_rx_desc = gmac_init_rx_desc,
|
||||||
|
.init_tx_desc = gmac_init_tx_desc,
|
||||||
|
.get_tx_owner = gmac_get_tx_owner,
|
||||||
|
.get_rx_owner = gmac_get_rx_owner,
|
||||||
|
.release_tx_desc = gmac_release_tx_desc,
|
||||||
|
.prepare_tx_desc = gmac_prepare_tx_desc,
|
||||||
|
.clear_tx_ic = gmac_clear_tx_ic,
|
||||||
|
.close_tx_desc = gmac_close_tx_desc,
|
||||||
|
.get_tx_ls = gmac_get_tx_ls,
|
||||||
|
.set_tx_owner = gmac_set_tx_owner,
|
||||||
|
.set_rx_owner = gmac_set_rx_owner,
|
||||||
|
.get_rx_frame_len = gmac_get_rx_frame_len,
|
||||||
|
.host_irq_status = gmac_irq_status,
|
||||||
|
.set_umac_addr = gmac_set_umac_addr,
|
||||||
|
.get_umac_addr = gmac_get_umac_addr,
|
||||||
|
};
|
||||||
|
|
||||||
|
struct mac_device_info *gmac_setup(unsigned long ioaddr)
|
||||||
|
{
|
||||||
|
struct mac_device_info *mac;
|
||||||
|
u32 uid = readl(ioaddr + GMAC_VERSION);
|
||||||
|
|
||||||
|
pr_info("\tGMAC - user ID: 0x%x, Synopsys ID: 0x%x\n",
|
||||||
|
((uid & 0x0000ff00) >> 8), (uid & 0x000000ff));
|
||||||
|
|
||||||
|
mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
|
||||||
|
|
||||||
|
mac->ops = &gmac_driver;
|
||||||
|
mac->hw.pmt = PMT_SUPPORTED;
|
||||||
|
mac->hw.link.port = GMAC_CONTROL_PS;
|
||||||
|
mac->hw.link.duplex = GMAC_CONTROL_DM;
|
||||||
|
mac->hw.link.speed = GMAC_CONTROL_FES;
|
||||||
|
mac->hw.mii.addr = GMAC_MII_ADDR;
|
||||||
|
mac->hw.mii.data = GMAC_MII_DATA;
|
||||||
|
|
||||||
|
return mac;
|
||||||
|
}
|
204
drivers/net/stmmac/gmac.h
Normal file
204
drivers/net/stmmac/gmac.h
Normal file
|
@ -0,0 +1,204 @@
|
||||||
|
/*******************************************************************************
|
||||||
|
Copyright (C) 2007-2009 STMicroelectronics Ltd
|
||||||
|
|
||||||
|
This program is free software; you can redistribute it and/or modify it
|
||||||
|
under the terms and conditions of the GNU General Public License,
|
||||||
|
version 2, as published by the Free Software Foundation.
|
||||||
|
|
||||||
|
This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License along with
|
||||||
|
this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||||
|
|
||||||
|
The full GNU General Public License is included in this distribution in
|
||||||
|
the file called "COPYING".
|
||||||
|
|
||||||
|
Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
#define GMAC_CONTROL 0x00000000 /* Configuration */
|
||||||
|
#define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */
|
||||||
|
#define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */
|
||||||
|
#define GMAC_HASH_LOW 0x0000000c /* Multicast Hash Table Low */
|
||||||
|
#define GMAC_MII_ADDR 0x00000010 /* MII Address */
|
||||||
|
#define GMAC_MII_DATA 0x00000014 /* MII Data */
|
||||||
|
#define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */
|
||||||
|
#define GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */
|
||||||
|
#define GMAC_VERSION 0x00000020 /* GMAC CORE Version */
|
||||||
|
#define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
|
||||||
|
|
||||||
|
#define GMAC_INT_STATUS 0x00000038 /* interrupt status register */
|
||||||
|
enum gmac_irq_status {
|
||||||
|
time_stamp_irq = 0x0200,
|
||||||
|
mmc_rx_csum_offload_irq = 0x0080,
|
||||||
|
mmc_tx_irq = 0x0040,
|
||||||
|
mmc_rx_irq = 0x0020,
|
||||||
|
mmc_irq = 0x0010,
|
||||||
|
pmt_irq = 0x0008,
|
||||||
|
pcs_ane_irq = 0x0004,
|
||||||
|
pcs_link_irq = 0x0002,
|
||||||
|
rgmii_irq = 0x0001,
|
||||||
|
};
|
||||||
|
#define GMAC_INT_MASK 0x0000003c /* interrupt mask register */
|
||||||
|
|
||||||
|
/* PMT Control and Status */
|
||||||
|
#define GMAC_PMT 0x0000002c
|
||||||
|
enum power_event {
|
||||||
|
pointer_reset = 0x80000000,
|
||||||
|
global_unicast = 0x00000200,
|
||||||
|
wake_up_rx_frame = 0x00000040,
|
||||||
|
magic_frame = 0x00000020,
|
||||||
|
wake_up_frame_en = 0x00000004,
|
||||||
|
magic_pkt_en = 0x00000002,
|
||||||
|
power_down = 0x00000001,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* GMAC HW ADDR regs */
|
||||||
|
#define GMAC_ADDR_HIGH(reg) (0x00000040+(reg * 8))
|
||||||
|
#define GMAC_ADDR_LOW(reg) (0x00000044+(reg * 8))
|
||||||
|
#define GMAC_MAX_UNICAST_ADDRESSES 16
|
||||||
|
|
||||||
|
#define GMAC_AN_CTRL 0x000000c0 /* AN control */
|
||||||
|
#define GMAC_AN_STATUS 0x000000c4 /* AN status */
|
||||||
|
#define GMAC_ANE_ADV 0x000000c8 /* Auto-Neg. Advertisement */
|
||||||
|
#define GMAC_ANE_LINK 0x000000cc /* Auto-Neg. link partener ability */
|
||||||
|
#define GMAC_ANE_EXP 0x000000d0 /* ANE expansion */
|
||||||
|
#define GMAC_TBI 0x000000d4 /* TBI extend status */
|
||||||
|
#define GMAC_GMII_STATUS 0x000000d8 /* S/R-GMII status */
|
||||||
|
|
||||||
|
/* GMAC Configuration defines */
|
||||||
|
#define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */
|
||||||
|
#define GMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on receive */
|
||||||
|
#define GMAC_CONTROL_JD 0x00400000 /* Jabber disable */
|
||||||
|
#define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */
|
||||||
|
#define GMAC_CONTROL_JE 0x00100000 /* Jumbo frame */
|
||||||
|
enum inter_frame_gap {
|
||||||
|
GMAC_CONTROL_IFG_88 = 0x00040000,
|
||||||
|
GMAC_CONTROL_IFG_80 = 0x00020000,
|
||||||
|
GMAC_CONTROL_IFG_40 = 0x000e0000,
|
||||||
|
};
|
||||||
|
#define GMAC_CONTROL_DCRS 0x00010000 /* Disable carrier sense during tx */
|
||||||
|
#define GMAC_CONTROL_PS 0x00008000 /* Port Select 0:GMI 1:MII */
|
||||||
|
#define GMAC_CONTROL_FES 0x00004000 /* Speed 0:10 1:100 */
|
||||||
|
#define GMAC_CONTROL_DO 0x00002000 /* Disable Rx Own */
|
||||||
|
#define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
|
||||||
|
#define GMAC_CONTROL_DM 0x00000800 /* Duplex Mode */
|
||||||
|
#define GMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */
|
||||||
|
#define GMAC_CONTROL_DR 0x00000200 /* Disable Retry */
|
||||||
|
#define GMAC_CONTROL_LUD 0x00000100 /* Link up/down */
|
||||||
|
#define GMAC_CONTROL_ACS 0x00000080 /* Automatic Pad Stripping */
|
||||||
|
#define GMAC_CONTROL_DC 0x00000010 /* Deferral Check */
|
||||||
|
#define GMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */
|
||||||
|
#define GMAC_CONTROL_RE 0x00000004 /* Receiver Enable */
|
||||||
|
|
||||||
|
#define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | GMAC_CONTROL_ACS | \
|
||||||
|
GMAC_CONTROL_IPC | GMAC_CONTROL_JE | GMAC_CONTROL_BE)
|
||||||
|
|
||||||
|
/* GMAC Frame Filter defines */
|
||||||
|
#define GMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */
|
||||||
|
#define GMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */
|
||||||
|
#define GMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */
|
||||||
|
#define GMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */
|
||||||
|
#define GMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */
|
||||||
|
#define GMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */
|
||||||
|
#define GMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */
|
||||||
|
#define GMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */
|
||||||
|
#define GMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */
|
||||||
|
#define GMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */
|
||||||
|
/* GMII ADDR defines */
|
||||||
|
#define GMAC_MII_ADDR_WRITE 0x00000002 /* MII Write */
|
||||||
|
#define GMAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */
|
||||||
|
/* GMAC FLOW CTRL defines */
|
||||||
|
#define GMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */
|
||||||
|
#define GMAC_FLOW_CTRL_PT_SHIFT 16
|
||||||
|
#define GMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */
|
||||||
|
#define GMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */
|
||||||
|
#define GMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */
|
||||||
|
|
||||||
|
/*--- DMA BLOCK defines ---*/
|
||||||
|
/* DMA Bus Mode register defines */
|
||||||
|
#define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */
|
||||||
|
#define DMA_BUS_MODE_DA 0x00000002 /* Arbitration scheme */
|
||||||
|
#define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */
|
||||||
|
#define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */
|
||||||
|
/* Programmable burst length (passed thorugh platform)*/
|
||||||
|
#define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */
|
||||||
|
#define DMA_BUS_MODE_PBL_SHIFT 8
|
||||||
|
|
||||||
|
enum rx_tx_priority_ratio {
|
||||||
|
double_ratio = 0x00004000, /*2:1 */
|
||||||
|
triple_ratio = 0x00008000, /*3:1 */
|
||||||
|
quadruple_ratio = 0x0000c000, /*4:1 */
|
||||||
|
};
|
||||||
|
|
||||||
|
#define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */
|
||||||
|
#define DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */
|
||||||
|
#define DMA_BUS_MODE_RPBL_SHIFT 17
|
||||||
|
#define DMA_BUS_MODE_USP 0x00800000
|
||||||
|
#define DMA_BUS_MODE_4PBL 0x01000000
|
||||||
|
#define DMA_BUS_MODE_AAL 0x02000000
|
||||||
|
|
||||||
|
/* DMA CRS Control and Status Register Mapping */
|
||||||
|
#define DMA_HOST_TX_DESC 0x00001048 /* Current Host Tx descriptor */
|
||||||
|
#define DMA_HOST_RX_DESC 0x0000104c /* Current Host Rx descriptor */
|
||||||
|
/* DMA Bus Mode register defines */
|
||||||
|
#define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */
|
||||||
|
#define DMA_BUS_PR_RATIO_SHIFT 14
|
||||||
|
#define DMA_BUS_FB 0x00010000 /* Fixed Burst */
|
||||||
|
|
||||||
|
/* DMA operation mode defines (start/stop tx/rx are placed in common header)*/
|
||||||
|
#define DMA_CONTROL_DT 0x04000000 /* Disable Drop TCP/IP csum error */
|
||||||
|
#define DMA_CONTROL_RSF 0x02000000 /* Receive Store and Forward */
|
||||||
|
#define DMA_CONTROL_DFF 0x01000000 /* Disaable flushing */
|
||||||
|
/* Theshold for Activating the FC */
|
||||||
|
enum rfa {
|
||||||
|
act_full_minus_1 = 0x00800000,
|
||||||
|
act_full_minus_2 = 0x00800200,
|
||||||
|
act_full_minus_3 = 0x00800400,
|
||||||
|
act_full_minus_4 = 0x00800600,
|
||||||
|
};
|
||||||
|
/* Theshold for Deactivating the FC */
|
||||||
|
enum rfd {
|
||||||
|
deac_full_minus_1 = 0x00400000,
|
||||||
|
deac_full_minus_2 = 0x00400800,
|
||||||
|
deac_full_minus_3 = 0x00401000,
|
||||||
|
deac_full_minus_4 = 0x00401800,
|
||||||
|
};
|
||||||
|
#define DMA_CONTROL_TSF 0x00200000 /* Transmit Store and Forward */
|
||||||
|
#define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */
|
||||||
|
|
||||||
|
enum ttc_control {
|
||||||
|
DMA_CONTROL_TTC_64 = 0x00000000,
|
||||||
|
DMA_CONTROL_TTC_128 = 0x00004000,
|
||||||
|
DMA_CONTROL_TTC_192 = 0x00008000,
|
||||||
|
DMA_CONTROL_TTC_256 = 0x0000c000,
|
||||||
|
DMA_CONTROL_TTC_40 = 0x00010000,
|
||||||
|
DMA_CONTROL_TTC_32 = 0x00014000,
|
||||||
|
DMA_CONTROL_TTC_24 = 0x00018000,
|
||||||
|
DMA_CONTROL_TTC_16 = 0x0001c000,
|
||||||
|
};
|
||||||
|
#define DMA_CONTROL_TC_TX_MASK 0xfffe3fff
|
||||||
|
|
||||||
|
#define DMA_CONTROL_EFC 0x00000100
|
||||||
|
#define DMA_CONTROL_FEF 0x00000080
|
||||||
|
#define DMA_CONTROL_FUF 0x00000040
|
||||||
|
|
||||||
|
enum rtc_control {
|
||||||
|
DMA_CONTROL_RTC_64 = 0x00000000,
|
||||||
|
DMA_CONTROL_RTC_32 = 0x00000008,
|
||||||
|
DMA_CONTROL_RTC_96 = 0x00000010,
|
||||||
|
DMA_CONTROL_RTC_128 = 0x00000018,
|
||||||
|
};
|
||||||
|
#define DMA_CONTROL_TC_RX_MASK 0xffffffe7
|
||||||
|
|
||||||
|
#define DMA_CONTROL_OSF 0x00000004 /* Operate on second frame */
|
||||||
|
|
||||||
|
/* MMC registers offset */
|
||||||
|
#define GMAC_MMC_CTRL 0x100
|
||||||
|
#define GMAC_MMC_RX_INTR 0x104
|
||||||
|
#define GMAC_MMC_TX_INTR 0x108
|
||||||
|
#define GMAC_MMC_RX_CSUM_OFFLOAD 0x208
|
517
drivers/net/stmmac/mac100.c
Normal file
517
drivers/net/stmmac/mac100.c
Normal file
|
@ -0,0 +1,517 @@
|
||||||
|
/*******************************************************************************
|
||||||
|
This is the driver for the MAC 10/100 on-chip Ethernet controller
|
||||||
|
currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
|
||||||
|
|
||||||
|
DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
|
||||||
|
this code.
|
||||||
|
|
||||||
|
Copyright (C) 2007-2009 STMicroelectronics Ltd
|
||||||
|
|
||||||
|
This program is free software; you can redistribute it and/or modify it
|
||||||
|
under the terms and conditions of the GNU General Public License,
|
||||||
|
version 2, as published by the Free Software Foundation.
|
||||||
|
|
||||||
|
This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License along with
|
||||||
|
this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||||
|
|
||||||
|
The full GNU General Public License is included in this distribution in
|
||||||
|
the file called "COPYING".
|
||||||
|
|
||||||
|
Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
#include <linux/netdevice.h>
|
||||||
|
#include <linux/crc32.h>
|
||||||
|
#include <linux/mii.h>
|
||||||
|
#include <linux/phy.h>
|
||||||
|
|
||||||
|
#include "common.h"
|
||||||
|
#include "mac100.h"
|
||||||
|
|
||||||
|
#undef MAC100_DEBUG
|
||||||
|
/*#define MAC100_DEBUG*/
|
||||||
|
#ifdef MAC100_DEBUG
|
||||||
|
#define DBG(fmt, args...) printk(fmt, ## args)
|
||||||
|
#else
|
||||||
|
#define DBG(fmt, args...) do { } while (0)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static void mac100_core_init(unsigned long ioaddr)
|
||||||
|
{
|
||||||
|
u32 value = readl(ioaddr + MAC_CONTROL);
|
||||||
|
|
||||||
|
writel((value | MAC_CORE_INIT), ioaddr + MAC_CONTROL);
|
||||||
|
|
||||||
|
#ifdef STMMAC_VLAN_TAG_USED
|
||||||
|
writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
|
||||||
|
#endif
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mac100_dump_mac_regs(unsigned long ioaddr)
|
||||||
|
{
|
||||||
|
pr_info("\t----------------------------------------------\n"
|
||||||
|
"\t MAC100 CSR (base addr = 0x%8x)\n"
|
||||||
|
"\t----------------------------------------------\n",
|
||||||
|
(unsigned int)ioaddr);
|
||||||
|
pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,
|
||||||
|
readl(ioaddr + MAC_CONTROL));
|
||||||
|
pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,
|
||||||
|
readl(ioaddr + MAC_ADDR_HIGH));
|
||||||
|
pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW,
|
||||||
|
readl(ioaddr + MAC_ADDR_LOW));
|
||||||
|
pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n",
|
||||||
|
MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));
|
||||||
|
pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n",
|
||||||
|
MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));
|
||||||
|
pr_info("\tflow control (offset 0x%x): 0x%08x\n",
|
||||||
|
MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));
|
||||||
|
pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1,
|
||||||
|
readl(ioaddr + MAC_VLAN1));
|
||||||
|
pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,
|
||||||
|
readl(ioaddr + MAC_VLAN2));
|
||||||
|
pr_info("\n\tMAC management counter registers\n");
|
||||||
|
pr_info("\t MMC crtl (offset 0x%x): 0x%08x\n",
|
||||||
|
MMC_CONTROL, readl(ioaddr + MMC_CONTROL));
|
||||||
|
pr_info("\t MMC High Interrupt (offset 0x%x): 0x%08x\n",
|
||||||
|
MMC_HIGH_INTR, readl(ioaddr + MMC_HIGH_INTR));
|
||||||
|
pr_info("\t MMC Low Interrupt (offset 0x%x): 0x%08x\n",
|
||||||
|
MMC_LOW_INTR, readl(ioaddr + MMC_LOW_INTR));
|
||||||
|
pr_info("\t MMC High Interrupt Mask (offset 0x%x): 0x%08x\n",
|
||||||
|
MMC_HIGH_INTR_MASK, readl(ioaddr + MMC_HIGH_INTR_MASK));
|
||||||
|
pr_info("\t MMC Low Interrupt Mask (offset 0x%x): 0x%08x\n",
|
||||||
|
MMC_LOW_INTR_MASK, readl(ioaddr + MMC_LOW_INTR_MASK));
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mac100_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx,
|
||||||
|
u32 dma_rx)
|
||||||
|
{
|
||||||
|
u32 value = readl(ioaddr + DMA_BUS_MODE);
|
||||||
|
/* DMA SW reset */
|
||||||
|
value |= DMA_BUS_MODE_SFT_RESET;
|
||||||
|
writel(value, ioaddr + DMA_BUS_MODE);
|
||||||
|
do {} while ((readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET));
|
||||||
|
|
||||||
|
/* Enable Application Access by writing to DMA CSR0 */
|
||||||
|
writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT),
|
||||||
|
ioaddr + DMA_BUS_MODE);
|
||||||
|
|
||||||
|
/* Mask interrupts by writing to CSR7 */
|
||||||
|
writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
|
||||||
|
|
||||||
|
/* The base address of the RX/TX descriptor lists must be written into
|
||||||
|
* DMA CSR3 and CSR4, respectively. */
|
||||||
|
writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
|
||||||
|
writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Store and Forward capability is not used at all..
|
||||||
|
* The transmit threshold can be programmed by
|
||||||
|
* setting the TTC bits in the DMA control register.*/
|
||||||
|
static void mac100_dma_operation_mode(unsigned long ioaddr, int txmode,
|
||||||
|
int rxmode)
|
||||||
|
{
|
||||||
|
u32 csr6 = readl(ioaddr + DMA_CONTROL);
|
||||||
|
|
||||||
|
if (txmode <= 32)
|
||||||
|
csr6 |= DMA_CONTROL_TTC_32;
|
||||||
|
else if (txmode <= 64)
|
||||||
|
csr6 |= DMA_CONTROL_TTC_64;
|
||||||
|
else
|
||||||
|
csr6 |= DMA_CONTROL_TTC_128;
|
||||||
|
|
||||||
|
writel(csr6, ioaddr + DMA_CONTROL);
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mac100_dump_dma_regs(unsigned long ioaddr)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
DBG(KERN_DEBUG "MAC100 DMA CSR \n");
|
||||||
|
for (i = 0; i < 9; i++)
|
||||||
|
pr_debug("\t CSR%d (offset 0x%x): 0x%08x\n", i,
|
||||||
|
(DMA_BUS_MODE + i * 4),
|
||||||
|
readl(ioaddr + DMA_BUS_MODE + i * 4));
|
||||||
|
DBG(KERN_DEBUG "\t CSR20 (offset 0x%x): 0x%08x\n",
|
||||||
|
DMA_CUR_TX_BUF_ADDR, readl(ioaddr + DMA_CUR_TX_BUF_ADDR));
|
||||||
|
DBG(KERN_DEBUG "\t CSR21 (offset 0x%x): 0x%08x\n",
|
||||||
|
DMA_CUR_RX_BUF_ADDR, readl(ioaddr + DMA_CUR_RX_BUF_ADDR));
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* DMA controller has two counters to track the number of
|
||||||
|
the receive missed frames. */
|
||||||
|
static void mac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x,
|
||||||
|
unsigned long ioaddr)
|
||||||
|
{
|
||||||
|
struct net_device_stats *stats = (struct net_device_stats *)data;
|
||||||
|
u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR);
|
||||||
|
|
||||||
|
if (unlikely(csr8)) {
|
||||||
|
if (csr8 & DMA_MISSED_FRAME_OVE) {
|
||||||
|
stats->rx_over_errors += 0x800;
|
||||||
|
x->rx_overflow_cntr += 0x800;
|
||||||
|
} else {
|
||||||
|
unsigned int ove_cntr;
|
||||||
|
ove_cntr = ((csr8 & DMA_MISSED_FRAME_OVE_CNTR) >> 17);
|
||||||
|
stats->rx_over_errors += ove_cntr;
|
||||||
|
x->rx_overflow_cntr += ove_cntr;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (csr8 & DMA_MISSED_FRAME_OVE_M) {
|
||||||
|
stats->rx_missed_errors += 0xffff;
|
||||||
|
x->rx_missed_cntr += 0xffff;
|
||||||
|
} else {
|
||||||
|
unsigned int miss_f = (csr8 & DMA_MISSED_FRAME_M_CNTR);
|
||||||
|
stats->rx_missed_errors += miss_f;
|
||||||
|
x->rx_missed_cntr += miss_f;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mac100_get_tx_frame_status(void *data, struct stmmac_extra_stats *x,
|
||||||
|
struct dma_desc *p, unsigned long ioaddr)
|
||||||
|
{
|
||||||
|
int ret = 0;
|
||||||
|
struct net_device_stats *stats = (struct net_device_stats *)data;
|
||||||
|
|
||||||
|
if (unlikely(p->des01.tx.error_summary)) {
|
||||||
|
if (unlikely(p->des01.tx.underflow_error)) {
|
||||||
|
x->tx_underflow++;
|
||||||
|
stats->tx_fifo_errors++;
|
||||||
|
}
|
||||||
|
if (unlikely(p->des01.tx.no_carrier)) {
|
||||||
|
x->tx_carrier++;
|
||||||
|
stats->tx_carrier_errors++;
|
||||||
|
}
|
||||||
|
if (unlikely(p->des01.tx.loss_carrier)) {
|
||||||
|
x->tx_losscarrier++;
|
||||||
|
stats->tx_carrier_errors++;
|
||||||
|
}
|
||||||
|
if (unlikely((p->des01.tx.excessive_deferral) ||
|
||||||
|
(p->des01.tx.excessive_collisions) ||
|
||||||
|
(p->des01.tx.late_collision)))
|
||||||
|
stats->collisions += p->des01.tx.collision_count;
|
||||||
|
ret = -1;
|
||||||
|
}
|
||||||
|
if (unlikely(p->des01.tx.heartbeat_fail)) {
|
||||||
|
x->tx_heartbeat++;
|
||||||
|
stats->tx_heartbeat_errors++;
|
||||||
|
ret = -1;
|
||||||
|
}
|
||||||
|
if (unlikely(p->des01.tx.deferred))
|
||||||
|
x->tx_deferred++;
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mac100_get_tx_len(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
return p->des01.tx.buffer1_size;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* This function verifies if each incoming frame has some errors
|
||||||
|
* and, if required, updates the multicast statistics.
|
||||||
|
* In case of success, it returns csum_none becasue the device
|
||||||
|
* is not able to compute the csum in HW. */
|
||||||
|
static int mac100_get_rx_frame_status(void *data, struct stmmac_extra_stats *x,
|
||||||
|
struct dma_desc *p)
|
||||||
|
{
|
||||||
|
int ret = csum_none;
|
||||||
|
struct net_device_stats *stats = (struct net_device_stats *)data;
|
||||||
|
|
||||||
|
if (unlikely(p->des01.rx.last_descriptor == 0)) {
|
||||||
|
pr_warning("mac100 Error: Oversized Ethernet "
|
||||||
|
"frame spanned multiple buffers\n");
|
||||||
|
stats->rx_length_errors++;
|
||||||
|
return discard_frame;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (unlikely(p->des01.rx.error_summary)) {
|
||||||
|
if (unlikely(p->des01.rx.descriptor_error))
|
||||||
|
x->rx_desc++;
|
||||||
|
if (unlikely(p->des01.rx.partial_frame_error))
|
||||||
|
x->rx_partial++;
|
||||||
|
if (unlikely(p->des01.rx.run_frame))
|
||||||
|
x->rx_runt++;
|
||||||
|
if (unlikely(p->des01.rx.frame_too_long))
|
||||||
|
x->rx_toolong++;
|
||||||
|
if (unlikely(p->des01.rx.collision)) {
|
||||||
|
x->rx_collision++;
|
||||||
|
stats->collisions++;
|
||||||
|
}
|
||||||
|
if (unlikely(p->des01.rx.crc_error)) {
|
||||||
|
x->rx_crc++;
|
||||||
|
stats->rx_crc_errors++;
|
||||||
|
}
|
||||||
|
ret = discard_frame;
|
||||||
|
}
|
||||||
|
if (unlikely(p->des01.rx.dribbling))
|
||||||
|
ret = discard_frame;
|
||||||
|
|
||||||
|
if (unlikely(p->des01.rx.length_error)) {
|
||||||
|
x->rx_lenght++;
|
||||||
|
ret = discard_frame;
|
||||||
|
}
|
||||||
|
if (unlikely(p->des01.rx.mii_error)) {
|
||||||
|
x->rx_mii++;
|
||||||
|
ret = discard_frame;
|
||||||
|
}
|
||||||
|
if (p->des01.rx.multicast_frame) {
|
||||||
|
x->rx_multicast++;
|
||||||
|
stats->multicast++;
|
||||||
|
}
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mac100_irq_status(unsigned long ioaddr)
|
||||||
|
{
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mac100_set_umac_addr(unsigned long ioaddr, unsigned char *addr,
|
||||||
|
unsigned int reg_n)
|
||||||
|
{
|
||||||
|
stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mac100_get_umac_addr(unsigned long ioaddr, unsigned char *addr,
|
||||||
|
unsigned int reg_n)
|
||||||
|
{
|
||||||
|
stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mac100_set_filter(struct net_device *dev)
|
||||||
|
{
|
||||||
|
unsigned long ioaddr = dev->base_addr;
|
||||||
|
u32 value = readl(ioaddr + MAC_CONTROL);
|
||||||
|
|
||||||
|
if (dev->flags & IFF_PROMISC) {
|
||||||
|
value |= MAC_CONTROL_PR;
|
||||||
|
value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO |
|
||||||
|
MAC_CONTROL_HP);
|
||||||
|
} else if ((dev->mc_count > HASH_TABLE_SIZE)
|
||||||
|
|| (dev->flags & IFF_ALLMULTI)) {
|
||||||
|
value |= MAC_CONTROL_PM;
|
||||||
|
value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO);
|
||||||
|
writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
|
||||||
|
writel(0xffffffff, ioaddr + MAC_HASH_LOW);
|
||||||
|
} else if (dev->mc_count == 0) { /* no multicast */
|
||||||
|
value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF |
|
||||||
|
MAC_CONTROL_HO | MAC_CONTROL_HP);
|
||||||
|
} else {
|
||||||
|
int i;
|
||||||
|
u32 mc_filter[2];
|
||||||
|
struct dev_mc_list *mclist;
|
||||||
|
|
||||||
|
/* Perfect filter mode for physical address and Hash
|
||||||
|
filter for multicast */
|
||||||
|
value |= MAC_CONTROL_HP;
|
||||||
|
value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF
|
||||||
|
| MAC_CONTROL_HO);
|
||||||
|
|
||||||
|
memset(mc_filter, 0, sizeof(mc_filter));
|
||||||
|
for (i = 0, mclist = dev->mc_list;
|
||||||
|
mclist && i < dev->mc_count; i++, mclist = mclist->next) {
|
||||||
|
/* The upper 6 bits of the calculated CRC are used to
|
||||||
|
* index the contens of the hash table */
|
||||||
|
int bit_nr =
|
||||||
|
ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
|
||||||
|
/* The most significant bit determines the register to
|
||||||
|
* use (H/L) while the other 5 bits determine the bit
|
||||||
|
* within the register. */
|
||||||
|
mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
|
||||||
|
}
|
||||||
|
writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
|
||||||
|
writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
|
||||||
|
}
|
||||||
|
|
||||||
|
writel(value, ioaddr + MAC_CONTROL);
|
||||||
|
|
||||||
|
DBG(KERN_INFO "%s: CTRL reg: 0x%08x Hash regs: "
|
||||||
|
"HI 0x%08x, LO 0x%08x\n",
|
||||||
|
__func__, readl(ioaddr + MAC_CONTROL),
|
||||||
|
readl(ioaddr + MAC_HASH_HIGH), readl(ioaddr + MAC_HASH_LOW));
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mac100_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
|
||||||
|
unsigned int fc, unsigned int pause_time)
|
||||||
|
{
|
||||||
|
unsigned int flow = MAC_FLOW_CTRL_ENABLE;
|
||||||
|
|
||||||
|
if (duplex)
|
||||||
|
flow |= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
|
||||||
|
writel(flow, ioaddr + MAC_FLOW_CTRL);
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* No PMT module supported in our SoC for the Ethernet Controller. */
|
||||||
|
static void mac100_pmt(unsigned long ioaddr, unsigned long mode)
|
||||||
|
{
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mac100_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
|
||||||
|
int disable_rx_ic)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
for (i = 0; i < ring_size; i++) {
|
||||||
|
p->des01.rx.own = 1;
|
||||||
|
p->des01.rx.buffer1_size = BUF_SIZE_2KiB - 1;
|
||||||
|
if (i == ring_size - 1)
|
||||||
|
p->des01.rx.end_ring = 1;
|
||||||
|
if (disable_rx_ic)
|
||||||
|
p->des01.rx.disable_ic = 1;
|
||||||
|
p++;
|
||||||
|
}
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mac100_init_tx_desc(struct dma_desc *p, unsigned int ring_size)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
for (i = 0; i < ring_size; i++) {
|
||||||
|
p->des01.tx.own = 0;
|
||||||
|
if (i == ring_size - 1)
|
||||||
|
p->des01.tx.end_ring = 1;
|
||||||
|
p++;
|
||||||
|
}
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mac100_get_tx_owner(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
return p->des01.tx.own;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mac100_get_rx_owner(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
return p->des01.rx.own;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mac100_set_tx_owner(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
p->des01.tx.own = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mac100_set_rx_owner(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
p->des01.rx.own = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mac100_get_tx_ls(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
return p->des01.tx.last_segment;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mac100_release_tx_desc(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
int ter = p->des01.tx.end_ring;
|
||||||
|
|
||||||
|
/* clean field used within the xmit */
|
||||||
|
p->des01.tx.first_segment = 0;
|
||||||
|
p->des01.tx.last_segment = 0;
|
||||||
|
p->des01.tx.buffer1_size = 0;
|
||||||
|
|
||||||
|
/* clean status reported */
|
||||||
|
p->des01.tx.error_summary = 0;
|
||||||
|
p->des01.tx.underflow_error = 0;
|
||||||
|
p->des01.tx.no_carrier = 0;
|
||||||
|
p->des01.tx.loss_carrier = 0;
|
||||||
|
p->des01.tx.excessive_deferral = 0;
|
||||||
|
p->des01.tx.excessive_collisions = 0;
|
||||||
|
p->des01.tx.late_collision = 0;
|
||||||
|
p->des01.tx.heartbeat_fail = 0;
|
||||||
|
p->des01.tx.deferred = 0;
|
||||||
|
|
||||||
|
/* set termination field */
|
||||||
|
p->des01.tx.end_ring = ter;
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mac100_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
|
||||||
|
int csum_flag)
|
||||||
|
{
|
||||||
|
p->des01.tx.first_segment = is_fs;
|
||||||
|
p->des01.tx.buffer1_size = len;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mac100_clear_tx_ic(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
p->des01.tx.interrupt = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mac100_close_tx_desc(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
p->des01.tx.last_segment = 1;
|
||||||
|
p->des01.tx.interrupt = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mac100_get_rx_frame_len(struct dma_desc *p)
|
||||||
|
{
|
||||||
|
return p->des01.rx.frame_length;
|
||||||
|
}
|
||||||
|
|
||||||
|
struct stmmac_ops mac100_driver = {
|
||||||
|
.core_init = mac100_core_init,
|
||||||
|
.dump_mac_regs = mac100_dump_mac_regs,
|
||||||
|
.dma_init = mac100_dma_init,
|
||||||
|
.dump_dma_regs = mac100_dump_dma_regs,
|
||||||
|
.dma_mode = mac100_dma_operation_mode,
|
||||||
|
.dma_diagnostic_fr = mac100_dma_diagnostic_fr,
|
||||||
|
.tx_status = mac100_get_tx_frame_status,
|
||||||
|
.rx_status = mac100_get_rx_frame_status,
|
||||||
|
.get_tx_len = mac100_get_tx_len,
|
||||||
|
.set_filter = mac100_set_filter,
|
||||||
|
.flow_ctrl = mac100_flow_ctrl,
|
||||||
|
.pmt = mac100_pmt,
|
||||||
|
.init_rx_desc = mac100_init_rx_desc,
|
||||||
|
.init_tx_desc = mac100_init_tx_desc,
|
||||||
|
.get_tx_owner = mac100_get_tx_owner,
|
||||||
|
.get_rx_owner = mac100_get_rx_owner,
|
||||||
|
.release_tx_desc = mac100_release_tx_desc,
|
||||||
|
.prepare_tx_desc = mac100_prepare_tx_desc,
|
||||||
|
.clear_tx_ic = mac100_clear_tx_ic,
|
||||||
|
.close_tx_desc = mac100_close_tx_desc,
|
||||||
|
.get_tx_ls = mac100_get_tx_ls,
|
||||||
|
.set_tx_owner = mac100_set_tx_owner,
|
||||||
|
.set_rx_owner = mac100_set_rx_owner,
|
||||||
|
.get_rx_frame_len = mac100_get_rx_frame_len,
|
||||||
|
.host_irq_status = mac100_irq_status,
|
||||||
|
.set_umac_addr = mac100_set_umac_addr,
|
||||||
|
.get_umac_addr = mac100_get_umac_addr,
|
||||||
|
};
|
||||||
|
|
||||||
|
struct mac_device_info *mac100_setup(unsigned long ioaddr)
|
||||||
|
{
|
||||||
|
struct mac_device_info *mac;
|
||||||
|
|
||||||
|
mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
|
||||||
|
|
||||||
|
pr_info("\tMAC 10/100\n");
|
||||||
|
|
||||||
|
mac->ops = &mac100_driver;
|
||||||
|
mac->hw.pmt = PMT_NOT_SUPPORTED;
|
||||||
|
mac->hw.link.port = MAC_CONTROL_PS;
|
||||||
|
mac->hw.link.duplex = MAC_CONTROL_F;
|
||||||
|
mac->hw.link.speed = 0;
|
||||||
|
mac->hw.mii.addr = MAC_MII_ADDR;
|
||||||
|
mac->hw.mii.data = MAC_MII_DATA;
|
||||||
|
|
||||||
|
return mac;
|
||||||
|
}
|
116
drivers/net/stmmac/mac100.h
Normal file
116
drivers/net/stmmac/mac100.h
Normal file
|
@ -0,0 +1,116 @@
|
||||||
|
/*******************************************************************************
|
||||||
|
MAC 10/100 Header File
|
||||||
|
|
||||||
|
Copyright (C) 2007-2009 STMicroelectronics Ltd
|
||||||
|
|
||||||
|
This program is free software; you can redistribute it and/or modify it
|
||||||
|
under the terms and conditions of the GNU General Public License,
|
||||||
|
version 2, as published by the Free Software Foundation.
|
||||||
|
|
||||||
|
This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License along with
|
||||||
|
this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||||
|
|
||||||
|
The full GNU General Public License is included in this distribution in
|
||||||
|
the file called "COPYING".
|
||||||
|
|
||||||
|
Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------
|
||||||
|
* MAC BLOCK defines
|
||||||
|
*---------------------------------------------------------------------------*/
|
||||||
|
/* MAC CSR offset */
|
||||||
|
#define MAC_CONTROL 0x00000000 /* MAC Control */
|
||||||
|
#define MAC_ADDR_HIGH 0x00000004 /* MAC Address High */
|
||||||
|
#define MAC_ADDR_LOW 0x00000008 /* MAC Address Low */
|
||||||
|
#define MAC_HASH_HIGH 0x0000000c /* Multicast Hash Table High */
|
||||||
|
#define MAC_HASH_LOW 0x00000010 /* Multicast Hash Table Low */
|
||||||
|
#define MAC_MII_ADDR 0x00000014 /* MII Address */
|
||||||
|
#define MAC_MII_DATA 0x00000018 /* MII Data */
|
||||||
|
#define MAC_FLOW_CTRL 0x0000001c /* Flow Control */
|
||||||
|
#define MAC_VLAN1 0x00000020 /* VLAN1 Tag */
|
||||||
|
#define MAC_VLAN2 0x00000024 /* VLAN2 Tag */
|
||||||
|
|
||||||
|
/* MAC CTRL defines */
|
||||||
|
#define MAC_CONTROL_RA 0x80000000 /* Receive All Mode */
|
||||||
|
#define MAC_CONTROL_BLE 0x40000000 /* Endian Mode */
|
||||||
|
#define MAC_CONTROL_HBD 0x10000000 /* Heartbeat Disable */
|
||||||
|
#define MAC_CONTROL_PS 0x08000000 /* Port Select */
|
||||||
|
#define MAC_CONTROL_DRO 0x00800000 /* Disable Receive Own */
|
||||||
|
#define MAC_CONTROL_EXT_LOOPBACK 0x00400000 /* Reserved (ext loopback?) */
|
||||||
|
#define MAC_CONTROL_OM 0x00200000 /* Loopback Operating Mode */
|
||||||
|
#define MAC_CONTROL_F 0x00100000 /* Full Duplex Mode */
|
||||||
|
#define MAC_CONTROL_PM 0x00080000 /* Pass All Multicast */
|
||||||
|
#define MAC_CONTROL_PR 0x00040000 /* Promiscuous Mode */
|
||||||
|
#define MAC_CONTROL_IF 0x00020000 /* Inverse Filtering */
|
||||||
|
#define MAC_CONTROL_PB 0x00010000 /* Pass Bad Frames */
|
||||||
|
#define MAC_CONTROL_HO 0x00008000 /* Hash Only Filtering Mode */
|
||||||
|
#define MAC_CONTROL_HP 0x00002000 /* Hash/Perfect Filtering Mode */
|
||||||
|
#define MAC_CONTROL_LCC 0x00001000 /* Late Collision Control */
|
||||||
|
#define MAC_CONTROL_DBF 0x00000800 /* Disable Broadcast Frames */
|
||||||
|
#define MAC_CONTROL_DRTY 0x00000400 /* Disable Retry */
|
||||||
|
#define MAC_CONTROL_ASTP 0x00000100 /* Automatic Pad Stripping */
|
||||||
|
#define MAC_CONTROL_BOLMT_10 0x00000000 /* Back Off Limit 10 */
|
||||||
|
#define MAC_CONTROL_BOLMT_8 0x00000040 /* Back Off Limit 8 */
|
||||||
|
#define MAC_CONTROL_BOLMT_4 0x00000080 /* Back Off Limit 4 */
|
||||||
|
#define MAC_CONTROL_BOLMT_1 0x000000c0 /* Back Off Limit 1 */
|
||||||
|
#define MAC_CONTROL_DC 0x00000020 /* Deferral Check */
|
||||||
|
#define MAC_CONTROL_TE 0x00000008 /* Transmitter Enable */
|
||||||
|
#define MAC_CONTROL_RE 0x00000004 /* Receiver Enable */
|
||||||
|
|
||||||
|
#define MAC_CORE_INIT (MAC_CONTROL_HBD | MAC_CONTROL_ASTP)
|
||||||
|
|
||||||
|
/* MAC FLOW CTRL defines */
|
||||||
|
#define MAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */
|
||||||
|
#define MAC_FLOW_CTRL_PT_SHIFT 16
|
||||||
|
#define MAC_FLOW_CTRL_PASS 0x00000004 /* Pass Control Frames */
|
||||||
|
#define MAC_FLOW_CTRL_ENABLE 0x00000002 /* Flow Control Enable */
|
||||||
|
#define MAC_FLOW_CTRL_PAUSE 0x00000001 /* Flow Control Busy ... */
|
||||||
|
|
||||||
|
/* MII ADDR defines */
|
||||||
|
#define MAC_MII_ADDR_WRITE 0x00000002 /* MII Write */
|
||||||
|
#define MAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------
|
||||||
|
* DMA BLOCK defines
|
||||||
|
*---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* DMA Bus Mode register defines */
|
||||||
|
#define DMA_BUS_MODE_DBO 0x00100000 /* Descriptor Byte Ordering */
|
||||||
|
#define DMA_BUS_MODE_BLE 0x00000080 /* Big Endian/Little Endian */
|
||||||
|
#define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */
|
||||||
|
#define DMA_BUS_MODE_PBL_SHIFT 8
|
||||||
|
#define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */
|
||||||
|
#define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */
|
||||||
|
#define DMA_BUS_MODE_BAR_BUS 0x00000002 /* Bar-Bus Arbitration */
|
||||||
|
#define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */
|
||||||
|
#define DMA_BUS_MODE_DEFAULT 0x00000000
|
||||||
|
|
||||||
|
/* DMA Control register defines */
|
||||||
|
#define DMA_CONTROL_SF 0x00200000 /* Store And Forward */
|
||||||
|
|
||||||
|
/* Transmit Threshold Control */
|
||||||
|
enum ttc_control {
|
||||||
|
DMA_CONTROL_TTC_DEFAULT = 0x00000000, /* Threshold is 32 DWORDS */
|
||||||
|
DMA_CONTROL_TTC_64 = 0x00004000, /* Threshold is 64 DWORDS */
|
||||||
|
DMA_CONTROL_TTC_128 = 0x00008000, /* Threshold is 128 DWORDS */
|
||||||
|
DMA_CONTROL_TTC_256 = 0x0000c000, /* Threshold is 256 DWORDS */
|
||||||
|
DMA_CONTROL_TTC_18 = 0x00400000, /* Threshold is 18 DWORDS */
|
||||||
|
DMA_CONTROL_TTC_24 = 0x00404000, /* Threshold is 24 DWORDS */
|
||||||
|
DMA_CONTROL_TTC_32 = 0x00408000, /* Threshold is 32 DWORDS */
|
||||||
|
DMA_CONTROL_TTC_40 = 0x0040c000, /* Threshold is 40 DWORDS */
|
||||||
|
DMA_CONTROL_SE = 0x00000008, /* Stop On Empty */
|
||||||
|
DMA_CONTROL_OSF = 0x00000004, /* Operate On 2nd Frame */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* STMAC110 DMA Missed Frame Counter register defines */
|
||||||
|
#define DMA_MISSED_FRAME_OVE 0x10000000 /* FIFO Overflow Overflow */
|
||||||
|
#define DMA_MISSED_FRAME_OVE_CNTR 0x0ffe0000 /* Overflow Frame Counter */
|
||||||
|
#define DMA_MISSED_FRAME_OVE_M 0x00010000 /* Missed Frame Overflow */
|
||||||
|
#define DMA_MISSED_FRAME_M_CNTR 0x0000ffff /* Missed Frame Couinter */
|
98
drivers/net/stmmac/stmmac.h
Normal file
98
drivers/net/stmmac/stmmac.h
Normal file
|
@ -0,0 +1,98 @@
|
||||||
|
/*******************************************************************************
|
||||||
|
Copyright (C) 2007-2009 STMicroelectronics Ltd
|
||||||
|
|
||||||
|
This program is free software; you can redistribute it and/or modify it
|
||||||
|
under the terms and conditions of the GNU General Public License,
|
||||||
|
version 2, as published by the Free Software Foundation.
|
||||||
|
|
||||||
|
This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License along with
|
||||||
|
this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||||
|
|
||||||
|
The full GNU General Public License is included in this distribution in
|
||||||
|
the file called "COPYING".
|
||||||
|
|
||||||
|
Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
#define DRV_MODULE_VERSION "Oct_09"
|
||||||
|
|
||||||
|
#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
|
||||||
|
#define STMMAC_VLAN_TAG_USED
|
||||||
|
#include <linux/if_vlan.h>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "common.h"
|
||||||
|
#ifdef CONFIG_STMMAC_TIMER
|
||||||
|
#include "stmmac_timer.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
struct stmmac_priv {
|
||||||
|
/* Frequently used values are kept adjacent for cache effect */
|
||||||
|
struct dma_desc *dma_tx ____cacheline_aligned;
|
||||||
|
dma_addr_t dma_tx_phy;
|
||||||
|
struct sk_buff **tx_skbuff;
|
||||||
|
unsigned int cur_tx;
|
||||||
|
unsigned int dirty_tx;
|
||||||
|
unsigned int dma_tx_size;
|
||||||
|
int tx_coe;
|
||||||
|
int tx_coalesce;
|
||||||
|
|
||||||
|
struct dma_desc *dma_rx ;
|
||||||
|
unsigned int cur_rx;
|
||||||
|
unsigned int dirty_rx;
|
||||||
|
struct sk_buff **rx_skbuff;
|
||||||
|
dma_addr_t *rx_skbuff_dma;
|
||||||
|
struct sk_buff_head rx_recycle;
|
||||||
|
|
||||||
|
struct net_device *dev;
|
||||||
|
int is_gmac;
|
||||||
|
dma_addr_t dma_rx_phy;
|
||||||
|
unsigned int dma_rx_size;
|
||||||
|
int rx_csum;
|
||||||
|
unsigned int dma_buf_sz;
|
||||||
|
struct device *device;
|
||||||
|
struct mac_device_info *mac_type;
|
||||||
|
|
||||||
|
struct stmmac_extra_stats xstats;
|
||||||
|
struct napi_struct napi;
|
||||||
|
|
||||||
|
phy_interface_t phy_interface;
|
||||||
|
int pbl;
|
||||||
|
int bus_id;
|
||||||
|
int phy_addr;
|
||||||
|
int phy_mask;
|
||||||
|
int (*phy_reset) (void *priv);
|
||||||
|
void (*fix_mac_speed) (void *priv, unsigned int speed);
|
||||||
|
void *bsp_priv;
|
||||||
|
|
||||||
|
int phy_irq;
|
||||||
|
struct phy_device *phydev;
|
||||||
|
int oldlink;
|
||||||
|
int speed;
|
||||||
|
int oldduplex;
|
||||||
|
unsigned int flow_ctrl;
|
||||||
|
unsigned int pause;
|
||||||
|
struct mii_bus *mii;
|
||||||
|
|
||||||
|
u32 msg_enable;
|
||||||
|
spinlock_t lock;
|
||||||
|
int wolopts;
|
||||||
|
int wolenabled;
|
||||||
|
int shutdown;
|
||||||
|
#ifdef CONFIG_STMMAC_TIMER
|
||||||
|
struct stmmac_timer *tm;
|
||||||
|
#endif
|
||||||
|
#ifdef STMMAC_VLAN_TAG_USED
|
||||||
|
struct vlan_group *vlgrp;
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
extern int stmmac_mdio_unregister(struct net_device *ndev);
|
||||||
|
extern int stmmac_mdio_register(struct net_device *ndev);
|
||||||
|
extern void stmmac_set_ethtool_ops(struct net_device *netdev);
|
395
drivers/net/stmmac/stmmac_ethtool.c
Normal file
395
drivers/net/stmmac/stmmac_ethtool.c
Normal file
|
@ -0,0 +1,395 @@
|
||||||
|
/*******************************************************************************
|
||||||
|
STMMAC Ethtool support
|
||||||
|
|
||||||
|
Copyright (C) 2007-2009 STMicroelectronics Ltd
|
||||||
|
|
||||||
|
This program is free software; you can redistribute it and/or modify it
|
||||||
|
under the terms and conditions of the GNU General Public License,
|
||||||
|
version 2, as published by the Free Software Foundation.
|
||||||
|
|
||||||
|
This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License along with
|
||||||
|
this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||||
|
|
||||||
|
The full GNU General Public License is included in this distribution in
|
||||||
|
the file called "COPYING".
|
||||||
|
|
||||||
|
Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
#include <linux/etherdevice.h>
|
||||||
|
#include <linux/ethtool.h>
|
||||||
|
#include <linux/mii.h>
|
||||||
|
#include <linux/phy.h>
|
||||||
|
|
||||||
|
#include "stmmac.h"
|
||||||
|
|
||||||
|
#define REG_SPACE_SIZE 0x1054
|
||||||
|
#define MAC100_ETHTOOL_NAME "st_mac100"
|
||||||
|
#define GMAC_ETHTOOL_NAME "st_gmac"
|
||||||
|
|
||||||
|
struct stmmac_stats {
|
||||||
|
char stat_string[ETH_GSTRING_LEN];
|
||||||
|
int sizeof_stat;
|
||||||
|
int stat_offset;
|
||||||
|
};
|
||||||
|
|
||||||
|
#define STMMAC_STAT(m) \
|
||||||
|
{ #m, FIELD_SIZEOF(struct stmmac_extra_stats, m), \
|
||||||
|
offsetof(struct stmmac_priv, xstats.m)}
|
||||||
|
|
||||||
|
static const struct stmmac_stats stmmac_gstrings_stats[] = {
|
||||||
|
STMMAC_STAT(tx_underflow),
|
||||||
|
STMMAC_STAT(tx_carrier),
|
||||||
|
STMMAC_STAT(tx_losscarrier),
|
||||||
|
STMMAC_STAT(tx_heartbeat),
|
||||||
|
STMMAC_STAT(tx_deferred),
|
||||||
|
STMMAC_STAT(tx_vlan),
|
||||||
|
STMMAC_STAT(rx_vlan),
|
||||||
|
STMMAC_STAT(tx_jabber),
|
||||||
|
STMMAC_STAT(tx_frame_flushed),
|
||||||
|
STMMAC_STAT(tx_payload_error),
|
||||||
|
STMMAC_STAT(tx_ip_header_error),
|
||||||
|
STMMAC_STAT(rx_desc),
|
||||||
|
STMMAC_STAT(rx_partial),
|
||||||
|
STMMAC_STAT(rx_runt),
|
||||||
|
STMMAC_STAT(rx_toolong),
|
||||||
|
STMMAC_STAT(rx_collision),
|
||||||
|
STMMAC_STAT(rx_crc),
|
||||||
|
STMMAC_STAT(rx_lenght),
|
||||||
|
STMMAC_STAT(rx_mii),
|
||||||
|
STMMAC_STAT(rx_multicast),
|
||||||
|
STMMAC_STAT(rx_gmac_overflow),
|
||||||
|
STMMAC_STAT(rx_watchdog),
|
||||||
|
STMMAC_STAT(da_rx_filter_fail),
|
||||||
|
STMMAC_STAT(sa_rx_filter_fail),
|
||||||
|
STMMAC_STAT(rx_missed_cntr),
|
||||||
|
STMMAC_STAT(rx_overflow_cntr),
|
||||||
|
STMMAC_STAT(tx_undeflow_irq),
|
||||||
|
STMMAC_STAT(tx_process_stopped_irq),
|
||||||
|
STMMAC_STAT(tx_jabber_irq),
|
||||||
|
STMMAC_STAT(rx_overflow_irq),
|
||||||
|
STMMAC_STAT(rx_buf_unav_irq),
|
||||||
|
STMMAC_STAT(rx_process_stopped_irq),
|
||||||
|
STMMAC_STAT(rx_watchdog_irq),
|
||||||
|
STMMAC_STAT(tx_early_irq),
|
||||||
|
STMMAC_STAT(fatal_bus_error_irq),
|
||||||
|
STMMAC_STAT(threshold),
|
||||||
|
STMMAC_STAT(tx_pkt_n),
|
||||||
|
STMMAC_STAT(rx_pkt_n),
|
||||||
|
STMMAC_STAT(poll_n),
|
||||||
|
STMMAC_STAT(sched_timer_n),
|
||||||
|
STMMAC_STAT(normal_irq_n),
|
||||||
|
};
|
||||||
|
#define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats)
|
||||||
|
|
||||||
|
void stmmac_ethtool_getdrvinfo(struct net_device *dev,
|
||||||
|
struct ethtool_drvinfo *info)
|
||||||
|
{
|
||||||
|
struct stmmac_priv *priv = netdev_priv(dev);
|
||||||
|
|
||||||
|
if (!priv->is_gmac)
|
||||||
|
strcpy(info->driver, MAC100_ETHTOOL_NAME);
|
||||||
|
else
|
||||||
|
strcpy(info->driver, GMAC_ETHTOOL_NAME);
|
||||||
|
|
||||||
|
strcpy(info->version, DRV_MODULE_VERSION);
|
||||||
|
info->fw_version[0] = '\0';
|
||||||
|
info->n_stats = STMMAC_STATS_LEN;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
int stmmac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
|
||||||
|
{
|
||||||
|
struct stmmac_priv *priv = netdev_priv(dev);
|
||||||
|
struct phy_device *phy = priv->phydev;
|
||||||
|
int rc;
|
||||||
|
if (phy == NULL) {
|
||||||
|
pr_err("%s: %s: PHY is not registered\n",
|
||||||
|
__func__, dev->name);
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
if (!netif_running(dev)) {
|
||||||
|
pr_err("%s: interface is disabled: we cannot track "
|
||||||
|
"link speed / duplex setting\n", dev->name);
|
||||||
|
return -EBUSY;
|
||||||
|
}
|
||||||
|
cmd->transceiver = XCVR_INTERNAL;
|
||||||
|
spin_lock_irq(&priv->lock);
|
||||||
|
rc = phy_ethtool_gset(phy, cmd);
|
||||||
|
spin_unlock_irq(&priv->lock);
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
|
||||||
|
int stmmac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
|
||||||
|
{
|
||||||
|
struct stmmac_priv *priv = netdev_priv(dev);
|
||||||
|
struct phy_device *phy = priv->phydev;
|
||||||
|
int rc;
|
||||||
|
|
||||||
|
spin_lock(&priv->lock);
|
||||||
|
rc = phy_ethtool_sset(phy, cmd);
|
||||||
|
spin_unlock(&priv->lock);
|
||||||
|
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 stmmac_ethtool_getmsglevel(struct net_device *dev)
|
||||||
|
{
|
||||||
|
struct stmmac_priv *priv = netdev_priv(dev);
|
||||||
|
return priv->msg_enable;
|
||||||
|
}
|
||||||
|
|
||||||
|
void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level)
|
||||||
|
{
|
||||||
|
struct stmmac_priv *priv = netdev_priv(dev);
|
||||||
|
priv->msg_enable = level;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
int stmmac_check_if_running(struct net_device *dev)
|
||||||
|
{
|
||||||
|
if (!netif_running(dev))
|
||||||
|
return -EBUSY;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int stmmac_ethtool_get_regs_len(struct net_device *dev)
|
||||||
|
{
|
||||||
|
return REG_SPACE_SIZE;
|
||||||
|
}
|
||||||
|
|
||||||
|
void stmmac_ethtool_gregs(struct net_device *dev,
|
||||||
|
struct ethtool_regs *regs, void *space)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
u32 *reg_space = (u32 *) space;
|
||||||
|
|
||||||
|
struct stmmac_priv *priv = netdev_priv(dev);
|
||||||
|
|
||||||
|
memset(reg_space, 0x0, REG_SPACE_SIZE);
|
||||||
|
|
||||||
|
if (!priv->is_gmac) {
|
||||||
|
/* MAC registers */
|
||||||
|
for (i = 0; i < 12; i++)
|
||||||
|
reg_space[i] = readl(dev->base_addr + (i * 4));
|
||||||
|
/* DMA registers */
|
||||||
|
for (i = 0; i < 9; i++)
|
||||||
|
reg_space[i + 12] =
|
||||||
|
readl(dev->base_addr + (DMA_BUS_MODE + (i * 4)));
|
||||||
|
reg_space[22] = readl(dev->base_addr + DMA_CUR_TX_BUF_ADDR);
|
||||||
|
reg_space[23] = readl(dev->base_addr + DMA_CUR_RX_BUF_ADDR);
|
||||||
|
} else {
|
||||||
|
/* MAC registers */
|
||||||
|
for (i = 0; i < 55; i++)
|
||||||
|
reg_space[i] = readl(dev->base_addr + (i * 4));
|
||||||
|
/* DMA registers */
|
||||||
|
for (i = 0; i < 22; i++)
|
||||||
|
reg_space[i + 55] =
|
||||||
|
readl(dev->base_addr + (DMA_BUS_MODE + (i * 4)));
|
||||||
|
}
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
int stmmac_ethtool_set_tx_csum(struct net_device *netdev, u32 data)
|
||||||
|
{
|
||||||
|
if (data)
|
||||||
|
netdev->features |= NETIF_F_HW_CSUM;
|
||||||
|
else
|
||||||
|
netdev->features &= ~NETIF_F_HW_CSUM;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 stmmac_ethtool_get_rx_csum(struct net_device *dev)
|
||||||
|
{
|
||||||
|
struct stmmac_priv *priv = netdev_priv(dev);
|
||||||
|
|
||||||
|
return priv->rx_csum;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
stmmac_get_pauseparam(struct net_device *netdev,
|
||||||
|
struct ethtool_pauseparam *pause)
|
||||||
|
{
|
||||||
|
struct stmmac_priv *priv = netdev_priv(netdev);
|
||||||
|
|
||||||
|
spin_lock(&priv->lock);
|
||||||
|
|
||||||
|
pause->rx_pause = 0;
|
||||||
|
pause->tx_pause = 0;
|
||||||
|
pause->autoneg = priv->phydev->autoneg;
|
||||||
|
|
||||||
|
if (priv->flow_ctrl & FLOW_RX)
|
||||||
|
pause->rx_pause = 1;
|
||||||
|
if (priv->flow_ctrl & FLOW_TX)
|
||||||
|
pause->tx_pause = 1;
|
||||||
|
|
||||||
|
spin_unlock(&priv->lock);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int
|
||||||
|
stmmac_set_pauseparam(struct net_device *netdev,
|
||||||
|
struct ethtool_pauseparam *pause)
|
||||||
|
{
|
||||||
|
struct stmmac_priv *priv = netdev_priv(netdev);
|
||||||
|
struct phy_device *phy = priv->phydev;
|
||||||
|
int new_pause = FLOW_OFF;
|
||||||
|
int ret = 0;
|
||||||
|
|
||||||
|
spin_lock(&priv->lock);
|
||||||
|
|
||||||
|
if (pause->rx_pause)
|
||||||
|
new_pause |= FLOW_RX;
|
||||||
|
if (pause->tx_pause)
|
||||||
|
new_pause |= FLOW_TX;
|
||||||
|
|
||||||
|
priv->flow_ctrl = new_pause;
|
||||||
|
|
||||||
|
if (phy->autoneg) {
|
||||||
|
if (netif_running(netdev)) {
|
||||||
|
struct ethtool_cmd cmd;
|
||||||
|
/* auto-negotiation automatically restarted */
|
||||||
|
cmd.cmd = ETHTOOL_NWAY_RST;
|
||||||
|
cmd.supported = phy->supported;
|
||||||
|
cmd.advertising = phy->advertising;
|
||||||
|
cmd.autoneg = phy->autoneg;
|
||||||
|
cmd.speed = phy->speed;
|
||||||
|
cmd.duplex = phy->duplex;
|
||||||
|
cmd.phy_address = phy->addr;
|
||||||
|
ret = phy_ethtool_sset(phy, &cmd);
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
unsigned long ioaddr = netdev->base_addr;
|
||||||
|
priv->mac_type->ops->flow_ctrl(ioaddr, phy->duplex,
|
||||||
|
priv->flow_ctrl, priv->pause);
|
||||||
|
}
|
||||||
|
spin_unlock(&priv->lock);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void stmmac_get_ethtool_stats(struct net_device *dev,
|
||||||
|
struct ethtool_stats *dummy, u64 *data)
|
||||||
|
{
|
||||||
|
struct stmmac_priv *priv = netdev_priv(dev);
|
||||||
|
unsigned long ioaddr = dev->base_addr;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
/* Update HW stats if supported */
|
||||||
|
priv->mac_type->ops->dma_diagnostic_fr(&dev->stats, &priv->xstats,
|
||||||
|
ioaddr);
|
||||||
|
|
||||||
|
for (i = 0; i < STMMAC_STATS_LEN; i++) {
|
||||||
|
char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset;
|
||||||
|
data[i] = (stmmac_gstrings_stats[i].sizeof_stat ==
|
||||||
|
sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p);
|
||||||
|
}
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int stmmac_get_sset_count(struct net_device *netdev, int sset)
|
||||||
|
{
|
||||||
|
switch (sset) {
|
||||||
|
case ETH_SS_STATS:
|
||||||
|
return STMMAC_STATS_LEN;
|
||||||
|
default:
|
||||||
|
return -EOPNOTSUPP;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
u8 *p = data;
|
||||||
|
|
||||||
|
switch (stringset) {
|
||||||
|
case ETH_SS_STATS:
|
||||||
|
for (i = 0; i < STMMAC_STATS_LEN; i++) {
|
||||||
|
memcpy(p, stmmac_gstrings_stats[i].stat_string,
|
||||||
|
ETH_GSTRING_LEN);
|
||||||
|
p += ETH_GSTRING_LEN;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
WARN_ON(1);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Currently only support WOL through Magic packet. */
|
||||||
|
static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
|
||||||
|
{
|
||||||
|
struct stmmac_priv *priv = netdev_priv(dev);
|
||||||
|
|
||||||
|
spin_lock_irq(&priv->lock);
|
||||||
|
if (priv->wolenabled == PMT_SUPPORTED) {
|
||||||
|
wol->supported = WAKE_MAGIC;
|
||||||
|
wol->wolopts = priv->wolopts;
|
||||||
|
}
|
||||||
|
spin_unlock_irq(&priv->lock);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
|
||||||
|
{
|
||||||
|
struct stmmac_priv *priv = netdev_priv(dev);
|
||||||
|
u32 support = WAKE_MAGIC;
|
||||||
|
|
||||||
|
if (priv->wolenabled == PMT_NOT_SUPPORTED)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
if (wol->wolopts & ~support)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
if (wol->wolopts == 0)
|
||||||
|
device_set_wakeup_enable(priv->device, 0);
|
||||||
|
else
|
||||||
|
device_set_wakeup_enable(priv->device, 1);
|
||||||
|
|
||||||
|
spin_lock_irq(&priv->lock);
|
||||||
|
priv->wolopts = wol->wolopts;
|
||||||
|
spin_unlock_irq(&priv->lock);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct ethtool_ops stmmac_ethtool_ops = {
|
||||||
|
.begin = stmmac_check_if_running,
|
||||||
|
.get_drvinfo = stmmac_ethtool_getdrvinfo,
|
||||||
|
.get_settings = stmmac_ethtool_getsettings,
|
||||||
|
.set_settings = stmmac_ethtool_setsettings,
|
||||||
|
.get_msglevel = stmmac_ethtool_getmsglevel,
|
||||||
|
.set_msglevel = stmmac_ethtool_setmsglevel,
|
||||||
|
.get_regs = stmmac_ethtool_gregs,
|
||||||
|
.get_regs_len = stmmac_ethtool_get_regs_len,
|
||||||
|
.get_link = ethtool_op_get_link,
|
||||||
|
.get_rx_csum = stmmac_ethtool_get_rx_csum,
|
||||||
|
.get_tx_csum = ethtool_op_get_tx_csum,
|
||||||
|
.set_tx_csum = stmmac_ethtool_set_tx_csum,
|
||||||
|
.get_sg = ethtool_op_get_sg,
|
||||||
|
.set_sg = ethtool_op_set_sg,
|
||||||
|
.get_pauseparam = stmmac_get_pauseparam,
|
||||||
|
.set_pauseparam = stmmac_set_pauseparam,
|
||||||
|
.get_ethtool_stats = stmmac_get_ethtool_stats,
|
||||||
|
.get_strings = stmmac_get_strings,
|
||||||
|
.get_wol = stmmac_get_wol,
|
||||||
|
.set_wol = stmmac_set_wol,
|
||||||
|
.get_sset_count = stmmac_get_sset_count,
|
||||||
|
#ifdef NETIF_F_TSO
|
||||||
|
.get_tso = ethtool_op_get_tso,
|
||||||
|
.set_tso = ethtool_op_set_tso,
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
void stmmac_set_ethtool_ops(struct net_device *netdev)
|
||||||
|
{
|
||||||
|
SET_ETHTOOL_OPS(netdev, &stmmac_ethtool_ops);
|
||||||
|
}
|
2204
drivers/net/stmmac/stmmac_main.c
Normal file
2204
drivers/net/stmmac/stmmac_main.c
Normal file
File diff suppressed because it is too large
Load diff
217
drivers/net/stmmac/stmmac_mdio.c
Normal file
217
drivers/net/stmmac/stmmac_mdio.c
Normal file
|
@ -0,0 +1,217 @@
|
||||||
|
/*******************************************************************************
|
||||||
|
STMMAC Ethernet Driver -- MDIO bus implementation
|
||||||
|
Provides Bus interface for MII registers
|
||||||
|
|
||||||
|
Copyright (C) 2007-2009 STMicroelectronics Ltd
|
||||||
|
|
||||||
|
This program is free software; you can redistribute it and/or modify it
|
||||||
|
under the terms and conditions of the GNU General Public License,
|
||||||
|
version 2, as published by the Free Software Foundation.
|
||||||
|
|
||||||
|
This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License along with
|
||||||
|
this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||||
|
|
||||||
|
The full GNU General Public License is included in this distribution in
|
||||||
|
the file called "COPYING".
|
||||||
|
|
||||||
|
Author: Carl Shaw <carl.shaw@st.com>
|
||||||
|
Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
#include <linux/netdevice.h>
|
||||||
|
#include <linux/mii.h>
|
||||||
|
#include <linux/phy.h>
|
||||||
|
|
||||||
|
#include "stmmac.h"
|
||||||
|
|
||||||
|
#define MII_BUSY 0x00000001
|
||||||
|
#define MII_WRITE 0x00000002
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stmmac_mdio_read
|
||||||
|
* @bus: points to the mii_bus structure
|
||||||
|
* @phyaddr: MII addr reg bits 15-11
|
||||||
|
* @phyreg: MII addr reg bits 10-6
|
||||||
|
* Description: it reads data from the MII register from within the phy device.
|
||||||
|
* For the 7111 GMAC, we must set the bit 0 in the MII address register while
|
||||||
|
* accessing the PHY registers.
|
||||||
|
* Fortunately, it seems this has no drawback for the 7109 MAC.
|
||||||
|
*/
|
||||||
|
static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
|
||||||
|
{
|
||||||
|
struct net_device *ndev = bus->priv;
|
||||||
|
struct stmmac_priv *priv = netdev_priv(ndev);
|
||||||
|
unsigned long ioaddr = ndev->base_addr;
|
||||||
|
unsigned int mii_address = priv->mac_type->hw.mii.addr;
|
||||||
|
unsigned int mii_data = priv->mac_type->hw.mii.data;
|
||||||
|
|
||||||
|
int data;
|
||||||
|
u16 regValue = (((phyaddr << 11) & (0x0000F800)) |
|
||||||
|
((phyreg << 6) & (0x000007C0)));
|
||||||
|
regValue |= MII_BUSY; /* in case of GMAC */
|
||||||
|
|
||||||
|
do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);
|
||||||
|
writel(regValue, ioaddr + mii_address);
|
||||||
|
do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);
|
||||||
|
|
||||||
|
/* Read the data from the MII data register */
|
||||||
|
data = (int)readl(ioaddr + mii_data);
|
||||||
|
|
||||||
|
return data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stmmac_mdio_write
|
||||||
|
* @bus: points to the mii_bus structure
|
||||||
|
* @phyaddr: MII addr reg bits 15-11
|
||||||
|
* @phyreg: MII addr reg bits 10-6
|
||||||
|
* @phydata: phy data
|
||||||
|
* Description: it writes the data into the MII register from within the device.
|
||||||
|
*/
|
||||||
|
static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
|
||||||
|
u16 phydata)
|
||||||
|
{
|
||||||
|
struct net_device *ndev = bus->priv;
|
||||||
|
struct stmmac_priv *priv = netdev_priv(ndev);
|
||||||
|
unsigned long ioaddr = ndev->base_addr;
|
||||||
|
unsigned int mii_address = priv->mac_type->hw.mii.addr;
|
||||||
|
unsigned int mii_data = priv->mac_type->hw.mii.data;
|
||||||
|
|
||||||
|
u16 value =
|
||||||
|
(((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0)))
|
||||||
|
| MII_WRITE;
|
||||||
|
|
||||||
|
value |= MII_BUSY;
|
||||||
|
|
||||||
|
/* Wait until any existing MII operation is complete */
|
||||||
|
do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);
|
||||||
|
|
||||||
|
/* Set the MII address register to write */
|
||||||
|
writel(phydata, ioaddr + mii_data);
|
||||||
|
writel(value, ioaddr + mii_address);
|
||||||
|
|
||||||
|
/* Wait until any existing MII operation is complete */
|
||||||
|
do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stmmac_mdio_reset
|
||||||
|
* @bus: points to the mii_bus structure
|
||||||
|
* Description: reset the MII bus
|
||||||
|
*/
|
||||||
|
static int stmmac_mdio_reset(struct mii_bus *bus)
|
||||||
|
{
|
||||||
|
struct net_device *ndev = bus->priv;
|
||||||
|
struct stmmac_priv *priv = netdev_priv(ndev);
|
||||||
|
unsigned long ioaddr = ndev->base_addr;
|
||||||
|
unsigned int mii_address = priv->mac_type->hw.mii.addr;
|
||||||
|
|
||||||
|
if (priv->phy_reset) {
|
||||||
|
pr_debug("stmmac_mdio_reset: calling phy_reset\n");
|
||||||
|
priv->phy_reset(priv->bsp_priv);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* This is a workaround for problems with the STE101P PHY.
|
||||||
|
* It doesn't complete its reset until at least one clock cycle
|
||||||
|
* on MDC, so perform a dummy mdio read.
|
||||||
|
*/
|
||||||
|
writel(0, ioaddr + mii_address);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stmmac_mdio_register
|
||||||
|
* @ndev: net device structure
|
||||||
|
* Description: it registers the MII bus
|
||||||
|
*/
|
||||||
|
int stmmac_mdio_register(struct net_device *ndev)
|
||||||
|
{
|
||||||
|
int err = 0;
|
||||||
|
struct mii_bus *new_bus;
|
||||||
|
int *irqlist;
|
||||||
|
struct stmmac_priv *priv = netdev_priv(ndev);
|
||||||
|
int addr, found;
|
||||||
|
|
||||||
|
new_bus = mdiobus_alloc();
|
||||||
|
if (new_bus == NULL)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
irqlist = kzalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
|
||||||
|
if (irqlist == NULL) {
|
||||||
|
err = -ENOMEM;
|
||||||
|
goto irqlist_alloc_fail;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Assign IRQ to phy at address phy_addr */
|
||||||
|
if (priv->phy_addr != -1)
|
||||||
|
irqlist[priv->phy_addr] = priv->phy_irq;
|
||||||
|
|
||||||
|
new_bus->name = "STMMAC MII Bus";
|
||||||
|
new_bus->read = &stmmac_mdio_read;
|
||||||
|
new_bus->write = &stmmac_mdio_write;
|
||||||
|
new_bus->reset = &stmmac_mdio_reset;
|
||||||
|
snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", priv->bus_id);
|
||||||
|
new_bus->priv = ndev;
|
||||||
|
new_bus->irq = irqlist;
|
||||||
|
new_bus->phy_mask = priv->phy_mask;
|
||||||
|
new_bus->parent = priv->device;
|
||||||
|
err = mdiobus_register(new_bus);
|
||||||
|
if (err != 0) {
|
||||||
|
pr_err("%s: Cannot register as MDIO bus\n", new_bus->name);
|
||||||
|
goto bus_register_fail;
|
||||||
|
}
|
||||||
|
|
||||||
|
priv->mii = new_bus;
|
||||||
|
|
||||||
|
found = 0;
|
||||||
|
for (addr = 0; addr < 32; addr++) {
|
||||||
|
struct phy_device *phydev = new_bus->phy_map[addr];
|
||||||
|
if (phydev) {
|
||||||
|
if (priv->phy_addr == -1) {
|
||||||
|
priv->phy_addr = addr;
|
||||||
|
phydev->irq = priv->phy_irq;
|
||||||
|
irqlist[addr] = priv->phy_irq;
|
||||||
|
}
|
||||||
|
pr_info("%s: PHY ID %08x at %d IRQ %d (%s)%s\n",
|
||||||
|
ndev->name, phydev->phy_id, addr,
|
||||||
|
phydev->irq, dev_name(&phydev->dev),
|
||||||
|
(addr == priv->phy_addr) ? " active" : "");
|
||||||
|
found = 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!found)
|
||||||
|
pr_warning("%s: No PHY found\n", ndev->name);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
bus_register_fail:
|
||||||
|
kfree(irqlist);
|
||||||
|
irqlist_alloc_fail:
|
||||||
|
kfree(new_bus);
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stmmac_mdio_unregister
|
||||||
|
* @ndev: net device structure
|
||||||
|
* Description: it unregisters the MII bus
|
||||||
|
*/
|
||||||
|
int stmmac_mdio_unregister(struct net_device *ndev)
|
||||||
|
{
|
||||||
|
struct stmmac_priv *priv = netdev_priv(ndev);
|
||||||
|
|
||||||
|
mdiobus_unregister(priv->mii);
|
||||||
|
priv->mii->priv = NULL;
|
||||||
|
kfree(priv->mii);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
140
drivers/net/stmmac/stmmac_timer.c
Normal file
140
drivers/net/stmmac/stmmac_timer.c
Normal file
|
@ -0,0 +1,140 @@
|
||||||
|
/*******************************************************************************
|
||||||
|
STMMAC external timer support.
|
||||||
|
|
||||||
|
Copyright (C) 2007-2009 STMicroelectronics Ltd
|
||||||
|
|
||||||
|
This program is free software; you can redistribute it and/or modify it
|
||||||
|
under the terms and conditions of the GNU General Public License,
|
||||||
|
version 2, as published by the Free Software Foundation.
|
||||||
|
|
||||||
|
This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License along with
|
||||||
|
this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||||
|
|
||||||
|
The full GNU General Public License is included in this distribution in
|
||||||
|
the file called "COPYING".
|
||||||
|
|
||||||
|
Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
#include <linux/etherdevice.h>
|
||||||
|
#include "stmmac_timer.h"
|
||||||
|
|
||||||
|
static void stmmac_timer_handler(void *data)
|
||||||
|
{
|
||||||
|
struct net_device *dev = (struct net_device *)data;
|
||||||
|
|
||||||
|
stmmac_schedule(dev);
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
#define STMMAC_TIMER_MSG(timer, freq) \
|
||||||
|
printk(KERN_INFO "stmmac_timer: %s Timer ON (freq %dHz)\n", timer, freq);
|
||||||
|
|
||||||
|
#if defined(CONFIG_STMMAC_RTC_TIMER)
|
||||||
|
#include <linux/rtc.h>
|
||||||
|
static struct rtc_device *stmmac_rtc;
|
||||||
|
static rtc_task_t stmmac_task;
|
||||||
|
|
||||||
|
static void stmmac_rtc_start(unsigned int new_freq)
|
||||||
|
{
|
||||||
|
rtc_irq_set_freq(stmmac_rtc, &stmmac_task, new_freq);
|
||||||
|
rtc_irq_set_state(stmmac_rtc, &stmmac_task, 1);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void stmmac_rtc_stop(void)
|
||||||
|
{
|
||||||
|
rtc_irq_set_state(stmmac_rtc, &stmmac_task, 0);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
int stmmac_open_ext_timer(struct net_device *dev, struct stmmac_timer *tm)
|
||||||
|
{
|
||||||
|
stmmac_task.private_data = dev;
|
||||||
|
stmmac_task.func = stmmac_timer_handler;
|
||||||
|
|
||||||
|
stmmac_rtc = rtc_class_open(CONFIG_RTC_HCTOSYS_DEVICE);
|
||||||
|
if (stmmac_rtc == NULL) {
|
||||||
|
pr_error("open rtc device failed\n");
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
|
||||||
|
rtc_irq_register(stmmac_rtc, &stmmac_task);
|
||||||
|
|
||||||
|
/* Periodic mode is not supported */
|
||||||
|
if ((rtc_irq_set_freq(stmmac_rtc, &stmmac_task, tm->freq) < 0)) {
|
||||||
|
pr_error("set periodic failed\n");
|
||||||
|
rtc_irq_unregister(stmmac_rtc, &stmmac_task);
|
||||||
|
rtc_class_close(stmmac_rtc);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
STMMAC_TIMER_MSG(CONFIG_RTC_HCTOSYS_DEVICE, tm->freq);
|
||||||
|
|
||||||
|
tm->timer_start = stmmac_rtc_start;
|
||||||
|
tm->timer_stop = stmmac_rtc_stop;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int stmmac_close_ext_timer(void)
|
||||||
|
{
|
||||||
|
rtc_irq_set_state(stmmac_rtc, &stmmac_task, 0);
|
||||||
|
rtc_irq_unregister(stmmac_rtc, &stmmac_task);
|
||||||
|
rtc_class_close(stmmac_rtc);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#elif defined(CONFIG_STMMAC_TMU_TIMER)
|
||||||
|
#include <linux/clk.h>
|
||||||
|
#define TMU_CHANNEL "tmu2_clk"
|
||||||
|
static struct clk *timer_clock;
|
||||||
|
|
||||||
|
static void stmmac_tmu_start(unsigned int new_freq)
|
||||||
|
{
|
||||||
|
clk_set_rate(timer_clock, new_freq);
|
||||||
|
clk_enable(timer_clock);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void stmmac_tmu_stop(void)
|
||||||
|
{
|
||||||
|
clk_disable(timer_clock);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
int stmmac_open_ext_timer(struct net_device *dev, struct stmmac_timer *tm)
|
||||||
|
{
|
||||||
|
timer_clock = clk_get(NULL, TMU_CHANNEL);
|
||||||
|
|
||||||
|
if (timer_clock == NULL)
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
if (tmu2_register_user(stmmac_timer_handler, (void *)dev) < 0) {
|
||||||
|
timer_clock = NULL;
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
STMMAC_TIMER_MSG("TMU2", tm->freq);
|
||||||
|
tm->timer_start = stmmac_tmu_start;
|
||||||
|
tm->timer_stop = stmmac_tmu_stop;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int stmmac_close_ext_timer(void)
|
||||||
|
{
|
||||||
|
clk_disable(timer_clock);
|
||||||
|
tmu2_unregister_user();
|
||||||
|
clk_put(timer_clock);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif
|
41
drivers/net/stmmac/stmmac_timer.h
Normal file
41
drivers/net/stmmac/stmmac_timer.h
Normal file
|
@ -0,0 +1,41 @@
|
||||||
|
/*******************************************************************************
|
||||||
|
STMMAC external timer Header File.
|
||||||
|
|
||||||
|
Copyright (C) 2007-2009 STMicroelectronics Ltd
|
||||||
|
|
||||||
|
This program is free software; you can redistribute it and/or modify it
|
||||||
|
under the terms and conditions of the GNU General Public License,
|
||||||
|
version 2, as published by the Free Software Foundation.
|
||||||
|
|
||||||
|
This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License along with
|
||||||
|
this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||||
|
|
||||||
|
The full GNU General Public License is included in this distribution in
|
||||||
|
the file called "COPYING".
|
||||||
|
|
||||||
|
Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
struct stmmac_timer {
|
||||||
|
void (*timer_start) (unsigned int new_freq);
|
||||||
|
void (*timer_stop) (void);
|
||||||
|
unsigned int freq;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Open the HW timer device and return 0 in case of success */
|
||||||
|
int stmmac_open_ext_timer(struct net_device *dev, struct stmmac_timer *tm);
|
||||||
|
/* Stop the timer and release it */
|
||||||
|
int stmmac_close_ext_timer(void);
|
||||||
|
/* Function used for scheduling task within the stmmac */
|
||||||
|
void stmmac_schedule(struct net_device *dev);
|
||||||
|
|
||||||
|
#if defined(CONFIG_STMMAC_TMU_TIMER)
|
||||||
|
extern int tmu2_register_user(void *fnt, void *data);
|
||||||
|
extern void tmu2_unregister_user(void);
|
||||||
|
#endif
|
|
@ -62,8 +62,11 @@ static char *devid=NULL;
|
||||||
static struct usb_eth_dev usb_dev_id[] = {
|
static struct usb_eth_dev usb_dev_id[] = {
|
||||||
#define PEGASUS_DEV(pn, vid, pid, flags) \
|
#define PEGASUS_DEV(pn, vid, pid, flags) \
|
||||||
{.name = pn, .vendor = vid, .device = pid, .private = flags},
|
{.name = pn, .vendor = vid, .device = pid, .private = flags},
|
||||||
|
#define PEGASUS_DEV_CLASS(pn, vid, pid, dclass, flags) \
|
||||||
|
PEGASUS_DEV(pn, vid, pid, flags)
|
||||||
#include "pegasus.h"
|
#include "pegasus.h"
|
||||||
#undef PEGASUS_DEV
|
#undef PEGASUS_DEV
|
||||||
|
#undef PEGASUS_DEV_CLASS
|
||||||
{NULL, 0, 0, 0},
|
{NULL, 0, 0, 0},
|
||||||
{NULL, 0, 0, 0}
|
{NULL, 0, 0, 0}
|
||||||
};
|
};
|
||||||
|
@ -71,8 +74,18 @@ static struct usb_eth_dev usb_dev_id[] = {
|
||||||
static struct usb_device_id pegasus_ids[] = {
|
static struct usb_device_id pegasus_ids[] = {
|
||||||
#define PEGASUS_DEV(pn, vid, pid, flags) \
|
#define PEGASUS_DEV(pn, vid, pid, flags) \
|
||||||
{.match_flags = USB_DEVICE_ID_MATCH_DEVICE, .idVendor = vid, .idProduct = pid},
|
{.match_flags = USB_DEVICE_ID_MATCH_DEVICE, .idVendor = vid, .idProduct = pid},
|
||||||
|
/*
|
||||||
|
* The Belkin F8T012xx1 bluetooth adaptor has the same vendor and product
|
||||||
|
* IDs as the Belkin F5D5050, so we need to teach the pegasus driver to
|
||||||
|
* ignore adaptors belonging to the "Wireless" class 0xE0. For this one
|
||||||
|
* case anyway, seeing as the pegasus is for "Wired" adaptors.
|
||||||
|
*/
|
||||||
|
#define PEGASUS_DEV_CLASS(pn, vid, pid, dclass, flags) \
|
||||||
|
{.match_flags = (USB_DEVICE_ID_MATCH_DEVICE | USB_DEVICE_ID_MATCH_DEV_CLASS), \
|
||||||
|
.idVendor = vid, .idProduct = pid, .bDeviceClass = dclass},
|
||||||
#include "pegasus.h"
|
#include "pegasus.h"
|
||||||
#undef PEGASUS_DEV
|
#undef PEGASUS_DEV
|
||||||
|
#undef PEGASUS_DEV_CLASS
|
||||||
{},
|
{},
|
||||||
{}
|
{}
|
||||||
};
|
};
|
||||||
|
|
|
@ -202,7 +202,11 @@ PEGASUS_DEV( "AEI USB Fast Ethernet Adapter", VENDOR_AEILAB, 0x1701,
|
||||||
DEFAULT_GPIO_RESET | PEGASUS_II )
|
DEFAULT_GPIO_RESET | PEGASUS_II )
|
||||||
PEGASUS_DEV( "Allied Telesyn Int. AT-USB100", VENDOR_ALLIEDTEL, 0xb100,
|
PEGASUS_DEV( "Allied Telesyn Int. AT-USB100", VENDOR_ALLIEDTEL, 0xb100,
|
||||||
DEFAULT_GPIO_RESET | PEGASUS_II )
|
DEFAULT_GPIO_RESET | PEGASUS_II )
|
||||||
PEGASUS_DEV( "Belkin F5D5050 USB Ethernet", VENDOR_BELKIN, 0x0121,
|
/*
|
||||||
|
* Distinguish between this Belkin adaptor and the Belkin bluetooth adaptors
|
||||||
|
* with the same product IDs by checking the device class too.
|
||||||
|
*/
|
||||||
|
PEGASUS_DEV_CLASS( "Belkin F5D5050 USB Ethernet", VENDOR_BELKIN, 0x0121, 0x00,
|
||||||
DEFAULT_GPIO_RESET | PEGASUS_II )
|
DEFAULT_GPIO_RESET | PEGASUS_II )
|
||||||
PEGASUS_DEV( "Billionton USB-100", VENDOR_BILLIONTON, 0x0986,
|
PEGASUS_DEV( "Billionton USB-100", VENDOR_BILLIONTON, 0x0986,
|
||||||
DEFAULT_GPIO_RESET )
|
DEFAULT_GPIO_RESET )
|
||||||
|
|
35
drivers/net/vmxnet3/Makefile
Normal file
35
drivers/net/vmxnet3/Makefile
Normal file
|
@ -0,0 +1,35 @@
|
||||||
|
################################################################################
|
||||||
|
#
|
||||||
|
# Linux driver for VMware's vmxnet3 ethernet NIC.
|
||||||
|
#
|
||||||
|
# Copyright (C) 2007-2009, VMware, Inc. All Rights Reserved.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or modify it
|
||||||
|
# under the terms of the GNU General Public License as published by the
|
||||||
|
# Free Software Foundation; version 2 of the License and no later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful, but
|
||||||
|
# WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||||
|
# NON INFRINGEMENT. See the GNU General Public License for more
|
||||||
|
# details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||||
|
#
|
||||||
|
# The full GNU General Public License is included in this distribution in
|
||||||
|
# the file called "COPYING".
|
||||||
|
#
|
||||||
|
# Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
|
||||||
|
#
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
#
|
||||||
|
# Makefile for the VMware vmxnet3 ethernet NIC driver
|
||||||
|
#
|
||||||
|
|
||||||
|
obj-$(CONFIG_VMXNET3) += vmxnet3.o
|
||||||
|
|
||||||
|
vmxnet3-objs := vmxnet3_drv.o vmxnet3_ethtool.o
|
96
drivers/net/vmxnet3/upt1_defs.h
Normal file
96
drivers/net/vmxnet3/upt1_defs.h
Normal file
|
@ -0,0 +1,96 @@
|
||||||
|
/*
|
||||||
|
* Linux driver for VMware's vmxnet3 ethernet NIC.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms of the GNU General Public License as published by the
|
||||||
|
* Free Software Foundation; version 2 of the License and no later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful, but
|
||||||
|
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||||
|
* NON INFRINGEMENT. See the GNU General Public License for more
|
||||||
|
* details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||||
|
*
|
||||||
|
* The full GNU General Public License is included in this distribution in
|
||||||
|
* the file called "COPYING".
|
||||||
|
*
|
||||||
|
* Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _UPT1_DEFS_H
|
||||||
|
#define _UPT1_DEFS_H
|
||||||
|
|
||||||
|
struct UPT1_TxStats {
|
||||||
|
u64 TSOPktsTxOK; /* TSO pkts post-segmentation */
|
||||||
|
u64 TSOBytesTxOK;
|
||||||
|
u64 ucastPktsTxOK;
|
||||||
|
u64 ucastBytesTxOK;
|
||||||
|
u64 mcastPktsTxOK;
|
||||||
|
u64 mcastBytesTxOK;
|
||||||
|
u64 bcastPktsTxOK;
|
||||||
|
u64 bcastBytesTxOK;
|
||||||
|
u64 pktsTxError;
|
||||||
|
u64 pktsTxDiscard;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct UPT1_RxStats {
|
||||||
|
u64 LROPktsRxOK; /* LRO pkts */
|
||||||
|
u64 LROBytesRxOK; /* bytes from LRO pkts */
|
||||||
|
/* the following counters are for pkts from the wire, i.e., pre-LRO */
|
||||||
|
u64 ucastPktsRxOK;
|
||||||
|
u64 ucastBytesRxOK;
|
||||||
|
u64 mcastPktsRxOK;
|
||||||
|
u64 mcastBytesRxOK;
|
||||||
|
u64 bcastPktsRxOK;
|
||||||
|
u64 bcastBytesRxOK;
|
||||||
|
u64 pktsRxOutOfBuf;
|
||||||
|
u64 pktsRxError;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* interrupt moderation level */
|
||||||
|
enum {
|
||||||
|
UPT1_IML_NONE = 0, /* no interrupt moderation */
|
||||||
|
UPT1_IML_HIGHEST = 7, /* least intr generated */
|
||||||
|
UPT1_IML_ADAPTIVE = 8, /* adpative intr moderation */
|
||||||
|
};
|
||||||
|
/* values for UPT1_RSSConf.hashFunc */
|
||||||
|
enum {
|
||||||
|
UPT1_RSS_HASH_TYPE_NONE = 0x0,
|
||||||
|
UPT1_RSS_HASH_TYPE_IPV4 = 0x01,
|
||||||
|
UPT1_RSS_HASH_TYPE_TCP_IPV4 = 0x02,
|
||||||
|
UPT1_RSS_HASH_TYPE_IPV6 = 0x04,
|
||||||
|
UPT1_RSS_HASH_TYPE_TCP_IPV6 = 0x08,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
UPT1_RSS_HASH_FUNC_NONE = 0x0,
|
||||||
|
UPT1_RSS_HASH_FUNC_TOEPLITZ = 0x01,
|
||||||
|
};
|
||||||
|
|
||||||
|
#define UPT1_RSS_MAX_KEY_SIZE 40
|
||||||
|
#define UPT1_RSS_MAX_IND_TABLE_SIZE 128
|
||||||
|
|
||||||
|
struct UPT1_RSSConf {
|
||||||
|
u16 hashType;
|
||||||
|
u16 hashFunc;
|
||||||
|
u16 hashKeySize;
|
||||||
|
u16 indTableSize;
|
||||||
|
u8 hashKey[UPT1_RSS_MAX_KEY_SIZE];
|
||||||
|
u8 indTable[UPT1_RSS_MAX_IND_TABLE_SIZE];
|
||||||
|
};
|
||||||
|
|
||||||
|
/* features */
|
||||||
|
enum {
|
||||||
|
UPT1_F_RXCSUM = 0x0001, /* rx csum verification */
|
||||||
|
UPT1_F_RSS = 0x0002,
|
||||||
|
UPT1_F_RXVLAN = 0x0004, /* VLAN tag stripping */
|
||||||
|
UPT1_F_LRO = 0x0008,
|
||||||
|
};
|
||||||
|
#endif
|
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue