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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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pinctrl: renesas: Updates for v5.14
- Minor fixes and improvements. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYLCs2AAKCRCKwlD9ZEnx cN7BAP9J+MuYE/rU9gsqrNscKUhtKlTcWIDcxBVFwnCCu3Y+XAEAtEYQI7I18LqH DF2Uq8WX+u9MBYoKT2wWiqv1RWkp4wY= =SkB4 -----END PGP SIGNATURE----- Merge tag 'renesas-pinctrl-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.14 - Minor fixes and improvements.
This commit is contained in:
Linus Walleij
commit
50bdc4d441
5 changed files with 56 additions and 56 deletions
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@ -18,9 +18,6 @@
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#include "sh_pfc.h"
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#define PORT_GP_PUP_1(bank, pin, fn, sfx) \
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PORT_GP_CFG_1(bank, pin, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
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#define CPU_ALL_GP(fn, sfx) \
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PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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@ -241,7 +241,7 @@
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#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
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#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
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#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
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#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
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#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
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/* GPSR7 */
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#define GPSR7_3 FM(GP7_03)
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@ -668,7 +668,7 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
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PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
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PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
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PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
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PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
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PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
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PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
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@ -67,6 +67,7 @@
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PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(PRESET_N, "PRESET#", fn, SH_PFC_PIN_CFG_PULL_DOWN),\
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PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
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@ -1548,7 +1549,7 @@ static const u16 pinmux_data[] = {
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* core will do the right thing and skip trying to mux the pin
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* while still applying configuration to it.
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*/
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#define FM(x) PINMUX_DATA(x##_MARK, 0),
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#define FM(x) PINMUX_DATA(x##_MARK, 0),
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PINMUX_STATIC
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#undef FM
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};
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@ -4233,7 +4234,7 @@ static const struct {
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SH_PFC_PIN_GROUP(avb_link),
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SH_PFC_PIN_GROUP(avb_magic),
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SH_PFC_PIN_GROUP(avb_phy_int),
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SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
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SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
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SH_PFC_PIN_GROUP(avb_mdio),
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SH_PFC_PIN_GROUP(avb_mii),
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SH_PFC_PIN_GROUP(avb_avtp_pps),
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@ -5990,7 +5991,8 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
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{ /* sentinel */ },
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};
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static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
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static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc,
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unsigned int pin, u32 *pocctrl)
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{
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int bit = -EINVAL;
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@ -6218,7 +6220,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
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[ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
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[ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
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[ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
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[ 7] = SH_PFC_PIN_NONE,
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[ 7] = PIN_PRESET_N, /* PRESET# */
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[ 8] = SH_PFC_PIN_NONE,
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[ 9] = SH_PFC_PIN_NONE,
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[10] = SH_PFC_PIN_NONE,
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@ -666,14 +666,14 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
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PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
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PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
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PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
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PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
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PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
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PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
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PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
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PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
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PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
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PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
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PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
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PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
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PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
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PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
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PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
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PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
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@ -727,16 +727,16 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
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PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
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PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
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PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
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PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
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PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
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PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
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PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
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PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
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PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
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PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
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PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
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PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
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PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
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PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
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PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
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PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
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PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
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PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
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PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
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PINMUX_IPSR_GPSR(IP1_31_28, A0),
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PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
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@ -1171,13 +1171,13 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
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PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
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PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
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PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
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PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
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PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
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PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
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PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
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PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
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PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
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PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
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PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
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PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
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PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
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@ -1553,7 +1553,7 @@ static const u16 pinmux_data[] = {
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* core will do the right thing and skip trying to mux the pin
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* while still applying configuration to it.
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*/
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#define FM(x) PINMUX_DATA(x##_MARK, 0),
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#define FM(x) PINMUX_DATA(x##_MARK, 0),
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PINMUX_STATIC
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#undef FM
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};
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@ -4224,24 +4224,24 @@ static const unsigned int vin4_data18_a_pins[] = {
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RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
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RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
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RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
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RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
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RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
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RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
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RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
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RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
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RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
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RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
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RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
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RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
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RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
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RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
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RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
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};
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static const unsigned int vin4_data18_a_mux[] = {
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VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
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VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
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VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
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VI4_DATA10_MARK, VI4_DATA11_MARK,
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VI4_DATA12_MARK, VI4_DATA13_MARK,
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VI4_DATA14_MARK, VI4_DATA15_MARK,
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VI4_DATA18_MARK, VI4_DATA19_MARK,
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VI4_DATA20_MARK, VI4_DATA21_MARK,
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VI4_DATA22_MARK, VI4_DATA23_MARK,
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VI4_DATA10_MARK, VI4_DATA11_MARK,
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VI4_DATA12_MARK, VI4_DATA13_MARK,
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VI4_DATA14_MARK, VI4_DATA15_MARK,
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VI4_DATA18_MARK, VI4_DATA19_MARK,
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VI4_DATA20_MARK, VI4_DATA21_MARK,
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VI4_DATA22_MARK, VI4_DATA23_MARK,
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};
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static const union vin_data vin4_data_a_pins = {
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@ -4294,12 +4294,12 @@ static const unsigned int vin4_data18_b_mux[] = {
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VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
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VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
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VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
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VI4_DATA10_MARK, VI4_DATA11_MARK,
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VI4_DATA12_MARK, VI4_DATA13_MARK,
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VI4_DATA14_MARK, VI4_DATA15_MARK,
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VI4_DATA18_MARK, VI4_DATA19_MARK,
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VI4_DATA20_MARK, VI4_DATA21_MARK,
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VI4_DATA22_MARK, VI4_DATA23_MARK,
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VI4_DATA10_MARK, VI4_DATA11_MARK,
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VI4_DATA12_MARK, VI4_DATA13_MARK,
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VI4_DATA14_MARK, VI4_DATA15_MARK,
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VI4_DATA18_MARK, VI4_DATA19_MARK,
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VI4_DATA20_MARK, VI4_DATA21_MARK,
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VI4_DATA22_MARK, VI4_DATA23_MARK,
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};
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static const union vin_data vin4_data_b_pins = {
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@ -6248,7 +6248,8 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
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{ /* sentinel */ },
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};
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static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
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static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc,
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unsigned int pin, u32 *pocctrl)
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{
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int bit = -EINVAL;
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@ -53,10 +53,10 @@
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PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(TCK, "TCK", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(TDI, "TDI", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
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PIN_NOGP_CFG(TRST_N, "TRST_N", fn, CFG_FLAGS)
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PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
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PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
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PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
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PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP)
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/*
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* F_() : just information
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@ -5197,8 +5197,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
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[27] = RCAR_GP_PIN(1, 0), /* A0 */
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[28] = SH_PFC_PIN_NONE,
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[29] = SH_PFC_PIN_NONE,
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[30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */
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[31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */
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[30] = RCAR_GP_PIN(2, 25), /* EX_WAIT0 */
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[31] = RCAR_GP_PIN(2, 24), /* RD/WR# */
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} },
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{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
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[0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
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@ -5333,8 +5333,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
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[27] = SH_PFC_PIN_NONE,
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[28] = SH_PFC_PIN_NONE,
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[29] = SH_PFC_PIN_NONE,
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[30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */
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[31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */
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[30] = RCAR_GP_PIN(6, 9), /* USB30_OVC */
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[31] = RCAR_GP_PIN(6, 17), /* USB30_PWEN */
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} },
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{ /* sentinel */ },
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};
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