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wl18xx: default config alignment with phy defaults
Driver default config is aligned with phy default parameters. Now that RDL1_3 has 2 antennas defined by default we need to explicitly define ht.mode to HT_MODE_WIDE to have SISO40 as default. Signed-off-by: Yair Shapira <yair.shapira@ti.com> Signed-off-by: Igal Chernobelsky <igalc@ti.com> Signed-off-by: Eliad Peller <eliad@wizery.com> Signed-off-by: Luciano Coelho <luciano.coelho@intel.com>
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a1b13b9ad3
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50e4c905a0
1 changed files with 8 additions and 8 deletions
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@ -505,7 +505,7 @@ static struct wlcore_conf wl18xx_conf = {
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static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
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.ht = {
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.mode = HT_MODE_DEFAULT,
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.mode = HT_MODE_WIDE,
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},
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.phy = {
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.phy_standalone = 0x00,
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@ -516,7 +516,7 @@ static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
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.auto_detect = 0x00,
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.dedicated_fem = FEM_NONE,
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.low_band_component = COMPONENT_3_WAY_SWITCH,
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.low_band_component_type = 0x04,
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.low_band_component_type = 0x05,
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.high_band_component = COMPONENT_2_WAY_SWITCH,
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.high_band_component_type = 0x09,
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.tcxo_ldo_voltage = 0x00,
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@ -556,15 +556,15 @@ static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
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.per_chan_pwr_limit_arr_11p = { 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff },
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.psat = 0,
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.low_power_val = 0x08,
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.med_power_val = 0x12,
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.high_power_val = 0x18,
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.low_power_val_2nd = 0x05,
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.med_power_val_2nd = 0x0a,
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.high_power_val_2nd = 0x14,
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.external_pa_dc2dc = 0,
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.number_of_assembled_ant2_4 = 2,
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.number_of_assembled_ant5 = 1,
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.low_power_val = 0xff,
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.med_power_val = 0xff,
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.high_power_val = 0xff,
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.low_power_val_2nd = 0xff,
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.med_power_val_2nd = 0xff,
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.high_power_val_2nd = 0xff,
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.tx_rf_margin = 1,
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},
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};
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