wl18xx: default config alignment with phy defaults

Driver default config is aligned with phy default parameters.

Now that RDL1_3 has 2 antennas defined by default we need to explicitly
define ht.mode to HT_MODE_WIDE to have SISO40 as default.

Signed-off-by: Yair Shapira <yair.shapira@ti.com>
Signed-off-by: Igal Chernobelsky <igalc@ti.com>
Signed-off-by: Eliad Peller <eliad@wizery.com>
Signed-off-by: Luciano Coelho <luciano.coelho@intel.com>
This commit is contained in:
Igal Chernobelsky 2013-09-09 12:24:32 +03:00 committed by Luciano Coelho
parent a1b13b9ad3
commit 50e4c905a0

View file

@ -505,7 +505,7 @@ static struct wlcore_conf wl18xx_conf = {
static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
.ht = {
.mode = HT_MODE_DEFAULT,
.mode = HT_MODE_WIDE,
},
.phy = {
.phy_standalone = 0x00,
@ -516,7 +516,7 @@ static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
.auto_detect = 0x00,
.dedicated_fem = FEM_NONE,
.low_band_component = COMPONENT_3_WAY_SWITCH,
.low_band_component_type = 0x04,
.low_band_component_type = 0x05,
.high_band_component = COMPONENT_2_WAY_SWITCH,
.high_band_component_type = 0x09,
.tcxo_ldo_voltage = 0x00,
@ -556,15 +556,15 @@ static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
.per_chan_pwr_limit_arr_11p = { 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff },
.psat = 0,
.low_power_val = 0x08,
.med_power_val = 0x12,
.high_power_val = 0x18,
.low_power_val_2nd = 0x05,
.med_power_val_2nd = 0x0a,
.high_power_val_2nd = 0x14,
.external_pa_dc2dc = 0,
.number_of_assembled_ant2_4 = 2,
.number_of_assembled_ant5 = 1,
.low_power_val = 0xff,
.med_power_val = 0xff,
.high_power_val = 0xff,
.low_power_val_2nd = 0xff,
.med_power_val_2nd = 0xff,
.high_power_val_2nd = 0xff,
.tx_rf_margin = 1,
},
};