can: m_can: fix whitespace in a few comments

Fixes whitespace in comments titling sections of register masks.

Link: https://lore.kernel.org/r/20210504125123.500553-5-torin@maxiluxsystems.com
Signed-off-by: Torin Cooper-Bennun <torin@maxiluxsystems.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This commit is contained in:
Torin Cooper-Bennun 2021-05-04 13:51:23 +01:00 committed by Marc Kleine-Budde
parent 0f31571668
commit 50fe7547b6

View file

@ -101,7 +101,7 @@ enum m_can_reg {
/* Test Register (TEST) */
#define TEST_LBCK BIT(4)
/* CC Control Register(CCCR) */
/* CC Control Register (CCCR) */
#define CCCR_TXP BIT(14)
#define CCCR_TEST BIT(7)
#define CCCR_DAR BIT(6)
@ -147,18 +147,18 @@ enum m_can_reg {
/* Timestamp Counter Value Register (TSCV) */
#define TSCV_TSC_MASK GENMASK(15, 0)
/* Error Counter Register(ECR) */
/* Error Counter Register (ECR) */
#define ECR_RP BIT(15)
#define ECR_REC_MASK GENMASK(14, 8)
#define ECR_TEC_MASK GENMASK(7, 0)
/* Protocol Status Register(PSR) */
/* Protocol Status Register (PSR) */
#define PSR_BO BIT(7)
#define PSR_EW BIT(6)
#define PSR_EP BIT(5)
#define PSR_LEC_MASK GENMASK(2, 0)
/* Interrupt Register(IR) */
/* Interrupt Register (IR) */
#define IR_ALL_INT 0xffffffff
/* Renamed bits for versions > 3.1.x */
@ -250,7 +250,7 @@ enum m_can_reg {
#define TXFQS_TFGI_MASK GENMASK(12, 8)
#define TXFQS_TFFL_MASK GENMASK(5, 0)
/* Tx Buffer Element Size Configuration(TXESC) */
/* Tx Buffer Element Size Configuration (TXESC) */
#define TXESC_TBDS_MASK GENMASK(2, 0)
#define TXESC_TBDS_64B 0x7