drm/amd/powerplay: fix pcie max lane define error

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2017-09-12 13:18:13 +08:00 committed by Alex Deucher
parent e71b7ae673
commit 510c2558b9

View file

@ -297,7 +297,7 @@ typedef enum PP_PCIEGen PP_PCIEGen;
#define PP_Min_PCIEGen PP_PCIEGen1
#define PP_Max_PCIEGen PP_PCIEGen3
#define PP_Min_PCIELane 1
#define PP_Max_PCIELane 32
#define PP_Max_PCIELane 16
enum phm_clock_Type {
PHM_DispClock = 1,