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tg3: Adjust BD replenish thresholds
The BD replenish thresholds for the 57765 and newer ASIC revs are a little strict. They were tuned for a mode that is currently unused. This patch relaxes the thresholds so that they are set to values more inline with the resources available. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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parent
f3791cdf33
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513aa6ea39
1 changed files with 3 additions and 5 deletions
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@ -8171,7 +8171,8 @@ static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
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if (!tg3_flag(tp, 5750_PLUS) ||
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if (!tg3_flag(tp, 5750_PLUS) ||
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tg3_flag(tp, 5780_CLASS) ||
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tg3_flag(tp, 5780_CLASS) ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
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tg3_flag(tp, 57765_PLUS))
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bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
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bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
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else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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@ -8191,10 +8192,7 @@ static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
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if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
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if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
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return;
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return;
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if (!tg3_flag(tp, 5705_PLUS))
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bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
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bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
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else
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bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717;
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host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
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host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
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