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drm/amdkfd: Extend CU mask to 8 SEs (v3)
Following bitmap layout logic introduced by: "drm/amdgpu: support get_cu_info for Arcturus". v2: squash in fixup for gfx_v9_0.c (Alex) v3: squash in debug print output fix Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
857b82d0df
commit
5145d57ec5
5 changed files with 30 additions and 12 deletions
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@ -3341,6 +3341,10 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
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mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
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mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
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mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
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mqd->compute_static_thread_mgmt_se4 = 0xffffffff;
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mqd->compute_static_thread_mgmt_se5 = 0xffffffff;
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mqd->compute_static_thread_mgmt_se6 = 0xffffffff;
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mqd->compute_static_thread_mgmt_se7 = 0xffffffff;
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mqd->compute_misc_reserved = 0x00000003;
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mqd->dynamic_cu_mask_addr_lo =
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@ -98,8 +98,8 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
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uint32_t *se_mask)
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{
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struct kfd_cu_info cu_info;
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uint32_t cu_per_sh[4] = {0};
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int i, se, cu = 0;
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uint32_t cu_per_se[KFD_MAX_NUM_SE] = {0};
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int i, se, sh, cu = 0;
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amdgpu_amdkfd_get_cu_info(mm->dev->kgd, &cu_info);
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@ -107,8 +107,8 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
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cu_mask_count = cu_info.cu_active_number;
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for (se = 0; se < cu_info.num_shader_engines; se++)
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for (i = 0; i < 4; i++)
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cu_per_sh[se] += hweight32(cu_info.cu_bitmap[se][i]);
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for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++)
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cu_per_se[se] += hweight32(cu_info.cu_bitmap[se % 4][sh + (se / 4)]);
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/* Symmetrically map cu_mask to all SEs:
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* cu_mask[0] bit0 -> se_mask[0] bit0;
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@ -128,6 +128,6 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
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se = 0;
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cu++;
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}
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} while (cu >= cu_per_sh[se] && cu < 32);
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} while (cu >= cu_per_se[se] && cu < 32);
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}
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}
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@ -26,6 +26,8 @@
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#include "kfd_priv.h"
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#define KFD_MAX_NUM_SE 8
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/**
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* struct mqd_manager
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*
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@ -46,7 +46,7 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd,
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struct queue_properties *q)
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{
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struct v9_mqd *m;
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uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */
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uint32_t se_mask[KFD_MAX_NUM_SE] = {0};
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if (q->cu_mask_count == 0)
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return;
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@ -59,12 +59,20 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd,
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m->compute_static_thread_mgmt_se1 = se_mask[1];
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m->compute_static_thread_mgmt_se2 = se_mask[2];
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m->compute_static_thread_mgmt_se3 = se_mask[3];
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m->compute_static_thread_mgmt_se4 = se_mask[4];
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m->compute_static_thread_mgmt_se5 = se_mask[5];
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m->compute_static_thread_mgmt_se6 = se_mask[6];
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m->compute_static_thread_mgmt_se7 = se_mask[7];
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pr_debug("update cu mask to %#x %#x %#x %#x\n",
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pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n",
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m->compute_static_thread_mgmt_se0,
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m->compute_static_thread_mgmt_se1,
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m->compute_static_thread_mgmt_se2,
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m->compute_static_thread_mgmt_se3);
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m->compute_static_thread_mgmt_se3,
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m->compute_static_thread_mgmt_se4,
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m->compute_static_thread_mgmt_se5,
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m->compute_static_thread_mgmt_se6,
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m->compute_static_thread_mgmt_se7);
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}
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static void set_priority(struct v9_mqd *m, struct queue_properties *q)
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@ -125,6 +133,10 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,
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m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
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m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
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m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
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m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF;
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m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF;
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m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF;
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m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF;
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m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
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0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
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@ -196,10 +196,10 @@ struct v9_mqd {
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uint32_t compute_wave_restore_addr_lo;
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uint32_t compute_wave_restore_addr_hi;
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uint32_t compute_wave_restore_control;
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uint32_t reserved_39;
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uint32_t reserved_40;
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uint32_t reserved_41;
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uint32_t reserved_42;
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uint32_t compute_static_thread_mgmt_se4;
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uint32_t compute_static_thread_mgmt_se5;
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uint32_t compute_static_thread_mgmt_se6;
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uint32_t compute_static_thread_mgmt_se7;
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uint32_t reserved_43;
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uint32_t reserved_44;
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uint32_t reserved_45;
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