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mt8173:

Browse source 
- add new power domain controller node
 
 mt8183:
 - add new power domain controller
 - add display, iommu and dsi nodes
 
 mt8192:
 - add basic support, pinctrl, uart, spi, i2c and timer
 
 mt8516:
 - add auxadc, efuse and usb nodes
 
 mt8167:
 - add basic support for the SoC
 - add support for the pumkin board
 
 mt6779:
 - add initial support, interrupt controller, clocks, uart
 
 mt7622:
 -  PWM node for all available PWM channels
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Merge tag 'v5.10-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

mt8173:
- add new power domain controller node

mt8183:
- add new power domain controller
- add display, iommu and dsi nodes

mt8192:
- add basic support, pinctrl, uart, spi, i2c and timer

mt8516:
- add auxadc, efuse and usb nodes

mt8167:
- add basic support for the SoC
- add support for the pumkin board

mt6779:
- add initial support, interrupt controller, clocks, uart

mt7622:
-  PWM node for all available PWM channels

* tag 'v5.10-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (25 commits)
  dts64: mt7622: disable spi1 and uart2 because pins are used by pwm
  dts64: mt7622: enable all pwm for bananapi r64
  arm64: dts: mt8183: Add display nodes for MT8183
  arm64: dts: mt8183: Add iommu and larb nodes
  arm64: dts: mt8183: Add dsi node
  arm64: dts: mt8183: Add pwm and backlight node
  arm64: dts: mediatek: Add mt8183 power domains controller
  arm64: dts: mediatek: Add smi_common node for MT8183
  arm64: dts: mediatek: Add mt8173 power domain controller
  dt-bindings: power: Add MT8192 power domains
  dt-bindings: power: Add MT8183 power domains
  dt-bindings: power: Add bindings for the Mediatek SCPSYS power domains controller
  arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile
  arm64: dts: mediatek: add MT8167 pumpkin board dts
  arm64: dts: mediatek: add dtsi for MT8167
  dt-bindings: arm64: dts: mediatek: Add mt8167-pumpkin board
  arm64: dts: mediatek: mt8516: add efuse node
  arm64: dts: mediatek: align GPIO hog names with dtschema
  arm64: dts: mediatek: mt8516: add usb1 node
  arm64: dts: mediatek: mt8516: rename usb phy
  ...

Link: https://lore.kernel.org/r/72fe1c4f-f27c-c455-dfd9-66bde90bb295@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-12-08 23:38:36 +01:00
commit 5161540797
20 changed files with 2638 additions and 71 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
Documentation/devicetree/bindings/arm/mediatek.yaml
View file

@ -84,6 +84,10 @@ properties:
- enum:
- mediatek,mt8135-evbp1
- const: mediatek,mt8135
- items:
- enum:
- mediatek,mt8167-pumpkin
- const: mediatek,mt8167
- description: Google Elm (Acer Chromebook R13)
items:
- const: google,elm-rev8

1
Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
View file

@ -17,6 +17,7 @@ Required properties:
- "mediatek,mt7622-auxadc": For MT7622 family of SoCs
- "mediatek,mt8173-auxadc": For MT8173 family of SoCs
- "mediatek,mt8183-auxadc", "mediatek,mt8173-auxadc": For MT8183 family of SoCs
- "mediatek,mt8516-auxadc", "mediatek,mt8173-auxadc": For MT8516 family of SoCs
- reg: Address range of the AUXADC unit.
- clocks: Should contain a clock specifier for each entry in clock-names
- clock-names: Should contain "main".

293
Documentation/devicetree/bindings/power/mediatek,power-controller.yaml Normal file
View file

@ -0,0 +1,293 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek Power Domains Controller
maintainers:
- Weiyi Lu <weiyi.lu@mediatek.com>
- Matthias Brugger <mbrugger@suse.com>
description: |
Mediatek processors include support for multiple power domains which can be
powered up/down by software based on different application scenes to save power.
IP cores belonging to a power domain should contain a 'power-domains'
property that is a phandle for SCPSYS node representing the domain.
properties:
$nodename:
const: power-controller
compatible:
enum:
- mediatek,mt8173-power-controller
- mediatek,mt8183-power-controller
- mediatek,mt8192-power-controller
'#power-domain-cells':
const: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
"^power-domain@[0-9a-f]+$":
type: object
description: |
Represents the power domains within the power controller node as documented
in Documentation/devicetree/bindings/power/power-domain.yaml.
properties:
'#power-domain-cells':
description:
Must be 0 for nodes representing a single PM domain and 1 for nodes
providing multiple PM domains.
'#address-cells':
const: 1
'#size-cells':
const: 0
reg:
description: |
Power domain index. Valid values are defined in:
"include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
"include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
"include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
maxItems: 1
clocks:
description: |
A number of phandles to clocks that need to be enabled during domain
power-up sequencing.
clock-names:
description: |
List of names of clocks, in order to match the power-up sequencing
for each power domain we need to group the clocks by name. BASIC
clocks need to be enabled before enabling the corresponding power
domain, and should not have a '-' in their name (i.e mm, mfg, venc).
SUSBYS clocks need to be enabled before releasing the bus protection,
and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
In order to follow properly the power-up sequencing, the clocks must
be specified by order, adding first the BASIC clocks followed by the
SUSBSYS clocks.
mediatek,infracfg:
$ref: /schemas/types.yaml#definitions/phandle
description: phandle to the device containing the INFRACFG register range.
mediatek,smi:
$ref: /schemas/types.yaml#definitions/phandle
description: phandle to the device containing the SMI register range.
patternProperties:
"^power-domain@[0-9a-f]+$":
type: object
description: |
Represents a power domain child within a power domain parent node.
properties:
'#power-domain-cells':
description:
Must be 0 for nodes representing a single PM domain and 1 for nodes
providing multiple PM domains.
'#address-cells':
const: 1
'#size-cells':
const: 0
reg:
maxItems: 1
clocks:
description: |
A number of phandles to clocks that need to be enabled during domain
power-up sequencing.
clock-names:
description: |
List of names of clocks, in order to match the power-up sequencing
for each power domain we need to group the clocks by name. BASIC
clocks need to be enabled before enabling the corresponding power
domain, and should not have a '-' in their name (i.e mm, mfg, venc).
SUSBYS clocks need to be enabled before releasing the bus protection,
and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
In order to follow properly the power-up sequencing, the clocks must
be specified by order, adding first the BASIC clocks followed by the
SUSBSYS clocks.
mediatek,infracfg:
$ref: /schemas/types.yaml#definitions/phandle
description: phandle to the device containing the INFRACFG register range.
mediatek,smi:
$ref: /schemas/types.yaml#definitions/phandle
description: phandle to the device containing the SMI register range.
patternProperties:
"^power-domain@[0-9a-f]+$":
type: object
description: |
Represents a power domain child within a power domain parent node.
properties:
'#power-domain-cells':
description:
Must be 0 for nodes representing a single PM domain and 1 for nodes
providing multiple PM domains.
'#address-cells':
const: 1
'#size-cells':
const: 0
reg:
maxItems: 1
clocks:
description: |
A number of phandles to clocks that need to be enabled during domain
power-up sequencing.
clock-names:
description: |
List of names of clocks, in order to match the power-up sequencing
for each power domain we need to group the clocks by name. BASIC
clocks need to be enabled before enabling the corresponding power
domain, and should not have a '-' in their name (i.e mm, mfg, venc).
SUSBYS clocks need to be enabled before releasing the bus protection,
and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
In order to follow properly the power-up sequencing, the clocks must
be specified by order, adding first the BASIC clocks followed by the
SUSBSYS clocks.
mediatek,infracfg:
$ref: /schemas/types.yaml#definitions/phandle
description: phandle to the device containing the INFRACFG register range.
mediatek,smi:
$ref: /schemas/types.yaml#definitions/phandle
description: phandle to the device containing the SMI register range.
required:
- reg
additionalProperties: false
required:
- reg
additionalProperties: false
required:
- reg
additionalProperties: false
required:
- compatible
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/power/mt8173-power.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
scpsys: syscon@10006000 {
compatible = "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
spm: power-controller {
compatible = "mediatek,mt8173-power-controller";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
/* power domains of the SoC */
power-domain@MT8173_POWER_DOMAIN_VDEC {
reg = <MT8173_POWER_DOMAIN_VDEC>;
clocks = <&topckgen CLK_TOP_MM_SEL>;
clock-names = "mm";
#power-domain-cells = <0>;
};
power-domain@MT8173_POWER_DOMAIN_VENC {
reg = <MT8173_POWER_DOMAIN_VENC>;
clocks = <&topckgen CLK_TOP_MM_SEL>,
<&topckgen CLK_TOP_VENC_SEL>;
clock-names = "mm", "venc";
#power-domain-cells = <0>;
};
power-domain@MT8173_POWER_DOMAIN_ISP {
reg = <MT8173_POWER_DOMAIN_ISP>;
clocks = <&topckgen CLK_TOP_MM_SEL>;
clock-names = "mm";
#power-domain-cells = <0>;
};
power-domain@MT8173_POWER_DOMAIN_MM {
reg = <MT8173_POWER_DOMAIN_MM>;
clocks = <&topckgen CLK_TOP_MM_SEL>;
clock-names = "mm";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8173_POWER_DOMAIN_VENC_LT {
reg = <MT8173_POWER_DOMAIN_VENC_LT>;
clocks = <&topckgen CLK_TOP_MM_SEL>,
<&topckgen CLK_TOP_VENC_LT_SEL>;
clock-names = "mm", "venclt";
#power-domain-cells = <0>;
};
power-domain@MT8173_POWER_DOMAIN_AUDIO {
reg = <MT8173_POWER_DOMAIN_AUDIO>;
#power-domain-cells = <0>;
};
power-domain@MT8173_POWER_DOMAIN_USB {
reg = <MT8173_POWER_DOMAIN_USB>;
#power-domain-cells = <0>;
};
power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
clocks = <&clk26m>;
clock-names = "mfg";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8173_POWER_DOMAIN_MFG_2D {
reg = <MT8173_POWER_DOMAIN_MFG_2D>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8173_POWER_DOMAIN_MFG {
reg = <MT8173_POWER_DOMAIN_MFG>;
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
};
};
};
};
};

3
arch/arm64/boot/dts/mediatek/Makefile
View file

@ -1,15 +1,18 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb

31
arch/arm64/boot/dts/mediatek/mt6779-evb.dts Normal file
View file

@ -0,0 +1,31 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Mars.C <mars.cheng@mediatek.com>
*
*/
/dts-v1/;
#include "mt6779.dtsi"
/ {
model = "MediaTek MT6779 EVB";
compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
aliases {
serial0 = &uart0;
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x1e800000>;
};
chosen {
stdout-path = "serial0:921600n8";
};
};
&uart0 {
status = "okay";
};

271
arch/arm64/boot/dts/mediatek/mt6779.dtsi Normal file
View file

@ -0,0 +1,271 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Mars.C <mars.cheng@mediatek.com>
*
*/
#include <dt-bindings/clock/mt6779-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt6779-pinfunc.h>
/ {
compatible = "mediatek,mt6779";
interrupt-parent = <&sysirq>;
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
enable-method = "psci";
reg = <0x000>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a55";
enable-method = "psci";
reg = <0x100>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a55";
enable-method = "psci";
reg = <0x200>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a55";
enable-method = "psci";
reg = <0x300>;
};
cpu4: cpu@4 {
device_type = "cpu";
compatible = "arm,cortex-a55";
enable-method = "psci";
reg = <0x400>;
};
cpu5: cpu@5 {
device_type = "cpu";
compatible = "arm,cortex-a55";
enable-method = "psci";
reg = <0x500>;
};
cpu6: cpu@6 {
device_type = "cpu";
compatible = "arm,cortex-a75";
enable-method = "psci";
reg = <0x600>;
};
cpu7: cpu@7 {
device_type = "cpu";
compatible = "arm,cortex-a75";
enable-method = "psci";
reg = <0x700>;
};
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>;
};
clk26m: oscillator@0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
clk32k: oscillator@1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "clk32k";
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
gic: interrupt-controller@0c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x40000>, /* GICD */
<0 0x0c040000 0 0x200000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
ppi-partitions {
ppi_cluster0: interrupt-partition-0 {
affinity = <&cpu0 &cpu1 \
&cpu2 &cpu3 &cpu4 &cpu5>;
};
ppi_cluster1: interrupt-partition-1 {
affinity = <&cpu6 &cpu7>;
};
};
};
sysirq: intpol-controller@0c53a650 {
compatible = "mediatek,mt6779-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x0c53a650 0 0x50>;
};
topckgen: clock-controller@10000000 {
compatible = "mediatek,mt6779-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infracfg_ao: clock-controller@10001000 {
compatible = "mediatek,mt6779-infracfg_ao", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
};
pio: pinctrl@10005000 {
compatible = "mediatek,mt6779-pinctrl", "syscon";
reg = <0 0x10005000 0 0x1000>,
<0 0x11c20000 0 0x1000>,
<0 0x11d10000 0 0x1000>,
<0 0x11e20000 0 0x1000>,
<0 0x11e70000 0 0x1000>,
<0 0x11ea0000 0 0x1000>,
<0 0x11f20000 0 0x1000>,
<0 0x11f30000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "gpio", "iocfg_rm",
"iocfg_br", "iocfg_lm",
"iocfg_lb", "iocfg_rt",
"iocfg_lt", "iocfg_tl",
"eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 210>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
};
apmixed: clock-controller@1000c000 {
compatible = "mediatek,mt6779-apmixed", "syscon";
reg = <0 0x1000c000 0 0xe00>;
#clock-cells = <1>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt6779-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>;
clock-names = "baud", "bus";
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt6779-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>;
clock-names = "baud", "bus";
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt6779-uart",
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>;
clock-names = "baud", "bus";
status = "disabled";
};
audio: clock-controller@11210000 {
compatible = "mediatek,mt6779-audio", "syscon";
reg = <0 0x11210000 0 0x1000>;
#clock-cells = <1>;
};
mfgcfg: clock-controller@13fbf000 {
compatible = "mediatek,mt6779-mfgcfg", "syscon";
reg = <0 0x13fbf000 0 0x1000>;
#clock-cells = <1>;
};
mmsys: syscon@14000000 {
compatible = "mediatek,mt6779-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};
imgsys: clock-controller@15020000 {
compatible = "mediatek,mt6779-imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;
#clock-cells = <1>;
};
vdecsys: clock-controller@16000000 {
compatible = "mediatek,mt6779-vdecsys", "syscon";
reg = <0 0x16000000 0 0x1000>;
#clock-cells = <1>;
};
vencsys: clock-controller@17000000 {
compatible = "mediatek,mt6779-vencsys", "syscon";
reg = <0 0x17000000 0 0x1000>;
#clock-cells = <1>;
};
camsys: clock-controller@1a000000 {
compatible = "mediatek,mt6779-camsys", "syscon";
reg = <0 0x1a000000 0 0x10000>;
#clock-cells = <1>;
};
ipesys: clock-controller@1b000000 {
compatible = "mediatek,mt6779-ipesys", "syscon";
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
};
};
};

13
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
View file

@ -412,10 +412,15 @@ mux {
};
};
pwm7_pins: pwm1-2-pins {
pwm_pins: pwm-pins {
mux {
function = "pwm";
groups = "pwm_ch7_2";
groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */
"pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */
"pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */
"pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */
"pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */
"pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */
};
};
@ -535,7 +540,7 @@ mux {
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm7_pins>;
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
@ -563,7 +568,6 @@ &spi0 {
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spic1_pins>;
status = "okay";
};
&ssusb {
@ -585,7 +589,6 @@ &uart0 {
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&watchdog {

744
arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h Normal file
View file

@ -0,0 +1,744 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020 MediaTek Inc.
*/
#ifndef __DTS_MT8167_PINFUNC_H
#define __DTS_MT8167_PINFUNC_H
#include <dt-bindings/pinctrl/mt65xx.h>
#define MT8167_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
#define MT8167_PIN_0_EINT0__FUNC_PWM_B (MTK_PIN_NO(0) | 1)
#define MT8167_PIN_0_EINT0__FUNC_DPI_CK (MTK_PIN_NO(0) | 2)
#define MT8167_PIN_0_EINT0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3)
#define MT8167_PIN_0_EINT0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4)
#define MT8167_PIN_0_EINT0__FUNC_SQICS (MTK_PIN_NO(0) | 6)
#define MT8167_PIN_0_EINT0__FUNC_DBG_MON_A_6 (MTK_PIN_NO(0) | 7)
#define MT8167_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
#define MT8167_PIN_1_EINT1__FUNC_PWM_C (MTK_PIN_NO(1) | 1)
#define MT8167_PIN_1_EINT1__FUNC_DPI_D12 (MTK_PIN_NO(1) | 2)
#define MT8167_PIN_1_EINT1__FUNC_I2S2_DI (MTK_PIN_NO(1) | 3)
#define MT8167_PIN_1_EINT1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4)
#define MT8167_PIN_1_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(1) | 5)
#define MT8167_PIN_1_EINT1__FUNC_SQISO (MTK_PIN_NO(1) | 6)
#define MT8167_PIN_1_EINT1__FUNC_DBG_MON_A_7 (MTK_PIN_NO(1) | 7)
#define MT8167_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
#define MT8167_PIN_2_EINT2__FUNC_CLKM0 (MTK_PIN_NO(2) | 1)
#define MT8167_PIN_2_EINT2__FUNC_DPI_D13 (MTK_PIN_NO(2) | 2)
#define MT8167_PIN_2_EINT2__FUNC_I2S2_LRCK (MTK_PIN_NO(2) | 3)
#define MT8167_PIN_2_EINT2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4)
#define MT8167_PIN_2_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(2) | 5)
#define MT8167_PIN_2_EINT2__FUNC_SQISI (MTK_PIN_NO(2) | 6)
#define MT8167_PIN_2_EINT2__FUNC_DBG_MON_A_8 (MTK_PIN_NO(2) | 7)
#define MT8167_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
#define MT8167_PIN_3_EINT3__FUNC_CLKM1 (MTK_PIN_NO(3) | 1)
#define MT8167_PIN_3_EINT3__FUNC_DPI_D14 (MTK_PIN_NO(3) | 2)
#define MT8167_PIN_3_EINT3__FUNC_SPI_MI (MTK_PIN_NO(3) | 3)
#define MT8167_PIN_3_EINT3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4)
#define MT8167_PIN_3_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(3) | 5)
#define MT8167_PIN_3_EINT3__FUNC_SQIWP (MTK_PIN_NO(3) | 6)
#define MT8167_PIN_3_EINT3__FUNC_DBG_MON_A_9 (MTK_PIN_NO(3) | 7)
#define MT8167_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
#define MT8167_PIN_4_EINT4__FUNC_CLKM2 (MTK_PIN_NO(4) | 1)
#define MT8167_PIN_4_EINT4__FUNC_DPI_D15 (MTK_PIN_NO(4) | 2)
#define MT8167_PIN_4_EINT4__FUNC_SPI_MO (MTK_PIN_NO(4) | 3)
#define MT8167_PIN_4_EINT4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4)
#define MT8167_PIN_4_EINT4__FUNC_CONN_MCU_TCK (MTK_PIN_NO(4) | 5)
#define MT8167_PIN_4_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(4) | 6)
#define MT8167_PIN_4_EINT4__FUNC_DBG_MON_A_10 (MTK_PIN_NO(4) | 7)
#define MT8167_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
#define MT8167_PIN_5_EINT5__FUNC_UCTS2 (MTK_PIN_NO(5) | 1)
#define MT8167_PIN_5_EINT5__FUNC_DPI_D16 (MTK_PIN_NO(5) | 2)
#define MT8167_PIN_5_EINT5__FUNC_SPI_CSB (MTK_PIN_NO(5) | 3)
#define MT8167_PIN_5_EINT5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4)
#define MT8167_PIN_5_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(5) | 5)
#define MT8167_PIN_5_EINT5__FUNC_CONN_TEST_CK (MTK_PIN_NO(5) | 6)
#define MT8167_PIN_5_EINT5__FUNC_DBG_MON_A_11 (MTK_PIN_NO(5) | 7)
#define MT8167_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
#define MT8167_PIN_6_EINT6__FUNC_URTS2 (MTK_PIN_NO(6) | 1)
#define MT8167_PIN_6_EINT6__FUNC_DPI_D17 (MTK_PIN_NO(6) | 2)
#define MT8167_PIN_6_EINT6__FUNC_SPI_CLK (MTK_PIN_NO(6) | 3)
#define MT8167_PIN_6_EINT6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4)
#define MT8167_PIN_6_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(6) | 5)
#define MT8167_PIN_6_EINT6__FUNC_MM_TEST_CK (MTK_PIN_NO(6) | 6)
#define MT8167_PIN_6_EINT6__FUNC_DBG_MON_A_12 (MTK_PIN_NO(6) | 7)
#define MT8167_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
#define MT8167_PIN_7_EINT7__FUNC_SQIRST (MTK_PIN_NO(7) | 1)
#define MT8167_PIN_7_EINT7__FUNC_DPI_D6 (MTK_PIN_NO(7) | 2)
#define MT8167_PIN_7_EINT7__FUNC_SDA1_0 (MTK_PIN_NO(7) | 3)
#define MT8167_PIN_7_EINT7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4)
#define MT8167_PIN_7_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(7) | 5)
#define MT8167_PIN_7_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(7) | 6)
#define MT8167_PIN_7_EINT7__FUNC_DBG_MON_A_13 (MTK_PIN_NO(7) | 7)
#define MT8167_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
#define MT8167_PIN_8_EINT8__FUNC_SQICK (MTK_PIN_NO(8) | 1)
#define MT8167_PIN_8_EINT8__FUNC_CLKM3 (MTK_PIN_NO(8) | 2)
#define MT8167_PIN_8_EINT8__FUNC_SCL1_0 (MTK_PIN_NO(8) | 3)
#define MT8167_PIN_8_EINT8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4)
#define MT8167_PIN_8_EINT8__FUNC_ANT_SEL0 (MTK_PIN_NO(8) | 5)
#define MT8167_PIN_8_EINT8__FUNC_DPI_D7 (MTK_PIN_NO(8) | 6)
#define MT8167_PIN_8_EINT8__FUNC_DBG_MON_A_14 (MTK_PIN_NO(8) | 7)
#define MT8167_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
#define MT8167_PIN_9_EINT9__FUNC_CLKM4 (MTK_PIN_NO(9) | 1)
#define MT8167_PIN_9_EINT9__FUNC_SDA2_0 (MTK_PIN_NO(9) | 2)
#define MT8167_PIN_9_EINT9__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3)
#define MT8167_PIN_9_EINT9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4)
#define MT8167_PIN_9_EINT9__FUNC_ANT_SEL1 (MTK_PIN_NO(9) | 5)
#define MT8167_PIN_9_EINT9__FUNC_DPI_D8 (MTK_PIN_NO(9) | 6)
#define MT8167_PIN_9_EINT9__FUNC_DBG_MON_A_15 (MTK_PIN_NO(9) | 7)
#define MT8167_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
#define MT8167_PIN_10_EINT10__FUNC_CLKM5 (MTK_PIN_NO(10) | 1)
#define MT8167_PIN_10_EINT10__FUNC_SCL2_0 (MTK_PIN_NO(10) | 2)
#define MT8167_PIN_10_EINT10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 3)
#define MT8167_PIN_10_EINT10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4)
#define MT8167_PIN_10_EINT10__FUNC_ANT_SEL2 (MTK_PIN_NO(10) | 5)
#define MT8167_PIN_10_EINT10__FUNC_DPI_D9 (MTK_PIN_NO(10) | 6)
#define MT8167_PIN_10_EINT10__FUNC_DBG_MON_A_16 (MTK_PIN_NO(10) | 7)
#define MT8167_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
#define MT8167_PIN_11_EINT11__FUNC_CLKM4 (MTK_PIN_NO(11) | 1)
#define MT8167_PIN_11_EINT11__FUNC_PWM_C (MTK_PIN_NO(11) | 2)
#define MT8167_PIN_11_EINT11__FUNC_CONN_TEST_CK (MTK_PIN_NO(11) | 3)
#define MT8167_PIN_11_EINT11__FUNC_ANT_SEL3 (MTK_PIN_NO(11) | 4)
#define MT8167_PIN_11_EINT11__FUNC_DPI_D10 (MTK_PIN_NO(11) | 5)
#define MT8167_PIN_11_EINT11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 6)
#define MT8167_PIN_11_EINT11__FUNC_DBG_MON_A_17 (MTK_PIN_NO(11) | 7)
#define MT8167_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
#define MT8167_PIN_12_EINT12__FUNC_CLKM5 (MTK_PIN_NO(12) | 1)
#define MT8167_PIN_12_EINT12__FUNC_PWM_A (MTK_PIN_NO(12) | 2)
#define MT8167_PIN_12_EINT12__FUNC_SPDIF_OUT (MTK_PIN_NO(12) | 3)
#define MT8167_PIN_12_EINT12__FUNC_ANT_SEL4 (MTK_PIN_NO(12) | 4)
#define MT8167_PIN_12_EINT12__FUNC_DPI_D11 (MTK_PIN_NO(12) | 5)
#define MT8167_PIN_12_EINT12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 6)
#define MT8167_PIN_12_EINT12__FUNC_DBG_MON_A_18 (MTK_PIN_NO(12) | 7)
#define MT8167_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
#define MT8167_PIN_13_EINT13__FUNC_TSF_IN (MTK_PIN_NO(13) | 3)
#define MT8167_PIN_13_EINT13__FUNC_ANT_SEL5 (MTK_PIN_NO(13) | 4)
#define MT8167_PIN_13_EINT13__FUNC_DPI_D0 (MTK_PIN_NO(13) | 5)
#define MT8167_PIN_13_EINT13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 6)
#define MT8167_PIN_13_EINT13__FUNC_DBG_MON_A_19 (MTK_PIN_NO(13) | 7)
#define MT8167_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
#define MT8167_PIN_14_EINT14__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(14) | 2)
#define MT8167_PIN_14_EINT14__FUNC_TDM_RX_MCK (MTK_PIN_NO(14) | 3)
#define MT8167_PIN_14_EINT14__FUNC_ANT_SEL1 (MTK_PIN_NO(14) | 4)
#define MT8167_PIN_14_EINT14__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(14) | 5)
#define MT8167_PIN_14_EINT14__FUNC_NCLE (MTK_PIN_NO(14) | 6)
#define MT8167_PIN_14_EINT14__FUNC_DBG_MON_B_8 (MTK_PIN_NO(14) | 7)
#define MT8167_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
#define MT8167_PIN_15_EINT15__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(15) | 2)
#define MT8167_PIN_15_EINT15__FUNC_TDM_RX_BCK (MTK_PIN_NO(15) | 3)
#define MT8167_PIN_15_EINT15__FUNC_ANT_SEL2 (MTK_PIN_NO(15) | 4)
#define MT8167_PIN_15_EINT15__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(15) | 5)
#define MT8167_PIN_15_EINT15__FUNC_NCEB1 (MTK_PIN_NO(15) | 6)
#define MT8167_PIN_15_EINT15__FUNC_DBG_MON_B_9 (MTK_PIN_NO(15) | 7)
#define MT8167_PIN_16_EINT16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
#define MT8167_PIN_16_EINT16__FUNC_I2S_8CH_BCK (MTK_PIN_NO(16) | 2)
#define MT8167_PIN_16_EINT16__FUNC_TDM_RX_LRCK (MTK_PIN_NO(16) | 3)
#define MT8167_PIN_16_EINT16__FUNC_ANT_SEL3 (MTK_PIN_NO(16) | 4)
#define MT8167_PIN_16_EINT16__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(16) | 5)
#define MT8167_PIN_16_EINT16__FUNC_NCEB0 (MTK_PIN_NO(16) | 6)
#define MT8167_PIN_16_EINT16__FUNC_DBG_MON_B_10 (MTK_PIN_NO(16) | 7)
#define MT8167_PIN_17_EINT17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
#define MT8167_PIN_17_EINT17__FUNC_I2S_8CH_MCK (MTK_PIN_NO(17) | 2)
#define MT8167_PIN_17_EINT17__FUNC_TDM_RX_DI (MTK_PIN_NO(17) | 3)
#define MT8167_PIN_17_EINT17__FUNC_IDDIG (MTK_PIN_NO(17) | 4)
#define MT8167_PIN_17_EINT17__FUNC_ANT_SEL4 (MTK_PIN_NO(17) | 5)
#define MT8167_PIN_17_EINT17__FUNC_NREB (MTK_PIN_NO(17) | 6)
#define MT8167_PIN_17_EINT17__FUNC_DBG_MON_B_11 (MTK_PIN_NO(17) | 7)
#define MT8167_PIN_18_EINT18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
#define MT8167_PIN_18_EINT18__FUNC_USB_DRVVBUS (MTK_PIN_NO(18) | 2)
#define MT8167_PIN_18_EINT18__FUNC_I2S3_LRCK (MTK_PIN_NO(18) | 3)
#define MT8167_PIN_18_EINT18__FUNC_CLKM1 (MTK_PIN_NO(18) | 4)
#define MT8167_PIN_18_EINT18__FUNC_ANT_SEL3 (MTK_PIN_NO(18) | 5)
#define MT8167_PIN_18_EINT18__FUNC_I2S2_BCK (MTK_PIN_NO(18) | 6)
#define MT8167_PIN_18_EINT18__FUNC_DBG_MON_A_20 (MTK_PIN_NO(18) | 7)
#define MT8167_PIN_19_EINT19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
#define MT8167_PIN_19_EINT19__FUNC_UCTS1 (MTK_PIN_NO(19) | 1)
#define MT8167_PIN_19_EINT19__FUNC_IDDIG (MTK_PIN_NO(19) | 2)
#define MT8167_PIN_19_EINT19__FUNC_I2S3_BCK (MTK_PIN_NO(19) | 3)
#define MT8167_PIN_19_EINT19__FUNC_CLKM2 (MTK_PIN_NO(19) | 4)
#define MT8167_PIN_19_EINT19__FUNC_ANT_SEL4 (MTK_PIN_NO(19) | 5)
#define MT8167_PIN_19_EINT19__FUNC_I2S2_DI (MTK_PIN_NO(19) | 6)
#define MT8167_PIN_19_EINT19__FUNC_DBG_MON_A_21 (MTK_PIN_NO(19) | 7)
#define MT8167_PIN_20_EINT20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
#define MT8167_PIN_20_EINT20__FUNC_URTS1 (MTK_PIN_NO(20) | 1)
#define MT8167_PIN_20_EINT20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 3)
#define MT8167_PIN_20_EINT20__FUNC_CLKM3 (MTK_PIN_NO(20) | 4)
#define MT8167_PIN_20_EINT20__FUNC_ANT_SEL5 (MTK_PIN_NO(20) | 5)
#define MT8167_PIN_20_EINT20__FUNC_I2S2_LRCK (MTK_PIN_NO(20) | 6)
#define MT8167_PIN_20_EINT20__FUNC_DBG_MON_A_22 (MTK_PIN_NO(20) | 7)
#define MT8167_PIN_21_EINT21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
#define MT8167_PIN_21_EINT21__FUNC_NRNB (MTK_PIN_NO(21) | 1)
#define MT8167_PIN_21_EINT21__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 2)
#define MT8167_PIN_21_EINT21__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(21) | 3)
#define MT8167_PIN_21_EINT21__FUNC_DBG_MON_B_31 (MTK_PIN_NO(21) | 7)
#define MT8167_PIN_22_EINT22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
#define MT8167_PIN_22_EINT22__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(22) | 2)
#define MT8167_PIN_22_EINT22__FUNC_TSF_IN (MTK_PIN_NO(22) | 3)
#define MT8167_PIN_22_EINT22__FUNC_USB_DRVVBUS (MTK_PIN_NO(22) | 4)
#define MT8167_PIN_22_EINT22__FUNC_SPDIF_OUT (MTK_PIN_NO(22) | 5)
#define MT8167_PIN_22_EINT22__FUNC_NRE_C (MTK_PIN_NO(22) | 6)
#define MT8167_PIN_22_EINT22__FUNC_DBG_MON_B_12 (MTK_PIN_NO(22) | 7)
#define MT8167_PIN_23_EINT23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
#define MT8167_PIN_23_EINT23__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(23) | 2)
#define MT8167_PIN_23_EINT23__FUNC_CLKM0 (MTK_PIN_NO(23) | 3)
#define MT8167_PIN_23_EINT23__FUNC_IR (MTK_PIN_NO(23) | 4)
#define MT8167_PIN_23_EINT23__FUNC_SPDIF_IN (MTK_PIN_NO(23) | 5)
#define MT8167_PIN_23_EINT23__FUNC_NDQS_C (MTK_PIN_NO(23) | 6)
#define MT8167_PIN_23_EINT23__FUNC_DBG_MON_B_13 (MTK_PIN_NO(23) | 7)
#define MT8167_PIN_24_EINT24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
#define MT8167_PIN_24_EINT24__FUNC_DPI_D20 (MTK_PIN_NO(24) | 1)
#define MT8167_PIN_24_EINT24__FUNC_DPI_DE (MTK_PIN_NO(24) | 2)
#define MT8167_PIN_24_EINT24__FUNC_ANT_SEL1 (MTK_PIN_NO(24) | 3)
#define MT8167_PIN_24_EINT24__FUNC_UCTS2 (MTK_PIN_NO(24) | 4)
#define MT8167_PIN_24_EINT24__FUNC_PWM_A (MTK_PIN_NO(24) | 5)
#define MT8167_PIN_24_EINT24__FUNC_I2S0_MCK (MTK_PIN_NO(24) | 6)
#define MT8167_PIN_24_EINT24__FUNC_DBG_MON_A_0 (MTK_PIN_NO(24) | 7)
#define MT8167_PIN_25_EINT25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
#define MT8167_PIN_25_EINT25__FUNC_DPI_D19 (MTK_PIN_NO(25) | 1)
#define MT8167_PIN_25_EINT25__FUNC_DPI_VSYNC (MTK_PIN_NO(25) | 2)
#define MT8167_PIN_25_EINT25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 3)
#define MT8167_PIN_25_EINT25__FUNC_URTS2 (MTK_PIN_NO(25) | 4)
#define MT8167_PIN_25_EINT25__FUNC_PWM_B (MTK_PIN_NO(25) | 5)
#define MT8167_PIN_25_EINT25__FUNC_I2S_8CH_MCK (MTK_PIN_NO(25) | 6)
#define MT8167_PIN_25_EINT25__FUNC_DBG_MON_A_1 (MTK_PIN_NO(25) | 7)
#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(26) | 1)
#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(26) | 2)
#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(27) | 1)
#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(27) | 2)
#define MT8167_PIN_28_PWRAP_INT__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S0_MCK (MTK_PIN_NO(28) | 1)
#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S_8CH_MCK (MTK_PIN_NO(28) | 4)
#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S2_MCK (MTK_PIN_NO(28) | 5)
#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S3_MCK (MTK_PIN_NO(28) | 6)
#define MT8167_PIN_29_PWRAP_SPI0_CK__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
#define MT8167_PIN_29_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(29) | 1)
#define MT8167_PIN_30_PWRAP_SPI0_CSN__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
#define MT8167_PIN_30_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(30) | 1)
#define MT8167_PIN_31_RTC32K_CK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
#define MT8167_PIN_31_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(31) | 1)
#define MT8167_PIN_32_WATCHDOG__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
#define MT8167_PIN_32_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(32) | 1)
#define MT8167_PIN_33_SRCLKENA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
#define MT8167_PIN_33_SRCLKENA__FUNC_SRCLKENA0 (MTK_PIN_NO(33) | 1)
#define MT8167_PIN_34_URXD2__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
#define MT8167_PIN_34_URXD2__FUNC_URXD2 (MTK_PIN_NO(34) | 1)
#define MT8167_PIN_34_URXD2__FUNC_DPI_D5 (MTK_PIN_NO(34) | 2)
#define MT8167_PIN_34_URXD2__FUNC_UTXD2 (MTK_PIN_NO(34) | 3)
#define MT8167_PIN_34_URXD2__FUNC_DBG_SCL (MTK_PIN_NO(34) | 4)
#define MT8167_PIN_34_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(34) | 6)
#define MT8167_PIN_34_URXD2__FUNC_DBG_MON_B_0 (MTK_PIN_NO(34) | 7)
#define MT8167_PIN_35_UTXD2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
#define MT8167_PIN_35_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(35) | 1)
#define MT8167_PIN_35_UTXD2__FUNC_DPI_HSYNC (MTK_PIN_NO(35) | 2)
#define MT8167_PIN_35_UTXD2__FUNC_URXD2 (MTK_PIN_NO(35) | 3)
#define MT8167_PIN_35_UTXD2__FUNC_DBG_SDA (MTK_PIN_NO(35) | 4)
#define MT8167_PIN_35_UTXD2__FUNC_DPI_D18 (MTK_PIN_NO(35) | 5)
#define MT8167_PIN_35_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(35) | 6)
#define MT8167_PIN_35_UTXD2__FUNC_DBG_MON_B_1 (MTK_PIN_NO(35) | 7)
#define MT8167_PIN_36_MRG_CLK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
#define MT8167_PIN_36_MRG_CLK__FUNC_MRG_CLK (MTK_PIN_NO(36) | 1)
#define MT8167_PIN_36_MRG_CLK__FUNC_DPI_D4 (MTK_PIN_NO(36) | 2)
#define MT8167_PIN_36_MRG_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(36) | 3)
#define MT8167_PIN_36_MRG_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(36) | 4)
#define MT8167_PIN_36_MRG_CLK__FUNC_PCM0_CLK (MTK_PIN_NO(36) | 5)
#define MT8167_PIN_36_MRG_CLK__FUNC_IR (MTK_PIN_NO(36) | 6)
#define MT8167_PIN_36_MRG_CLK__FUNC_DBG_MON_A_2 (MTK_PIN_NO(36) | 7)
#define MT8167_PIN_37_MRG_SYNC__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
#define MT8167_PIN_37_MRG_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(37) | 1)
#define MT8167_PIN_37_MRG_SYNC__FUNC_DPI_D3 (MTK_PIN_NO(37) | 2)
#define MT8167_PIN_37_MRG_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(37) | 3)
#define MT8167_PIN_37_MRG_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(37) | 4)
#define MT8167_PIN_37_MRG_SYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(37) | 5)
#define MT8167_PIN_37_MRG_SYNC__FUNC_EXT_COL (MTK_PIN_NO(37) | 6)
#define MT8167_PIN_37_MRG_SYNC__FUNC_DBG_MON_A_3 (MTK_PIN_NO(37) | 7)
#define MT8167_PIN_38_MRG_DI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
#define MT8167_PIN_38_MRG_DI__FUNC_MRG_DI (MTK_PIN_NO(38) | 1)
#define MT8167_PIN_38_MRG_DI__FUNC_DPI_D1 (MTK_PIN_NO(38) | 2)
#define MT8167_PIN_38_MRG_DI__FUNC_I2S0_DI (MTK_PIN_NO(38) | 3)
#define MT8167_PIN_38_MRG_DI__FUNC_I2S3_DO (MTK_PIN_NO(38) | 4)
#define MT8167_PIN_38_MRG_DI__FUNC_PCM0_DI (MTK_PIN_NO(38) | 5)
#define MT8167_PIN_38_MRG_DI__FUNC_EXT_MDIO (MTK_PIN_NO(38) | 6)
#define MT8167_PIN_38_MRG_DI__FUNC_DBG_MON_A_4 (MTK_PIN_NO(38) | 7)
#define MT8167_PIN_39_MRG_DO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
#define MT8167_PIN_39_MRG_DO__FUNC_MRG_DO (MTK_PIN_NO(39) | 1)
#define MT8167_PIN_39_MRG_DO__FUNC_DPI_D2 (MTK_PIN_NO(39) | 2)
#define MT8167_PIN_39_MRG_DO__FUNC_I2S0_MCK (MTK_PIN_NO(39) | 3)
#define MT8167_PIN_39_MRG_DO__FUNC_I2S3_MCK (MTK_PIN_NO(39) | 4)
#define MT8167_PIN_39_MRG_DO__FUNC_PCM0_DO (MTK_PIN_NO(39) | 5)
#define MT8167_PIN_39_MRG_DO__FUNC_EXT_MDC (MTK_PIN_NO(39) | 6)
#define MT8167_PIN_39_MRG_DO__FUNC_DBG_MON_A_5 (MTK_PIN_NO(39) | 7)
#define MT8167_PIN_40_KPROW0__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
#define MT8167_PIN_40_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(40) | 1)
#define MT8167_PIN_40_KPROW0__FUNC_IMG_TEST_CK (MTK_PIN_NO(40) | 4)
#define MT8167_PIN_40_KPROW0__FUNC_DBG_MON_B_4 (MTK_PIN_NO(40) | 7)
#define MT8167_PIN_41_KPROW1__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
#define MT8167_PIN_41_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(41) | 1)
#define MT8167_PIN_41_KPROW1__FUNC_IDDIG (MTK_PIN_NO(41) | 2)
#define MT8167_PIN_41_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 3)
#define MT8167_PIN_41_KPROW1__FUNC_MFG_TEST_CK (MTK_PIN_NO(41) | 4)
#define MT8167_PIN_41_KPROW1__FUNC_DBG_MON_B_5 (MTK_PIN_NO(41) | 7)
#define MT8167_PIN_42_KPCOL0__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
#define MT8167_PIN_42_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(42) | 1)
#define MT8167_PIN_42_KPCOL0__FUNC_DBG_MON_B_6 (MTK_PIN_NO(42) | 7)
#define MT8167_PIN_43_KPCOL1__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
#define MT8167_PIN_43_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(43) | 1)
#define MT8167_PIN_43_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(43) | 2)
#define MT8167_PIN_43_KPCOL1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(43) | 3)
#define MT8167_PIN_43_KPCOL1__FUNC_TSF_IN (MTK_PIN_NO(43) | 4)
#define MT8167_PIN_43_KPCOL1__FUNC_DFD_NTRST_XI (MTK_PIN_NO(43) | 5)
#define MT8167_PIN_43_KPCOL1__FUNC_UDI_NTRST_XI (MTK_PIN_NO(43) | 6)
#define MT8167_PIN_43_KPCOL1__FUNC_DBG_MON_B_7 (MTK_PIN_NO(43) | 7)
#define MT8167_PIN_44_JTMS__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
#define MT8167_PIN_44_JTMS__FUNC_JTMS (MTK_PIN_NO(44) | 1)
#define MT8167_PIN_44_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(44) | 2)
#define MT8167_PIN_44_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(44) | 3)
#define MT8167_PIN_44_JTMS__FUNC_GPUDFD_TMS_XI (MTK_PIN_NO(44) | 4)
#define MT8167_PIN_44_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(44) | 5)
#define MT8167_PIN_44_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(44) | 6)
#define MT8167_PIN_45_JTCK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
#define MT8167_PIN_45_JTCK__FUNC_JTCK (MTK_PIN_NO(45) | 1)
#define MT8167_PIN_45_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(45) | 2)
#define MT8167_PIN_45_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(45) | 3)
#define MT8167_PIN_45_JTCK__FUNC_GPUDFD_TCK_XI (MTK_PIN_NO(45) | 4)
#define MT8167_PIN_45_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(45) | 5)
#define MT8167_PIN_45_JTCK__FUNC_UDI_TCK_XI (MTK_PIN_NO(45) | 6)
#define MT8167_PIN_46_JTDI__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
#define MT8167_PIN_46_JTDI__FUNC_JTDI (MTK_PIN_NO(46) | 1)
#define MT8167_PIN_46_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(46) | 2)
#define MT8167_PIN_46_JTDI__FUNC_GPUDFD_TDI_XI (MTK_PIN_NO(46) | 4)
#define MT8167_PIN_46_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(46) | 5)
#define MT8167_PIN_46_JTDI__FUNC_UDI_TDI_XI (MTK_PIN_NO(46) | 6)
#define MT8167_PIN_47_JTDO__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
#define MT8167_PIN_47_JTDO__FUNC_JTDO (MTK_PIN_NO(47) | 1)
#define MT8167_PIN_47_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(47) | 2)
#define MT8167_PIN_47_JTDO__FUNC_GPUDFD_TDO (MTK_PIN_NO(47) | 4)
#define MT8167_PIN_47_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(47) | 5)
#define MT8167_PIN_47_JTDO__FUNC_UDI_TDO (MTK_PIN_NO(47) | 6)
#define MT8167_PIN_48_SPI_CS__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
#define MT8167_PIN_48_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(48) | 1)
#define MT8167_PIN_48_SPI_CS__FUNC_I2S0_DI (MTK_PIN_NO(48) | 3)
#define MT8167_PIN_48_SPI_CS__FUNC_I2S2_BCK (MTK_PIN_NO(48) | 4)
#define MT8167_PIN_48_SPI_CS__FUNC_DBG_MON_A_23 (MTK_PIN_NO(48) | 7)
#define MT8167_PIN_49_SPI_CK__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
#define MT8167_PIN_49_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(49) | 1)
#define MT8167_PIN_49_SPI_CK__FUNC_I2S0_LRCK (MTK_PIN_NO(49) | 3)
#define MT8167_PIN_49_SPI_CK__FUNC_I2S2_DI (MTK_PIN_NO(49) | 4)
#define MT8167_PIN_49_SPI_CK__FUNC_DBG_MON_A_24 (MTK_PIN_NO(49) | 7)
#define MT8167_PIN_50_SPI_MI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
#define MT8167_PIN_50_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(50) | 1)
#define MT8167_PIN_50_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(50) | 2)
#define MT8167_PIN_50_SPI_MI__FUNC_I2S0_BCK (MTK_PIN_NO(50) | 3)
#define MT8167_PIN_50_SPI_MI__FUNC_I2S2_LRCK (MTK_PIN_NO(50) | 4)
#define MT8167_PIN_50_SPI_MI__FUNC_DBG_MON_A_25 (MTK_PIN_NO(50) | 7)
#define MT8167_PIN_51_SPI_MO__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
#define MT8167_PIN_51_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(51) | 1)
#define MT8167_PIN_51_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(51) | 2)
#define MT8167_PIN_51_SPI_MO__FUNC_I2S0_MCK (MTK_PIN_NO(51) | 3)
#define MT8167_PIN_51_SPI_MO__FUNC_I2S2_MCK (MTK_PIN_NO(51) | 4)
#define MT8167_PIN_51_SPI_MO__FUNC_DBG_MON_A_26 (MTK_PIN_NO(51) | 7)
#define MT8167_PIN_52_SDA1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
#define MT8167_PIN_52_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(52) | 1)
#define MT8167_PIN_53_SCL1__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
#define MT8167_PIN_53_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(53) | 1)
#define MT8167_PIN_54_DISP_PWM__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
#define MT8167_PIN_54_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(54) | 1)
#define MT8167_PIN_54_DISP_PWM__FUNC_PWM_B (MTK_PIN_NO(54) | 2)
#define MT8167_PIN_54_DISP_PWM__FUNC_DBG_MON_B_2 (MTK_PIN_NO(54) | 7)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(55) | 1)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_UCTS0 (MTK_PIN_NO(55) | 2)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(55) | 3)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(55) | 4)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(55) | 5)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S2_BCK (MTK_PIN_NO(55) | 6)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_DBG_MON_A_28 (MTK_PIN_NO(55) | 7)
#define MT8167_PIN_56_I2S_LRCK__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(56) | 1)
#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(56) | 3)
#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(56) | 4)
#define MT8167_PIN_56_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(56) | 5)
#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S2_DI (MTK_PIN_NO(56) | 6)
#define MT8167_PIN_56_I2S_LRCK__FUNC_DBG_MON_A_29 (MTK_PIN_NO(56) | 7)
#define MT8167_PIN_57_I2S_BCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
#define MT8167_PIN_57_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(57) | 1)
#define MT8167_PIN_57_I2S_BCK__FUNC_URTS0 (MTK_PIN_NO(57) | 2)
#define MT8167_PIN_57_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(57) | 3)
#define MT8167_PIN_57_I2S_BCK__FUNC_I2S_8CH_BCK (MTK_PIN_NO(57) | 4)
#define MT8167_PIN_57_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(57) | 5)
#define MT8167_PIN_57_I2S_BCK__FUNC_I2S2_LRCK (MTK_PIN_NO(57) | 6)
#define MT8167_PIN_57_I2S_BCK__FUNC_DBG_MON_A_30 (MTK_PIN_NO(57) | 7)
#define MT8167_PIN_58_SDA0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
#define MT8167_PIN_58_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(58) | 1)
#define MT8167_PIN_59_SCL0__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
#define MT8167_PIN_59_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(59) | 1)
#define MT8167_PIN_60_SDA2__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
#define MT8167_PIN_60_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(60) | 1)
#define MT8167_PIN_60_SDA2__FUNC_PWM_B (MTK_PIN_NO(60) | 2)
#define MT8167_PIN_61_SCL2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
#define MT8167_PIN_61_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(61) | 1)
#define MT8167_PIN_61_SCL2__FUNC_PWM_C (MTK_PIN_NO(61) | 2)
#define MT8167_PIN_62_URXD0__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
#define MT8167_PIN_62_URXD0__FUNC_URXD0 (MTK_PIN_NO(62) | 1)
#define MT8167_PIN_62_URXD0__FUNC_UTXD0 (MTK_PIN_NO(62) | 2)
#define MT8167_PIN_63_UTXD0__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
#define MT8167_PIN_63_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(63) | 1)
#define MT8167_PIN_63_UTXD0__FUNC_URXD0 (MTK_PIN_NO(63) | 2)
#define MT8167_PIN_64_URXD1__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
#define MT8167_PIN_64_URXD1__FUNC_URXD1 (MTK_PIN_NO(64) | 1)
#define MT8167_PIN_64_URXD1__FUNC_UTXD1 (MTK_PIN_NO(64) | 2)
#define MT8167_PIN_64_URXD1__FUNC_DBG_MON_A_27 (MTK_PIN_NO(64) | 7)
#define MT8167_PIN_65_UTXD1__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
#define MT8167_PIN_65_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(65) | 1)
#define MT8167_PIN_65_UTXD1__FUNC_URXD1 (MTK_PIN_NO(65) | 2)
#define MT8167_PIN_65_UTXD1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(65) | 7)
#define MT8167_PIN_66_LCM_RST__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
#define MT8167_PIN_66_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(66) | 1)
#define MT8167_PIN_66_LCM_RST__FUNC_I2S0_MCK (MTK_PIN_NO(66) | 3)
#define MT8167_PIN_66_LCM_RST__FUNC_DBG_MON_B_3 (MTK_PIN_NO(66) | 7)
#define MT8167_PIN_67_DSI_TE__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
#define MT8167_PIN_67_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(67) | 1)
#define MT8167_PIN_67_DSI_TE__FUNC_I2S_8CH_MCK (MTK_PIN_NO(67) | 3)
#define MT8167_PIN_67_DSI_TE__FUNC_DBG_MON_B_14 (MTK_PIN_NO(67) | 7)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(68) | 1)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(68) | 2)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_SDA1_0 (MTK_PIN_NO(68) | 3)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_USB_SDA (MTK_PIN_NO(68) | 5)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_I2S3_BCK (MTK_PIN_NO(68) | 6)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_DBG_MON_B_15 (MTK_PIN_NO(68) | 7)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(69) | 1)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(69) | 2)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_SCL1_0 (MTK_PIN_NO(69) | 3)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_DPI_D21 (MTK_PIN_NO(69) | 4)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_USB_SCL (MTK_PIN_NO(69) | 5)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_I2S3_LRCK (MTK_PIN_NO(69) | 6)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_DBG_MON_B_16 (MTK_PIN_NO(69) | 7)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(70) | 1)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(70) | 2)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_DPI_D22 (MTK_PIN_NO(70) | 4)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_UTXD0 (MTK_PIN_NO(70) | 5)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_I2S3_DO (MTK_PIN_NO(70) | 6)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(70) | 7)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(71) | 1)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(71) | 2)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_PWM_A (MTK_PIN_NO(71) | 3)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_I2S3_MCK (MTK_PIN_NO(71) | 4)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_URXD0 (MTK_PIN_NO(71) | 5)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_PWM_B (MTK_PIN_NO(71) | 6)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_DBG_MON_B_18 (MTK_PIN_NO(71) | 7)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(72) | 1)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(72) | 2)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_SDA2_0 (MTK_PIN_NO(72) | 3)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_DPI_D23 (MTK_PIN_NO(72) | 4)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_UTXD1 (MTK_PIN_NO(72) | 5)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_PWM_C (MTK_PIN_NO(72) | 6)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_DBG_MON_B_19 (MTK_PIN_NO(72) | 7)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(73) | 1)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_I2S_8CH_BCK (MTK_PIN_NO(73) | 2)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_SCL2_0 (MTK_PIN_NO(73) | 3)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(73) | 4)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_URXD1 (MTK_PIN_NO(73) | 5)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_PWM_A (MTK_PIN_NO(73) | 6)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_DBG_MON_B_20 (MTK_PIN_NO(73) | 7)
#define MT8167_PIN_74_TDN3__FUNC_GPI74 (MTK_PIN_NO(74) | 0)
#define MT8167_PIN_74_TDN3__FUNC_TDN3 (MTK_PIN_NO(74) | 1)
#define MT8167_PIN_75_TDP3__FUNC_GPI75 (MTK_PIN_NO(75) | 0)
#define MT8167_PIN_75_TDP3__FUNC_TDP3 (MTK_PIN_NO(75) | 1)
#define MT8167_PIN_76_TDN2__FUNC_GPI76 (MTK_PIN_NO(76) | 0)
#define MT8167_PIN_76_TDN2__FUNC_TDN2 (MTK_PIN_NO(76) | 1)
#define MT8167_PIN_77_TDP2__FUNC_GPI77 (MTK_PIN_NO(77) | 0)
#define MT8167_PIN_77_TDP2__FUNC_TDP2 (MTK_PIN_NO(77) | 1)
#define MT8167_PIN_78_TCN__FUNC_GPI78 (MTK_PIN_NO(78) | 0)
#define MT8167_PIN_78_TCN__FUNC_TCN (MTK_PIN_NO(78) | 1)
#define MT8167_PIN_79_TCP__FUNC_GPI79 (MTK_PIN_NO(79) | 0)
#define MT8167_PIN_79_TCP__FUNC_TCP (MTK_PIN_NO(79) | 1)
#define MT8167_PIN_80_TDN1__FUNC_GPI80 (MTK_PIN_NO(80) | 0)
#define MT8167_PIN_80_TDN1__FUNC_TDN1 (MTK_PIN_NO(80) | 1)
#define MT8167_PIN_81_TDP1__FUNC_GPI81 (MTK_PIN_NO(81) | 0)
#define MT8167_PIN_81_TDP1__FUNC_TDP1 (MTK_PIN_NO(81) | 1)
#define MT8167_PIN_82_TDN0__FUNC_GPI82 (MTK_PIN_NO(82) | 0)
#define MT8167_PIN_82_TDN0__FUNC_TDN0 (MTK_PIN_NO(82) | 1)
#define MT8167_PIN_83_TDP0__FUNC_GPI83 (MTK_PIN_NO(83) | 0)
#define MT8167_PIN_83_TDP0__FUNC_TDP0 (MTK_PIN_NO(83) | 1)
#define MT8167_PIN_84_RDN0__FUNC_GPI84 (MTK_PIN_NO(84) | 0)
#define MT8167_PIN_84_RDN0__FUNC_RDN0 (MTK_PIN_NO(84) | 1)
#define MT8167_PIN_85_RDP0__FUNC_GPI85 (MTK_PIN_NO(85) | 0)
#define MT8167_PIN_85_RDP0__FUNC_RDP0 (MTK_PIN_NO(85) | 1)
#define MT8167_PIN_86_RDN1__FUNC_GPI86 (MTK_PIN_NO(86) | 0)
#define MT8167_PIN_86_RDN1__FUNC_RDN1 (MTK_PIN_NO(86) | 1)
#define MT8167_PIN_87_RDP1__FUNC_GPI87 (MTK_PIN_NO(87) | 0)
#define MT8167_PIN_87_RDP1__FUNC_RDP1 (MTK_PIN_NO(87) | 1)
#define MT8167_PIN_88_RCN__FUNC_GPI88 (MTK_PIN_NO(88) | 0)
#define MT8167_PIN_88_RCN__FUNC_RCN (MTK_PIN_NO(88) | 1)
#define MT8167_PIN_89_RCP__FUNC_GPI89 (MTK_PIN_NO(89) | 0)
#define MT8167_PIN_89_RCP__FUNC_RCP (MTK_PIN_NO(89) | 1)
#define MT8167_PIN_90_RDN2__FUNC_GPI90 (MTK_PIN_NO(90) | 0)
#define MT8167_PIN_90_RDN2__FUNC_RDN2 (MTK_PIN_NO(90) | 1)
#define MT8167_PIN_90_RDN2__FUNC_CMDAT8 (MTK_PIN_NO(90) | 2)
#define MT8167_PIN_91_RDP2__FUNC_GPI91 (MTK_PIN_NO(91) | 0)
#define MT8167_PIN_91_RDP2__FUNC_RDP2 (MTK_PIN_NO(91) | 1)
#define MT8167_PIN_91_RDP2__FUNC_CMDAT9 (MTK_PIN_NO(91) | 2)
#define MT8167_PIN_92_RDN3__FUNC_GPI92 (MTK_PIN_NO(92) | 0)
#define MT8167_PIN_92_RDN3__FUNC_RDN3 (MTK_PIN_NO(92) | 1)
#define MT8167_PIN_92_RDN3__FUNC_CMDAT4 (MTK_PIN_NO(92) | 2)
#define MT8167_PIN_93_RDP3__FUNC_GPI93 (MTK_PIN_NO(93) | 0)
#define MT8167_PIN_93_RDP3__FUNC_RDP3 (MTK_PIN_NO(93) | 1)
#define MT8167_PIN_93_RDP3__FUNC_CMDAT5 (MTK_PIN_NO(93) | 2)
#define MT8167_PIN_94_RCN_A__FUNC_GPI94 (MTK_PIN_NO(94) | 0)
#define MT8167_PIN_94_RCN_A__FUNC_RCN_A (MTK_PIN_NO(94) | 1)
#define MT8167_PIN_94_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(94) | 2)
#define MT8167_PIN_95_RCP_A__FUNC_GPI95 (MTK_PIN_NO(95) | 0)
#define MT8167_PIN_95_RCP_A__FUNC_RCP_A (MTK_PIN_NO(95) | 1)
#define MT8167_PIN_95_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(95) | 2)
#define MT8167_PIN_96_RDN1_A__FUNC_GPI96 (MTK_PIN_NO(96) | 0)
#define MT8167_PIN_96_RDN1_A__FUNC_RDN1_A (MTK_PIN_NO(96) | 1)
#define MT8167_PIN_96_RDN1_A__FUNC_CMDAT2 (MTK_PIN_NO(96) | 2)
#define MT8167_PIN_96_RDN1_A__FUNC_CMCSD2 (MTK_PIN_NO(96) | 3)
#define MT8167_PIN_97_RDP1_A__FUNC_GPI97 (MTK_PIN_NO(97) | 0)
#define MT8167_PIN_97_RDP1_A__FUNC_RDP1_A (MTK_PIN_NO(97) | 1)
#define MT8167_PIN_97_RDP1_A__FUNC_CMDAT3 (MTK_PIN_NO(97) | 2)
#define MT8167_PIN_97_RDP1_A__FUNC_CMCSD3 (MTK_PIN_NO(97) | 3)
#define MT8167_PIN_98_RDN0_A__FUNC_GPI98 (MTK_PIN_NO(98) | 0)
#define MT8167_PIN_98_RDN0_A__FUNC_RDN0_A (MTK_PIN_NO(98) | 1)
#define MT8167_PIN_98_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(98) | 2)
#define MT8167_PIN_99_RDP0_A__FUNC_GPI99 (MTK_PIN_NO(99) | 0)
#define MT8167_PIN_99_RDP0_A__FUNC_RDP0_A (MTK_PIN_NO(99) | 1)
#define MT8167_PIN_99_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(99) | 2)
#define MT8167_PIN_100_CMDAT0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
#define MT8167_PIN_100_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(100) | 1)
#define MT8167_PIN_100_CMDAT0__FUNC_CMCSD0 (MTK_PIN_NO(100) | 2)
#define MT8167_PIN_100_CMDAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(100) | 3)
#define MT8167_PIN_100_CMDAT0__FUNC_TDM_RX_MCK (MTK_PIN_NO(100) | 5)
#define MT8167_PIN_100_CMDAT0__FUNC_DBG_MON_B_21 (MTK_PIN_NO(100) | 7)
#define MT8167_PIN_101_CMDAT1__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
#define MT8167_PIN_101_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(101) | 1)
#define MT8167_PIN_101_CMDAT1__FUNC_CMCSD1 (MTK_PIN_NO(101) | 2)
#define MT8167_PIN_101_CMDAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(101) | 3)
#define MT8167_PIN_101_CMDAT1__FUNC_CMFLASH (MTK_PIN_NO(101) | 4)
#define MT8167_PIN_101_CMDAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(101) | 5)
#define MT8167_PIN_101_CMDAT1__FUNC_DBG_MON_B_22 (MTK_PIN_NO(101) | 7)
#define MT8167_PIN_102_CMMCLK__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
#define MT8167_PIN_102_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(102) | 1)
#define MT8167_PIN_102_CMMCLK__FUNC_ANT_SEL4 (MTK_PIN_NO(102) | 3)
#define MT8167_PIN_102_CMMCLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(102) | 5)
#define MT8167_PIN_102_CMMCLK__FUNC_DBG_MON_B_23 (MTK_PIN_NO(102) | 7)
#define MT8167_PIN_103_CMPCLK__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
#define MT8167_PIN_103_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(103) | 1)
#define MT8167_PIN_103_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(103) | 2)
#define MT8167_PIN_103_CMPCLK__FUNC_ANT_SEL5 (MTK_PIN_NO(103) | 3)
#define MT8167_PIN_103_CMPCLK__FUNC_TDM_RX_DI (MTK_PIN_NO(103) | 5)
#define MT8167_PIN_103_CMPCLK__FUNC_DBG_MON_B_24 (MTK_PIN_NO(103) | 7)
#define MT8167_PIN_104_MSDC1_CMD__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
#define MT8167_PIN_104_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(104) | 1)
#define MT8167_PIN_104_MSDC1_CMD__FUNC_SQICS (MTK_PIN_NO(104) | 4)
#define MT8167_PIN_104_MSDC1_CMD__FUNC_DBG_MON_B_25 (MTK_PIN_NO(104) | 7)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(105) | 1)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_UDI_NTRST_XI (MTK_PIN_NO(105) | 2)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_DFD_NTRST_XI (MTK_PIN_NO(105) | 3)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_SQISO (MTK_PIN_NO(105) | 4)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_GPUEJ_NTRST_XI (MTK_PIN_NO(105) | 5)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_DBG_MON_B_26 (MTK_PIN_NO(105) | 7)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(106) | 1)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_UDI_TMS_XI (MTK_PIN_NO(106) | 2)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_DFD_TMS_XI (MTK_PIN_NO(106) | 3)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_SQISI (MTK_PIN_NO(106) | 4)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_GPUEJ_TMS_XI (MTK_PIN_NO(106) | 5)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_DBG_MON_B_27 (MTK_PIN_NO(106) | 7)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(107) | 1)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_UDI_TCK_XI (MTK_PIN_NO(107) | 2)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_DFD_TCK_XI (MTK_PIN_NO(107) | 3)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_SQIWP (MTK_PIN_NO(107) | 4)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_GPUEJ_TCK_XI (MTK_PIN_NO(107) | 5)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_DBG_MON_B_28 (MTK_PIN_NO(107) | 7)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(108) | 1)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_UDI_TDI_XI (MTK_PIN_NO(108) | 2)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_DFD_TDI_XI (MTK_PIN_NO(108) | 3)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_SQIRST (MTK_PIN_NO(108) | 4)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_GPUEJ_TDI_XI (MTK_PIN_NO(108) | 5)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_DBG_MON_B_29 (MTK_PIN_NO(108) | 7)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(109) | 1)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_UDI_TDO (MTK_PIN_NO(109) | 2)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_DFD_TDO (MTK_PIN_NO(109) | 3)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_SQICK (MTK_PIN_NO(109) | 4)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_GPUEJ_TDO (MTK_PIN_NO(109) | 5)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_DBG_MON_B_30 (MTK_PIN_NO(109) | 7)
#define MT8167_PIN_110_MSDC0_DAT7__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
#define MT8167_PIN_110_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(110) | 1)
#define MT8167_PIN_110_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(110) | 4)
#define MT8167_PIN_111_MSDC0_DAT6__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
#define MT8167_PIN_111_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(111) | 1)
#define MT8167_PIN_111_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(111) | 4)
#define MT8167_PIN_112_MSDC0_DAT5__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
#define MT8167_PIN_112_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(112) | 1)
#define MT8167_PIN_112_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(112) | 4)
#define MT8167_PIN_113_MSDC0_DAT4__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
#define MT8167_PIN_113_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(113) | 1)
#define MT8167_PIN_113_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(113) | 4)
#define MT8167_PIN_114_MSDC0_RSTB__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
#define MT8167_PIN_114_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(114) | 1)
#define MT8167_PIN_114_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(114) | 4)
#define MT8167_PIN_115_MSDC0_CMD__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
#define MT8167_PIN_115_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(115) | 1)
#define MT8167_PIN_115_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(115) | 4)
#define MT8167_PIN_116_MSDC0_CLK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
#define MT8167_PIN_116_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(116) | 1)
#define MT8167_PIN_116_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(116) | 4)
#define MT8167_PIN_117_MSDC0_DAT3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
#define MT8167_PIN_117_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(117) | 1)
#define MT8167_PIN_117_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(117) | 4)
#define MT8167_PIN_118_MSDC0_DAT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
#define MT8167_PIN_118_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(118) | 1)
#define MT8167_PIN_118_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(118) | 4)
#define MT8167_PIN_119_MSDC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
#define MT8167_PIN_119_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(119) | 1)
#define MT8167_PIN_119_MSDC0_DAT1__FUNC_NLD8 (MTK_PIN_NO(119) | 4)
#define MT8167_PIN_120_MSDC0_DAT0__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
#define MT8167_PIN_120_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(120) | 1)
#define MT8167_PIN_120_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(120) | 4)
#define MT8167_PIN_120_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(120) | 5)
#define MT8167_PIN_121_CEC__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
#define MT8167_PIN_121_CEC__FUNC_CEC (MTK_PIN_NO(121) | 1)
#define MT8167_PIN_122_HTPLG__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
#define MT8167_PIN_122_HTPLG__FUNC_HTPLG (MTK_PIN_NO(122) | 1)
#define MT8167_PIN_123_HDMISCK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
#define MT8167_PIN_123_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(123) | 1)
#define MT8167_PIN_124_HDMISD__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
#define MT8167_PIN_124_HDMISD__FUNC_HDMISD (MTK_PIN_NO(124) | 1)
#endif /* __DTS_MT8167_PINFUNC_H */

20
arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts Normal file
View file

@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 BayLibre, SAS.
* Author: Fabien Parent <fparent@baylibre.com>
*/
/dts-v1/;
#include "mt8167.dtsi"
#include "pumpkin-common.dtsi"
/ {
model = "Pumpkin MT8167";
compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167";
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x80000000>;
};
};

61
arch/arm64/boot/dts/mediatek/mt8167.dtsi Normal file
View file

@ -0,0 +1,61 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 MediaTek Inc.
* Copyright (c) 2020 BayLibre, SAS.
* Author: Fabien Parent <fparent@baylibre.com>
*/
#include <dt-bindings/clock/mt8167-clk.h>
#include <dt-bindings/memory/mt8167-larb-port.h>
#include "mt8167-pinfunc.h"
#include "mt8516.dtsi"
/ {
compatible = "mediatek,mt8167";
soc {
topckgen: topckgen@10000000 {
compatible = "mediatek,mt8167-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infracfg: infracfg@10001000 {
compatible = "mediatek,mt8167-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
};
apmixedsys: apmixedsys@10018000 {
compatible = "mediatek,mt8167-apmixedsys", "syscon";
reg = <0 0x10018000 0 0x710>;
#clock-cells = <1>;
};
imgsys: syscon@15000000 {
compatible = "mediatek,mt8167-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
};
vdecsys: syscon@16000000 {
compatible = "mediatek,mt8167-vdecsys", "syscon";
reg = <0 0x16000000 0 0x1000>;
#clock-cells = <1>;
};
pio: pinctrl@1000b000 {
compatible = "mediatek,mt8167-pinctrl";
reg = <0 0x1000b000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl>;
pins-are-numbered;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
};
};
};

1
arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
View file

@ -87,7 +87,6 @@ volume_up {
panel: panel {
compatible = "lg,lp120up1";
power-supply = <&panel_fixed_3v3>;
ddc-i2c-bus = <&i2c0>;
backlight = <&backlight>;
port {

164
arch/arm64/boot/dts/mediatek/mt8173.dtsi
View file

@ -450,16 +450,82 @@ pins1 {
};
};
scpsys: power-controller@10006000 {
compatible = "mediatek,mt8173-scpsys";
#power-domain-cells = <1>;
scpsys: syscon@10006000 {
compatible = "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
clocks = <&clk26m>,
<&topckgen CLK_TOP_MM_SEL>,
<&topckgen CLK_TOP_VENC_SEL>,
<&topckgen CLK_TOP_VENC_LT_SEL>;
clock-names = "mfg", "mm", "venc", "venc_lt";
infracfg = <&infracfg>;
#power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
compatible = "mediatek,mt8173-power-controller";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
/* power domains of the SoC */
power-domain@MT8173_POWER_DOMAIN_VDEC {
reg = <MT8173_POWER_DOMAIN_VDEC>;
clocks = <&topckgen CLK_TOP_MM_SEL>;
clock-names = "mm";
#power-domain-cells = <0>;
};
power-domain@MT8173_POWER_DOMAIN_VENC {
reg = <MT8173_POWER_DOMAIN_VENC>;
clocks = <&topckgen CLK_TOP_MM_SEL>,
<&topckgen CLK_TOP_VENC_SEL>;
clock-names = "mm", "venc";
#power-domain-cells = <0>;
};
power-domain@MT8173_POWER_DOMAIN_ISP {
reg = <MT8173_POWER_DOMAIN_ISP>;
clocks = <&topckgen CLK_TOP_MM_SEL>;
clock-names = "mm";
#power-domain-cells = <0>;
};
power-domain@MT8173_POWER_DOMAIN_MM {
reg = <MT8173_POWER_DOMAIN_MM>;
clocks = <&topckgen CLK_TOP_MM_SEL>;
clock-names = "mm";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8173_POWER_DOMAIN_VENC_LT {
reg = <MT8173_POWER_DOMAIN_VENC_LT>;
clocks = <&topckgen CLK_TOP_MM_SEL>,
<&topckgen CLK_TOP_VENC_LT_SEL>;
clock-names = "mm", "venclt";
#power-domain-cells = <0>;
};
power-domain@MT8173_POWER_DOMAIN_AUDIO {
reg = <MT8173_POWER_DOMAIN_AUDIO>;
#power-domain-cells = <0>;
};
power-domain@MT8173_POWER_DOMAIN_USB {
reg = <MT8173_POWER_DOMAIN_USB>;
#power-domain-cells = <0>;
};
power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
clocks = <&clk26m>;
clock-names = "mfg";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8173_POWER_DOMAIN_MFG_2D {
reg = <MT8173_POWER_DOMAIN_MFG_2D>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8173_POWER_DOMAIN_MFG {
reg = <MT8173_POWER_DOMAIN_MFG>;
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
};
};
};
};
watchdog: watchdog@10007000 {
@ -792,7 +858,7 @@ afe: audio-controller@11220000 {
compatible = "mediatek,mt8173-afe-pcm";
reg = <0 0x11220000 0 0x1000>;
interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>;
clocks = <&infracfg CLK_INFRA_AUDIO>,
<&topckgen CLK_TOP_AUDIO_SEL>,
<&topckgen CLK_TOP_AUD_INTBUS_SEL>,
@ -868,7 +934,7 @@ ssusb: usb@11271000 {
phys = <&u2port0 PHY_TYPE_USB2>,
<&u3port0 PHY_TYPE_USB3>,
<&u2port1 PHY_TYPE_USB2>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
clock-names = "sys_ck", "ref_ck";
mediatek,syscon-wakeup = <&pericfg 0x400 1>;
@ -882,7 +948,7 @@ usb_host: xhci@11270000 {
reg = <0 0x11270000 0 0x1000>;
reg-names = "mac";
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
clock-names = "sys_ck", "ref_ck";
status = "disabled";
@ -925,7 +991,7 @@ u2port1: usb-phy@11291000 {
mmsys: syscon@14000000 {
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
assigned-clock-rates = <400000000>;
#clock-cells = <1>;
@ -940,7 +1006,7 @@ mdp_rdma0: rdma@14001000 {
reg = <0 0x14001000 0 0x1000>;
clocks = <&mmsys CLK_MM_MDP_RDMA0>,
<&mmsys CLK_MM_MUTEX_32K>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_RDMA0>;
mediatek,larb = <&larb0>;
mediatek,vpu = <&vpu>;
@ -951,7 +1017,7 @@ mdp_rdma1: rdma@14002000 {
reg = <0 0x14002000 0 0x1000>;
clocks = <&mmsys CLK_MM_MDP_RDMA1>,
<&mmsys CLK_MM_MUTEX_32K>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_RDMA1>;
mediatek,larb = <&larb4>;
};
@ -960,28 +1026,28 @@ mdp_rsz0: rsz@14003000 {
compatible = "mediatek,mt8173-mdp-rsz";
reg = <0 0x14003000 0 0x1000>;
clocks = <&mmsys CLK_MM_MDP_RSZ0>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
};
mdp_rsz1: rsz@14004000 {
compatible = "mediatek,mt8173-mdp-rsz";
reg = <0 0x14004000 0 0x1000>;
clocks = <&mmsys CLK_MM_MDP_RSZ1>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
};
mdp_rsz2: rsz@14005000 {
compatible = "mediatek,mt8173-mdp-rsz";
reg = <0 0x14005000 0 0x1000>;
clocks = <&mmsys CLK_MM_MDP_RSZ2>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
};
mdp_wdma0: wdma@14006000 {
compatible = "mediatek,mt8173-mdp-wdma";
reg = <0 0x14006000 0 0x1000>;
clocks = <&mmsys CLK_MM_MDP_WDMA>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WDMA>;
mediatek,larb = <&larb0>;
};
@ -990,7 +1056,7 @@ mdp_wrot0: wrot@14007000 {
compatible = "mediatek,mt8173-mdp-wrot";
reg = <0 0x14007000 0 0x1000>;
clocks = <&mmsys CLK_MM_MDP_WROT0>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WROT0>;
mediatek,larb = <&larb0>;
};
@ -999,7 +1065,7 @@ mdp_wrot1: wrot@14008000 {
compatible = "mediatek,mt8173-mdp-wrot";
reg = <0 0x14008000 0 0x1000>;
clocks = <&mmsys CLK_MM_MDP_WROT1>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WROT1>;
mediatek,larb = <&larb4>;
};
@ -1008,7 +1074,7 @@ ovl0: ovl@1400c000 {
compatible = "mediatek,mt8173-disp-ovl";
reg = <0 0x1400c000 0 0x1000>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_OVL0>;
iommus = <&iommu M4U_PORT_DISP_OVL0>;
mediatek,larb = <&larb0>;
@ -1019,7 +1085,7 @@ ovl1: ovl@1400d000 {
compatible = "mediatek,mt8173-disp-ovl";
reg = <0 0x1400d000 0 0x1000>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_OVL1>;
iommus = <&iommu M4U_PORT_DISP_OVL1>;
mediatek,larb = <&larb4>;
@ -1030,7 +1096,7 @@ rdma0: rdma@1400e000 {
compatible = "mediatek,mt8173-disp-rdma";
reg = <0 0x1400e000 0 0x1000>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
mediatek,larb = <&larb0>;
@ -1041,7 +1107,7 @@ rdma1: rdma@1400f000 {
compatible = "mediatek,mt8173-disp-rdma";
reg = <0 0x1400f000 0 0x1000>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
mediatek,larb = <&larb4>;
@ -1052,7 +1118,7 @@ rdma2: rdma@14010000 {
compatible = "mediatek,mt8173-disp-rdma";
reg = <0 0x14010000 0 0x1000>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA2>;
iommus = <&iommu M4U_PORT_DISP_RDMA2>;
mediatek,larb = <&larb4>;
@ -1063,7 +1129,7 @@ wdma0: wdma@14011000 {
compatible = "mediatek,mt8173-disp-wdma";
reg = <0 0x14011000 0 0x1000>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
mediatek,larb = <&larb0>;
@ -1074,7 +1140,7 @@ wdma1: wdma@14012000 {
compatible = "mediatek,mt8173-disp-wdma";
reg = <0 0x14012000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_WDMA1>;
iommus = <&iommu M4U_PORT_DISP_WDMA1>;
mediatek,larb = <&larb4>;
@ -1085,7 +1151,7 @@ color0: color@14013000 {
compatible = "mediatek,mt8173-disp-color";
reg = <0 0x14013000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
};
@ -1094,7 +1160,7 @@ color1: color@14014000 {
compatible = "mediatek,mt8173-disp-color";
reg = <0 0x14014000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_COLOR1>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
};
@ -1103,7 +1169,7 @@ aal@14015000 {
compatible = "mediatek,mt8173-disp-aal";
reg = <0 0x14015000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_AAL>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
};
@ -1112,7 +1178,7 @@ gamma@14016000 {
compatible = "mediatek,mt8173-disp-gamma";
reg = <0 0x14016000 0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
};
@ -1120,21 +1186,21 @@ gamma@14016000 {
merge@14017000 {
compatible = "mediatek,mt8173-disp-merge";
reg = <0 0x14017000 0 0x1000>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_MERGE>;
};
split0: split@14018000 {
compatible = "mediatek,mt8173-disp-split";
reg = <0 0x14018000 0 0x1000>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
};
split1: split@14019000 {
compatible = "mediatek,mt8173-disp-split";
reg = <0 0x14019000 0 0x1000>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
};
@ -1142,7 +1208,7 @@ ufoe@1401a000 {
compatible = "mediatek,mt8173-disp-ufoe";
reg = <0 0x1401a000 0 0x1000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_UFOE>;
};
@ -1150,7 +1216,7 @@ dsi0: dsi@1401b000 {
compatible = "mediatek,mt8173-dsi";
reg = <0 0x1401b000 0 0x1000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
<&mmsys CLK_MM_DSI0_DIGITAL>,
<&mipi_tx0>;
@ -1164,7 +1230,7 @@ dsi1: dsi@1401c000 {
compatible = "mediatek,mt8173-dsi";
reg = <0 0x1401c000 0 0x1000>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
<&mmsys CLK_MM_DSI1_DIGITAL>,
<&mipi_tx1>;
@ -1178,7 +1244,7 @@ dpi0: dpi@1401d000 {
compatible = "mediatek,mt8173-dpi";
reg = <0 0x1401d000 0 0x1000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DPI_PIXEL>,
<&mmsys CLK_MM_DPI_ENGINE>,
<&apmixedsys CLK_APMIXED_TVDPLL>;
@ -1218,7 +1284,7 @@ mutex: mutex@14020000 {
compatible = "mediatek,mt8173-disp-mutex";
reg = <0 0x14020000 0 0x1000>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_MUTEX_32K>;
mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
<CMDQ_EVENT_MUTEX1_STREAM_EOF>;
@ -1228,7 +1294,7 @@ larb0: larb@14021000 {
compatible = "mediatek,mt8173-smi-larb";
reg = <0 0x14021000 0 0x1000>;
mediatek,smi = <&smi_common>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_SMI_LARB0>,
<&mmsys CLK_MM_SMI_LARB0>;
clock-names = "apb", "smi";
@ -1237,7 +1303,7 @@ larb0: larb@14021000 {
smi_common: smi@14022000 {
compatible = "mediatek,mt8173-smi-common";
reg = <0 0x14022000 0 0x1000>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_COMMON>;
clock-names = "apb", "smi";
@ -1285,7 +1351,7 @@ larb4: larb@14027000 {
compatible = "mediatek,mt8173-smi-larb";
reg = <0 0x14027000 0 0x1000>;
mediatek,smi = <&smi_common>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_SMI_LARB4>,
<&mmsys CLK_MM_SMI_LARB4>;
clock-names = "apb", "smi";
@ -1301,7 +1367,7 @@ larb2: larb@15001000 {
compatible = "mediatek,mt8173-smi-larb";
reg = <0 0x15001000 0 0x1000>;
mediatek,smi = <&smi_common>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
power-domains = <&spm MT8173_POWER_DOMAIN_ISP>;
clocks = <&imgsys CLK_IMG_LARB2_SMI>,
<&imgsys CLK_IMG_LARB2_SMI>;
clock-names = "apb", "smi";
@ -1338,7 +1404,7 @@ vcodec_dec: vcodec@16000000 {
<&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
<&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
mediatek,vpu = <&vpu>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
<&topckgen CLK_TOP_UNIVPLL_D2>,
<&topckgen CLK_TOP_CCI400_SEL>,
@ -1370,7 +1436,7 @@ larb1: larb@16010000 {
compatible = "mediatek,mt8173-smi-larb";
reg = <0 0x16010000 0 0x1000>;
mediatek,smi = <&smi_common>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
clocks = <&vdecsys CLK_VDEC_CKEN>,
<&vdecsys CLK_VDEC_LARB_CKEN>;
clock-names = "apb", "smi";
@ -1386,7 +1452,7 @@ larb3: larb@18001000 {
compatible = "mediatek,mt8173-smi-larb";
reg = <0 0x18001000 0 0x1000>;
mediatek,smi = <&smi_common>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
clocks = <&vencsys CLK_VENC_CKE1>,
<&vencsys CLK_VENC_CKE0>;
clock-names = "apb", "smi";
@ -1443,7 +1509,7 @@ jpegdec: jpegdec@18004000 {
<&vencsys CLK_VENC_CKE3>;
clock-names = "jpgdec-smi",
"jpgdec";
power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
mediatek,larb = <&larb3>;
iommus = <&iommu M4U_PORT_JPGDEC_WDMA>,
<&iommu M4U_PORT_JPGDEC_BSDMA>;
@ -1459,7 +1525,7 @@ larb5: larb@19001000 {
compatible = "mediatek,mt8173-smi-larb";
reg = <0 0x19001000 0 0x1000>;
mediatek,smi = <&smi_common>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;
clocks = <&vencltsys CLK_VENCLT_CKE1>,
<&vencltsys CLK_VENCLT_CKE0>;
clock-names = "apb", "smi";

28
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View file

@ -19,6 +19,17 @@ chosen {
stdout-path = "serial0:115200n8";
};
backlight_lcd0: backlight_lcd0 {
compatible = "pwm-backlight";
pwms = <&pwm0 0 500000>;
power-supply = <&bl_pp5000>;
enable-gpios = <&pio 176 0>;
brightness-levels = <0 1023>;
num-interpolated-steps = <1023>;
default-brightness-level = <576>;
status = "okay";
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x80000000>;
@ -536,6 +547,17 @@ pins_clk {
};
};
pwm0_pin_default: pwm0_pin_default {
pins1 {
pinmux = <PINMUX_GPIO176__FUNC_GPIO176>;
output-high;
bias-pull-up;
};
pins2 {
pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>;
};
};
scp_pins: scp {
pins_scp_uart {
pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>,
@ -670,6 +692,12 @@ pins_wifi_wakeup {
};
};
&pwm0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin_default>;
};
&scp {
status = "okay";
pinctrl-names = "default";

408
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View file

@ -6,8 +6,11 @@
*/
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/gce/mt8173-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt8183-larb-port.h>
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/reset-controller/mt8183-resets.h>
#include <dt-bindings/phy/phy.h>
#include "mt8183-pinfunc.h"
@ -31,6 +34,11 @@ aliases {
i2c9 = &i2c9;
i2c10 = &i2c10;
i2c11 = &i2c11;
ovl0 = &ovl0;
ovl-2l0 = &ovl_2l0;
ovl-2l1 = &ovl_2l1;
rdma0 = &rdma0;
rdma1 = &rdma1;
};
cpus {
@ -316,6 +324,167 @@ pio: pinctrl@10005000 {
#interrupt-cells = <2>;
};
scpsys: syscon@10006000 {
compatible = "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
#power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
compatible = "mediatek,mt8183-power-controller";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
/* power domain of the SoC */
power-domain@MT8183_POWER_DOMAIN_AUDIO {
reg = <MT8183_POWER_DOMAIN_AUDIO>;
clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
<&infracfg CLK_INFRA_AUDIO>,
<&infracfg CLK_INFRA_AUDIO_26M_BCLK>;
clock-names = "audio", "audio1", "audio2";
#power-domain-cells = <0>;
};
power-domain@MT8183_POWER_DOMAIN_CONN {
reg = <MT8183_POWER_DOMAIN_CONN>;
mediatek,infracfg = <&infracfg>;
#power-domain-cells = <0>;
};
power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC {
reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>;
clocks = <&topckgen CLK_TOP_MUX_MFG>;
clock-names = "mfg";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8183_POWER_DOMAIN_MFG {
reg = <MT8183_POWER_DOMAIN_MFG>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 {
reg = <MT8183_POWER_DOMAIN_MFG_CORE0>;
#power-domain-cells = <0>;
};
power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 {
reg = <MT8183_POWER_DOMAIN_MFG_CORE1>;
#power-domain-cells = <0>;
};
power-domain@MT8183_POWER_DOMAIN_MFG_2D {
reg = <MT8183_POWER_DOMAIN_MFG_2D>;
mediatek,infracfg = <&infracfg>;
#power-domain-cells = <0>;
};
};
};
power-domain@MT8183_POWER_DOMAIN_DISP {
reg = <MT8183_POWER_DOMAIN_DISP>;
clocks = <&topckgen CLK_TOP_MUX_MM>,
<&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_LARB0>,
<&mmsys CLK_MM_SMI_LARB1>,
<&mmsys CLK_MM_GALS_COMM0>,
<&mmsys CLK_MM_GALS_COMM1>,
<&mmsys CLK_MM_GALS_CCU2MM>,
<&mmsys CLK_MM_GALS_IPU12MM>,
<&mmsys CLK_MM_GALS_IMG2MM>,
<&mmsys CLK_MM_GALS_CAM2MM>,
<&mmsys CLK_MM_GALS_IPU2MM>;
clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3",
"mm-4", "mm-5", "mm-6", "mm-7",
"mm-8", "mm-9";
mediatek,infracfg = <&infracfg>;
mediatek,smi = <&smi_common>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8183_POWER_DOMAIN_CAM {
reg = <MT8183_POWER_DOMAIN_CAM>;
clocks = <&topckgen CLK_TOP_MUX_CAM>,
<&camsys CLK_CAM_LARB6>,
<&camsys CLK_CAM_LARB3>,
<&camsys CLK_CAM_SENINF>,
<&camsys CLK_CAM_CAMSV0>,
<&camsys CLK_CAM_CAMSV1>,
<&camsys CLK_CAM_CAMSV2>,
<&camsys CLK_CAM_CCU>;
clock-names = "cam", "cam-0", "cam-1",
"cam-2", "cam-3", "cam-4",
"cam-5", "cam-6";
mediatek,infracfg = <&infracfg>;
mediatek,smi = <&smi_common>;
#power-domain-cells = <0>;
};
power-domain@MT8183_POWER_DOMAIN_ISP {
reg = <MT8183_POWER_DOMAIN_ISP>;
clocks = <&topckgen CLK_TOP_MUX_IMG>,
<&imgsys CLK_IMG_LARB5>,
<&imgsys CLK_IMG_LARB2>;
clock-names = "isp", "isp-0", "isp-1";
mediatek,infracfg = <&infracfg>;
mediatek,smi = <&smi_common>;
#power-domain-cells = <0>;
};
power-domain@MT8183_POWER_DOMAIN_VDEC {
reg = <MT8183_POWER_DOMAIN_VDEC>;
mediatek,smi = <&smi_common>;
#power-domain-cells = <0>;
};
power-domain@MT8183_POWER_DOMAIN_VENC {
reg = <MT8183_POWER_DOMAIN_VENC>;
mediatek,smi = <&smi_common>;
#power-domain-cells = <0>;
};
power-domain@MT8183_POWER_DOMAIN_VPU_TOP {
reg = <MT8183_POWER_DOMAIN_VPU_TOP>;
clocks = <&topckgen CLK_TOP_MUX_IPU_IF>,
<&topckgen CLK_TOP_MUX_DSP>,
<&ipu_conn CLK_IPU_CONN_IPU>,
<&ipu_conn CLK_IPU_CONN_AHB>,
<&ipu_conn CLK_IPU_CONN_AXI>,
<&ipu_conn CLK_IPU_CONN_ISP>,
<&ipu_conn CLK_IPU_CONN_CAM_ADL>,
<&ipu_conn CLK_IPU_CONN_IMG_ADL>;
clock-names = "vpu", "vpu1", "vpu-0", "vpu-1",
"vpu-2", "vpu-3", "vpu-4", "vpu-5";
mediatek,infracfg = <&infracfg>;
mediatek,smi = <&smi_common>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 {
reg = <MT8183_POWER_DOMAIN_VPU_CORE0>;
clocks = <&topckgen CLK_TOP_MUX_DSP1>;
clock-names = "vpu2";
mediatek,infracfg = <&infracfg>;
#power-domain-cells = <0>;
};
power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 {
reg = <MT8183_POWER_DOMAIN_VPU_CORE1>;
clocks = <&topckgen CLK_TOP_MUX_DSP2>;
clock-names = "vpu3";
mediatek,infracfg = <&infracfg>;
#power-domain-cells = <0>;
};
};
};
};
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8183-wdt";
reg = <0 0x10007000 0 0x100>;
@ -359,11 +528,20 @@ systimer: timer@10017000 {
clock-names = "clk13m";
};
iommu: iommu@10205000 {
compatible = "mediatek,mt8183-m4u";
reg = <0 0x10205000 0 0x1000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
mediatek,larbs = <&larb0 &larb1 &larb2 &larb3
&larb4 &larb5 &larb6>;
#iommu-cells = <1>;
};
gce: mailbox@10238000 {
compatible = "mediatek,mt8183-gce";
reg = <0 0x10238000 0 0x4000>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
#mbox-cells = <3>;
#mbox-cells = <2>;
clocks = <&infracfg CLK_INFRA_GCE>;
clock-names = "gce";
};
@ -479,6 +657,16 @@ spi0: spi@1100a000 {
status = "disabled";
};
pwm0: pwm@1100e000 {
compatible = "mediatek,mt8183-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
#pwm-cells = <2>;
clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>,
<&infracfg CLK_INFRA_DISP_PWM>;
clock-names = "main", "mm";
};
i2c3: i2c@1100f000 {
compatible = "mediatek,mt8183-i2c";
reg = <0 0x1100f000 0 0x1000>,
@ -720,10 +908,27 @@ mmc1: mmc@11240000 {
status = "disabled";
};
mipi_tx0: mipi-dphy@11e50000 {
compatible = "mediatek,mt8183-mipi-tx";
reg = <0 0x11e50000 0 0x1000>;
clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>;
clock-names = "ref_clk";
#clock-cells = <0>;
#phy-cells = <0>;
clock-output-names = "mipi_tx0_pll";
nvmem-cells = <&mipi_tx_calibration>;
nvmem-cell-names = "calibration-data";
};
efuse: efuse@11f10000 {
compatible = "mediatek,mt8183-efuse",
"mediatek,efuse";
reg = <0 0x11f10000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
mipi_tx_calibration: calib@190 {
reg = <0x190 0xc>;
};
};
u3phy: usb-phy@11f40000 {
@ -765,24 +970,205 @@ mmsys: syscon@14000000 {
#clock-cells = <1>;
};
ovl0: ovl@14008000 {
compatible = "mediatek,mt8183-disp-ovl";
reg = <0 0x14008000 0 0x1000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL0>;
iommus = <&iommu M4U_PORT_DISP_OVL0>;
mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
};
ovl_2l0: ovl@14009000 {
compatible = "mediatek,mt8183-disp-ovl-2l";
reg = <0 0x14009000 0 0x1000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
};
ovl_2l1: ovl@1400a000 {
compatible = "mediatek,mt8183-disp-ovl-2l";
reg = <0 0x1400a000 0 0x1000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>;
mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
};
rdma0: rdma@1400b000 {
compatible = "mediatek,mt8183-disp-rdma";
reg = <0 0x1400b000 0 0x1000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
mediatek,larb = <&larb0>;
mediatek,rdma_fifo_size = <5120>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
};
rdma1: rdma@1400c000 {
compatible = "mediatek,mt8183-disp-rdma";
reg = <0 0x1400c000 0 0x1000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
mediatek,larb = <&larb0>;
mediatek,rdma_fifo_size = <2048>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
};
color0: color@1400e000 {
compatible = "mediatek,mt8183-disp-color",
"mediatek,mt8173-disp-color";
reg = <0 0x1400e000 0 0x1000>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
};
ccorr0: ccorr@1400f000 {
compatible = "mediatek,mt8183-disp-ccorr";
reg = <0 0x1400f000 0 0x1000>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
};
aal0: aal@14010000 {
compatible = "mediatek,mt8183-disp-aal",
"mediatek,mt8173-disp-aal";
reg = <0 0x14010000 0 0x1000>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_AAL0>;
};
gamma0: gamma@14011000 {
compatible = "mediatek,mt8183-disp-gamma",
"mediatek,mt8173-disp-gamma";
reg = <0 0x14011000 0 0x1000>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
};
dither0: dither@14012000 {
compatible = "mediatek,mt8183-disp-dither";
reg = <0 0x14012000 0 0x1000>;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
};
dsi0: dsi@14014000 {
compatible = "mediatek,mt8183-dsi";
reg = <0 0x14014000 0 0x1000>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
mediatek,syscon-dsi = <&mmsys 0x140>;
clocks = <&mmsys CLK_MM_DSI0_MM>,
<&mmsys CLK_MM_DSI0_IF>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
phys = <&mipi_tx0>;
phy-names = "dphy";
};
mutex: mutex@14016000 {
compatible = "mediatek,mt8183-disp-mutex";
reg = <0 0x14016000 0 0x1000>;
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
};
larb0: larb@14017000 {
compatible = "mediatek,mt8183-smi-larb";
reg = <0 0x14017000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&mmsys CLK_MM_SMI_LARB0>,
<&mmsys CLK_MM_SMI_LARB0>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clock-names = "apb", "smi";
};
smi_common: smi@14019000 {
compatible = "mediatek,mt8183-smi-common", "syscon";
reg = <0 0x14019000 0 0x1000>;
clocks = <&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_GALS_COMM0>,
<&mmsys CLK_MM_GALS_COMM1>;
clock-names = "apb", "smi", "gals0", "gals1";
};
imgsys: syscon@15020000 {
compatible = "mediatek,mt8183-imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;
#clock-cells = <1>;
};
larb5: larb@15021000 {
compatible = "mediatek,mt8183-smi-larb";
reg = <0 0x15021000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>,
<&mmsys CLK_MM_GALS_IMG2MM>;
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
};
larb2: larb@1502f000 {
compatible = "mediatek,mt8183-smi-larb";
reg = <0 0x1502f000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>,
<&mmsys CLK_MM_GALS_IPU2MM>;
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
};
vdecsys: syscon@16000000 {
compatible = "mediatek,mt8183-vdecsys", "syscon";
reg = <0 0x16000000 0 0x1000>;
#clock-cells = <1>;
};
larb1: larb@16010000 {
compatible = "mediatek,mt8183-smi-larb";
reg = <0 0x16010000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>;
clock-names = "apb", "smi";
power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
};
vencsys: syscon@17000000 {
compatible = "mediatek,mt8183-vencsys", "syscon";
reg = <0 0x17000000 0 0x1000>;
#clock-cells = <1>;
};
larb4: larb@17010000 {
compatible = "mediatek,mt8183-smi-larb";
reg = <0 0x17010000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&vencsys CLK_VENC_LARB>,
<&vencsys CLK_VENC_LARB>;
clock-names = "apb", "smi";
power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
};
ipu_conn: syscon@19000000 {
compatible = "mediatek,mt8183-ipu_conn", "syscon";
reg = <0 0x19000000 0 0x1000>;
@ -812,5 +1198,25 @@ camsys: syscon@1a000000 {
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
larb6: larb@1a001000 {
compatible = "mediatek,mt8183-smi-larb";
reg = <0 0x1a001000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>,
<&mmsys CLK_MM_GALS_CAM2MM>;
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
};
larb3: larb@1a002000 {
compatible = "mediatek,mt8183-smi-larb";
reg = <0 0x1a002000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>,
<&mmsys CLK_MM_GALS_IPU12MM>;
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
};
};
};

29
arch/arm64/boot/dts/mediatek/mt8192-evb.dts Normal file
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@ -0,0 +1,29 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2020 MediaTek Inc.
* Author: Seiya Wang <seiya.wang@mediatek.com>
*/
/dts-v1/;
#include "mt8192.dtsi"
/ {
model = "MediaTek MT8192 evaluation board";
compatible = "mediatek,mt8192-evb", "mediatek,mt8192";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:921600n8";
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x80000000>;
};
};
&uart0 {
status = "okay";
};

512
arch/arm64/boot/dts/mediatek/mt8192.dtsi Normal file
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@ -0,0 +1,512 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2020 MediaTek Inc.
* Author: Seiya Wang <seiya.wang@mediatek.com>
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
/ {
compatible = "mediatek,mt8192";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
clk26m: oscillator0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
clk32k: oscillator1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "clk32k";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x000>;
enable-method = "psci";
clock-frequency = <1701000000>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x100>;
enable-method = "psci";
clock-frequency = <1701000000>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x200>;
enable-method = "psci";
clock-frequency = <1701000000>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x300>;
enable-method = "psci";
clock-frequency = <1701000000>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
cpu4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x400>;
enable-method = "psci";
clock-frequency = <2171000000>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
cpu5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x500>;
enable-method = "psci";
clock-frequency = <2171000000>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
cpu6: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x600>;
enable-method = "psci";
clock-frequency = <2171000000>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
cpu7: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x700>;
enable-method = "psci";
clock-frequency = <2171000000>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
};
l2_0: l2-cache0 {
compatible = "cache";
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
};
};
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
};
pmu-a76 {
compatible = "arm,cortex-a76-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer: timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
clock-frequency = <13000000>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
#redistributor-regions = <1>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x40000>,
<0 0x0c040000 0 0x200000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
ppi-partitions {
ppi_cluster0: interrupt-partition-0 {
affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
};
ppi_cluster1: interrupt-partition-1 {
affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
};
};
};
pio: pinctrl@10005000 {
compatible = "mediatek,mt8192-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x11c20000 0 0x1000>,
<0 0x11d10000 0 0x1000>,
<0 0x11d30000 0 0x1000>,
<0 0x11d40000 0 0x1000>,
<0 0x11e20000 0 0x1000>,
<0 0x11e70000 0 0x1000>,
<0 0x11ea0000 0 0x1000>,
<0 0x11f20000 0 0x1000>,
<0 0x11f30000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
"iocfg_bl", "iocfg_br", "iocfg_lm",
"iocfg_lb", "iocfg_rt", "iocfg_lt",
"iocfg_tl", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 220>;
interrupt-controller;
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
#interrupt-cells = <2>;
};
systimer: timer@10017000 {
compatible = "mediatek,mt8192-timer",
"mediatek,mt6765-timer";
reg = <0 0x10017000 0 0x1000>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>;
clock-names = "clk13m";
};
uart0: serial@11002000 {
compatible = "mediatek,mt8192-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clock-names = "baud", "bus";
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt8192-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clock-names = "baud", "bus";
status = "disabled";
};
spi0: spi@1100a000 {
compatible = "mediatek,mt8192-spi",
"mediatek,mt6765-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x1100a000 0 0x1000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>,
<&clk26m>,
<&clk26m>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi1: spi@11010000 {
compatible = "mediatek,mt8192-spi",
"mediatek,mt6765-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11010000 0 0x1000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>,
<&clk26m>,
<&clk26m>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi2: spi@11012000 {
compatible = "mediatek,mt8192-spi",
"mediatek,mt6765-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11012000 0 0x1000>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>,
<&clk26m>,
<&clk26m>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi3: spi@11013000 {
compatible = "mediatek,mt8192-spi",
"mediatek,mt6765-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11013000 0 0x1000>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>,
<&clk26m>,
<&clk26m>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi4: spi@11018000 {
compatible = "mediatek,mt8192-spi",
"mediatek,mt6765-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11018000 0 0x1000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>,
<&clk26m>,
<&clk26m>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi5: spi@11019000 {
compatible = "mediatek,mt8192-spi",
"mediatek,mt6765-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11019000 0 0x1000>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>,
<&clk26m>,
<&clk26m>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi6: spi@1101d000 {
compatible = "mediatek,mt8192-spi",
"mediatek,mt6765-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x1101d000 0 0x1000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>,
<&clk26m>,
<&clk26m>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi7: spi@1101e000 {
compatible = "mediatek,mt8192-spi",
"mediatek,mt6765-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x1101e000 0 0x1000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>,
<&clk26m>,
<&clk26m>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
i2c3: i2c3@11cb0000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11cb0000 0 0x1000>,
<0 0x10217300 0 0x80>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c7: i2c7@11d00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11d00000 0 0x1000>,
<0 0x10217600 0 0x180>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c8: i2c8@11d01000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11d01000 0 0x1000>,
<0 0x10217780 0 0x180>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c9: i2c9@11d02000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11d02000 0 0x1000>,
<0 0x10217900 0 0x180>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c1@11d20000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11d20000 0 0x1000>,
<0 0x10217100 0 0x80>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c2@11d21000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11d21000 0 0x1000>,
<0 0x10217180 0 0x180>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c4@11d22000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11d22000 0 0x1000>,
<0 0x10217380 0 0x180>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c5@11e00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11e00000 0 0x1000>,
<0 0x10217500 0 0x80>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c0: i2c0@11f00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11f00000 0 0x1000>,
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c6: i2c6@11f01000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11f01000 0 0x1000>,
<0 0x10217580 0 0x80>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
};

40
arch/arm64/boot/dts/mediatek/mt8516.dtsi
View file

@ -237,6 +237,13 @@ pio: pinctrl@1000b000 {
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
};
efuse: efuse@10009000 {
compatible = "mediatek,mt8516-efuse", "mediatek,efuse";
reg = <0 0x10009000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
};
pwrap: pwrap@1000f000 {
compatible = "mediatek,mt8516-pwrap";
reg = <0 0x1000f000 0 0x1000>;
@ -455,7 +462,21 @@ usb0: usb@11100000 {
status = "disabled";
};
usb0_phy: usb@11110000 {
usb1: usb@11190000 {
compatible = "mediatek,mtk-musb";
reg = <0 0x11190000 0 0x1000>;
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "mc";
phys = <&usb1_port PHY_TYPE_USB2>;
clocks = <&topckgen CLK_TOP_USB>,
<&topckgen CLK_TOP_USBIF>,
<&topckgen CLK_TOP_USB_1P>;
clock-names = "main","mcu","univpll";
dr_mode = "host";
status = "disabled";
};
usb_phy: usb@11110000 {
compatible = "mediatek,generic-tphy-v1";
reg = <0 0x11110000 0 0x800>;
#address-cells = <2>;
@ -469,6 +490,23 @@ usb0_port: usb-phy@11110800 {
clock-names = "ref";
#phy-cells = <1>;
};
usb1_port: usb-phy@11110900 {
reg = <0 0x11110900 0 0x100>;
clocks = <&topckgen CLK_TOP_USB_PHY48M>;
clock-names = "ref";
#phy-cells = <1>;
};
};
auxadc: adc@11003000 {
compatible = "mediatek,mt8516-auxadc",
"mediatek,mt8173-auxadc";
reg = <0 0x11003000 0 0x1000>;
clocks = <&topckgen CLK_TOP_AUX_ADC>;
clock-names = "main";
#io-channel-cells = <1>;
status = "disabled";
};
};
};

28
arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
View file

@ -63,91 +63,91 @@ tca6416: gpio@20 {
gpio-controller;
#gpio-cells = <2>;
eint20_mux_sel0 {
eint20-mux-sel0-hog {
gpio-hog;
gpios = <0 0>;
input;
line-name = "eint20_mux_sel0";
};
expcon_mux_sel1 {
expcon-mux-sel1-hog {
gpio-hog;
gpios = <1 0>;
input;
line-name = "expcon_mux_sel1";
};
mrg_di_mux_sel2 {
mrg-di-mux-sel2-hog {
gpio-hog;
gpios = <2 0>;
input;
line-name = "mrg_di_mux_sel2";
};
sd_sdio_mux_sel3 {
sd-sdio-mux-sel3-hog {
gpio-hog;
gpios = <3 0>;
input;
line-name = "sd_sdio_mux_sel3";
};
sd_sdio_mux_ctrl7 {
sd-sdio-mux-ctrl7-hog {
gpio-hog;
gpios = <7 0>;
output-low;
line-name = "sd_sdio_mux_ctrl7";
};
hw_id0 {
hw-id0-hog {
gpio-hog;
gpios = <8 0>;
input;
line-name = "hw_id0";
};
hw_id1 {
hw-id1-hog {
gpio-hog;
gpios = <9 0>;
input;
line-name = "hw_id1";
};
hw_id2 {
hw-id2-hog {
gpio-hog;
gpios = <10 0>;
input;
line-name = "hw_id2";
};
fg_int_n {
fg-int-n-hog {
gpio-hog;
gpios = <11 0>;
input;
line-name = "fg_int_n";
};
usba_pwr_en {
usba-pwr-en-hog {
gpio-hog;
gpios = <12 0>;
output-high;
line-name = "usba_pwr_en";
};
wifi_3v3_pg {
wifi-3v3-pg-hog {
gpio-hog;
gpios = <13 0>;
input;
line-name = "wifi_3v3_pg";
};
cam_rst {
cam-rst-hog {
gpio-hog;
gpios = <14 0>;
output-low;
line-name = "cam_rst";
};
cam_pwdn {
cam-pwdn-hog {
gpio-hog;
gpios = <15 0>;
output-low;
@ -195,7 +195,7 @@ usb_con: connector {
};
};
&usb0_phy {
&usb_phy {
status = "okay";
};

26
include/dt-bindings/power/mt8183-power.h Normal file
View file

@ -0,0 +1,26 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2020 MediaTek Inc.
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
*/
#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
#define _DT_BINDINGS_POWER_MT8183_POWER_H
#define MT8183_POWER_DOMAIN_AUDIO 0
#define MT8183_POWER_DOMAIN_CONN 1
#define MT8183_POWER_DOMAIN_MFG_ASYNC 2
#define MT8183_POWER_DOMAIN_MFG 3
#define MT8183_POWER_DOMAIN_MFG_CORE0 4
#define MT8183_POWER_DOMAIN_MFG_CORE1 5
#define MT8183_POWER_DOMAIN_MFG_2D 6
#define MT8183_POWER_DOMAIN_DISP 7
#define MT8183_POWER_DOMAIN_CAM 8
#define MT8183_POWER_DOMAIN_ISP 9
#define MT8183_POWER_DOMAIN_VDEC 10
#define MT8183_POWER_DOMAIN_VENC 11
#define MT8183_POWER_DOMAIN_VPU_TOP 12
#define MT8183_POWER_DOMAIN_VPU_CORE0 13
#define MT8183_POWER_DOMAIN_VPU_CORE1 14
#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */

32
include/dt-bindings/power/mt8192-power.h Normal file
View file

@ -0,0 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (c) 2020 MediaTek Inc.
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
*/
#ifndef _DT_BINDINGS_POWER_MT8192_POWER_H
#define _DT_BINDINGS_POWER_MT8192_POWER_H
#define MT8192_POWER_DOMAIN_AUDIO 0
#define MT8192_POWER_DOMAIN_CONN 1
#define MT8192_POWER_DOMAIN_MFG0 2
#define MT8192_POWER_DOMAIN_MFG1 3
#define MT8192_POWER_DOMAIN_MFG2 4
#define MT8192_POWER_DOMAIN_MFG3 5
#define MT8192_POWER_DOMAIN_MFG4 6
#define MT8192_POWER_DOMAIN_MFG5 7
#define MT8192_POWER_DOMAIN_MFG6 8
#define MT8192_POWER_DOMAIN_DISP 9
#define MT8192_POWER_DOMAIN_IPE 10
#define MT8192_POWER_DOMAIN_ISP 11
#define MT8192_POWER_DOMAIN_ISP2 12
#define MT8192_POWER_DOMAIN_MDP 13
#define MT8192_POWER_DOMAIN_VENC 14
#define MT8192_POWER_DOMAIN_VDEC 15
#define MT8192_POWER_DOMAIN_VDEC2 16
#define MT8192_POWER_DOMAIN_CAM 17
#define MT8192_POWER_DOMAIN_CAM_RAWA 18
#define MT8192_POWER_DOMAIN_CAM_RAWB 19
#define MT8192_POWER_DOMAIN_CAM_RAWC 20
#endif /* _DT_BINDINGS_POWER_MT8192_POWER_H */