mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 03:10:12 +00:00
drm/nouveau: move PFIFO ISR into nv04_fifo.c
Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
25b85783da
commit
5178d40dff
7 changed files with 219 additions and 208 deletions
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@ -1053,6 +1053,7 @@ extern void nvc0_fb_takedown(struct drm_device *);
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/* nv04_fifo.c */
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extern int nv04_fifo_init(struct drm_device *);
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extern void nv04_fifo_fini(struct drm_device *);
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extern void nv04_fifo_disable(struct drm_device *);
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extern void nv04_fifo_enable(struct drm_device *);
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extern bool nv04_fifo_reassign(struct drm_device *, bool);
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@ -1062,6 +1063,7 @@ extern int nv04_fifo_create_context(struct nouveau_channel *);
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extern void nv04_fifo_destroy_context(struct nouveau_channel *);
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extern int nv04_fifo_load_context(struct nouveau_channel *);
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extern int nv04_fifo_unload_context(struct drm_device *);
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extern void nv04_fifo_isr(struct drm_device *);
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/* nv10_fifo.c */
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extern int nv10_fifo_init(struct drm_device *);
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@ -69,204 +69,6 @@ nouveau_irq_uninstall(struct drm_device *dev)
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nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
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}
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static bool
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nouveau_fifo_swmthd(struct drm_device *dev, u32 chid, u32 addr, u32 data)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_channel *chan = NULL;
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struct nouveau_gpuobj *obj;
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unsigned long flags;
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const int subc = (addr >> 13) & 0x7;
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const int mthd = addr & 0x1ffc;
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bool handled = false;
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u32 engine;
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spin_lock_irqsave(&dev_priv->channels.lock, flags);
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if (likely(chid >= 0 && chid < dev_priv->engine.fifo.channels))
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chan = dev_priv->channels.ptr[chid];
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if (unlikely(!chan))
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goto out;
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switch (mthd) {
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case 0x0000: /* bind object to subchannel */
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obj = nouveau_ramht_find(chan, data);
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if (unlikely(!obj || obj->engine != NVOBJ_ENGINE_SW))
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break;
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chan->sw_subchannel[subc] = obj->class;
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engine = 0x0000000f << (subc * 4);
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nv_mask(dev, NV04_PFIFO_CACHE1_ENGINE, engine, 0x00000000);
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handled = true;
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break;
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default:
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engine = nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE);
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if (unlikely(((engine >> (subc * 4)) & 0xf) != 0))
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break;
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if (!nouveau_gpuobj_mthd_call(chan, chan->sw_subchannel[subc],
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mthd, data))
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handled = true;
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break;
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}
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out:
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spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
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return handled;
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}
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static void
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nouveau_fifo_irq_handler(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_engine *engine = &dev_priv->engine;
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uint32_t status, reassign;
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int cnt = 0;
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reassign = nv_rd32(dev, NV03_PFIFO_CACHES) & 1;
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while ((status = nv_rd32(dev, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) {
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uint32_t chid, get;
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nv_wr32(dev, NV03_PFIFO_CACHES, 0);
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chid = engine->fifo.channel_id(dev);
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get = nv_rd32(dev, NV03_PFIFO_CACHE1_GET);
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if (status & NV_PFIFO_INTR_CACHE_ERROR) {
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uint32_t mthd, data;
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int ptr;
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/* NV_PFIFO_CACHE1_GET actually goes to 0xffc before
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* wrapping on my G80 chips, but CACHE1 isn't big
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* enough for this much data.. Tests show that it
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* wraps around to the start at GET=0x800.. No clue
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* as to why..
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*/
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ptr = (get & 0x7ff) >> 2;
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if (dev_priv->card_type < NV_40) {
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mthd = nv_rd32(dev,
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NV04_PFIFO_CACHE1_METHOD(ptr));
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data = nv_rd32(dev,
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NV04_PFIFO_CACHE1_DATA(ptr));
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} else {
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mthd = nv_rd32(dev,
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NV40_PFIFO_CACHE1_METHOD(ptr));
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data = nv_rd32(dev,
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NV40_PFIFO_CACHE1_DATA(ptr));
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}
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if (!nouveau_fifo_swmthd(dev, chid, mthd, data)) {
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NV_INFO(dev, "PFIFO_CACHE_ERROR - Ch %d/%d "
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"Mthd 0x%04x Data 0x%08x\n",
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chid, (mthd >> 13) & 7, mthd & 0x1ffc,
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data);
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}
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 0);
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nv_wr32(dev, NV03_PFIFO_INTR_0,
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NV_PFIFO_INTR_CACHE_ERROR);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
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nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) & ~1);
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nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
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nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) | 1);
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nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH,
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nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
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nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
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status &= ~NV_PFIFO_INTR_CACHE_ERROR;
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}
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if (status & NV_PFIFO_INTR_DMA_PUSHER) {
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u32 dma_get = nv_rd32(dev, 0x003244);
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u32 dma_put = nv_rd32(dev, 0x003240);
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u32 push = nv_rd32(dev, 0x003220);
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u32 state = nv_rd32(dev, 0x003228);
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if (dev_priv->card_type == NV_50) {
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u32 ho_get = nv_rd32(dev, 0x003328);
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u32 ho_put = nv_rd32(dev, 0x003320);
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u32 ib_get = nv_rd32(dev, 0x003334);
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u32 ib_put = nv_rd32(dev, 0x003330);
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if (nouveau_ratelimit())
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NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%02x%08x "
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"Put 0x%02x%08x IbGet 0x%08x IbPut 0x%08x "
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"State 0x%08x Push 0x%08x\n",
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chid, ho_get, dma_get, ho_put,
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dma_put, ib_get, ib_put, state,
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push);
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/* METHOD_COUNT, in DMA_STATE on earlier chipsets */
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nv_wr32(dev, 0x003364, 0x00000000);
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if (dma_get != dma_put || ho_get != ho_put) {
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nv_wr32(dev, 0x003244, dma_put);
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nv_wr32(dev, 0x003328, ho_put);
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} else
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if (ib_get != ib_put) {
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nv_wr32(dev, 0x003334, ib_put);
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}
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} else {
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NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%08x "
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"Put 0x%08x State 0x%08x Push 0x%08x\n",
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chid, dma_get, dma_put, state, push);
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if (dma_get != dma_put)
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nv_wr32(dev, 0x003244, dma_put);
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}
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nv_wr32(dev, 0x003228, 0x00000000);
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nv_wr32(dev, 0x003220, 0x00000001);
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nv_wr32(dev, 0x002100, NV_PFIFO_INTR_DMA_PUSHER);
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status &= ~NV_PFIFO_INTR_DMA_PUSHER;
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}
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if (status & NV_PFIFO_INTR_SEMAPHORE) {
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uint32_t sem;
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status &= ~NV_PFIFO_INTR_SEMAPHORE;
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nv_wr32(dev, NV03_PFIFO_INTR_0,
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NV_PFIFO_INTR_SEMAPHORE);
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sem = nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE);
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nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);
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nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
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nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
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}
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if (dev_priv->card_type == NV_50) {
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if (status & 0x00000010) {
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nv50_fb_vm_trap(dev, 1, "PFIFO_BAR_FAULT");
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status &= ~0x00000010;
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nv_wr32(dev, 0x002100, 0x00000010);
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}
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}
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if (status) {
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if (nouveau_ratelimit())
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NV_INFO(dev, "PFIFO_INTR 0x%08x - Ch %d\n",
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status, chid);
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nv_wr32(dev, NV03_PFIFO_INTR_0, status);
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status = 0;
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}
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nv_wr32(dev, NV03_PFIFO_CACHES, reassign);
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}
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if (status) {
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NV_INFO(dev, "PFIFO still angry after %d spins, halt\n", cnt);
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nv_wr32(dev, 0x2140, 0);
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nv_wr32(dev, 0x140, 0);
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}
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nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
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}
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static struct nouveau_bitfield nstatus_names[] =
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{
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{ NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
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@ -1146,11 +948,6 @@ nouveau_irq_handler(DRM_IRQ_ARGS)
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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if (status & NV_PMC_INTR_0_PFIFO_PENDING) {
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nouveau_fifo_irq_handler(dev);
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status &= ~NV_PMC_INTR_0_PFIFO_PENDING;
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}
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if (status & NV_PMC_INTR_0_PGRAPH_PENDING) {
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if (dev_priv->card_type >= NV_50)
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nv50_pgraph_irq_handler(dev);
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@ -75,7 +75,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->graph.unload_context = nv04_graph_unload_context;
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engine->fifo.channels = 16;
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engine->fifo.init = nv04_fifo_init;
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engine->fifo.takedown = nouveau_stub_takedown;
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engine->fifo.takedown = nv04_fifo_fini;
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engine->fifo.disable = nv04_fifo_disable;
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engine->fifo.enable = nv04_fifo_enable;
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engine->fifo.reassign = nv04_fifo_reassign;
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engine->graph.set_tile_region = nv10_graph_set_tile_region;
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engine->fifo.channels = 32;
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engine->fifo.init = nv10_fifo_init;
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engine->fifo.takedown = nouveau_stub_takedown;
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engine->fifo.takedown = nv04_fifo_fini;
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engine->fifo.disable = nv04_fifo_disable;
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engine->fifo.enable = nv04_fifo_enable;
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engine->fifo.reassign = nv04_fifo_reassign;
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@ -189,7 +189,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->graph.set_tile_region = nv20_graph_set_tile_region;
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engine->fifo.channels = 32;
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engine->fifo.init = nv10_fifo_init;
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engine->fifo.takedown = nouveau_stub_takedown;
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engine->fifo.takedown = nv04_fifo_fini;
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engine->fifo.disable = nv04_fifo_disable;
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engine->fifo.enable = nv04_fifo_enable;
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engine->fifo.reassign = nv04_fifo_reassign;
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@ -246,7 +246,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->graph.set_tile_region = nv20_graph_set_tile_region;
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engine->fifo.channels = 32;
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engine->fifo.init = nv10_fifo_init;
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engine->fifo.takedown = nouveau_stub_takedown;
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engine->fifo.takedown = nv04_fifo_fini;
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engine->fifo.disable = nv04_fifo_disable;
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engine->fifo.enable = nv04_fifo_enable;
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engine->fifo.reassign = nv04_fifo_reassign;
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@ -306,7 +306,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->graph.set_tile_region = nv40_graph_set_tile_region;
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engine->fifo.channels = 32;
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engine->fifo.init = nv40_fifo_init;
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engine->fifo.takedown = nouveau_stub_takedown;
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engine->fifo.takedown = nv04_fifo_fini;
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engine->fifo.disable = nv04_fifo_disable;
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engine->fifo.enable = nv04_fifo_enable;
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engine->fifo.reassign = nv04_fifo_reassign;
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@ -28,6 +28,7 @@
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_ramht.h"
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#include "nouveau_util.h"
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#define NV04_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV04_RAMFC__SIZE))
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#define NV04_RAMFC__SIZE 32
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@ -284,6 +285,7 @@ nv04_fifo_init_ramxx(struct drm_device *dev)
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static void
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nv04_fifo_init_intr(struct drm_device *dev)
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{
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nouveau_irq_register(dev, 8, nv04_fifo_isr);
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nv_wr32(dev, 0x002100, 0xffffffff);
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nv_wr32(dev, 0x002140, 0xffffffff);
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}
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@ -315,3 +317,207 @@ nv04_fifo_init(struct drm_device *dev)
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return 0;
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}
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void
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nv04_fifo_fini(struct drm_device *dev)
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{
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nv_wr32(dev, 0x2140, 0x00000000);
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nouveau_irq_unregister(dev, 8);
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}
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static bool
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nouveau_fifo_swmthd(struct drm_device *dev, u32 chid, u32 addr, u32 data)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_channel *chan = NULL;
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struct nouveau_gpuobj *obj;
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unsigned long flags;
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const int subc = (addr >> 13) & 0x7;
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const int mthd = addr & 0x1ffc;
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bool handled = false;
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u32 engine;
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spin_lock_irqsave(&dev_priv->channels.lock, flags);
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if (likely(chid >= 0 && chid < dev_priv->engine.fifo.channels))
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chan = dev_priv->channels.ptr[chid];
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if (unlikely(!chan))
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goto out;
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switch (mthd) {
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case 0x0000: /* bind object to subchannel */
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obj = nouveau_ramht_find(chan, data);
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if (unlikely(!obj || obj->engine != NVOBJ_ENGINE_SW))
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break;
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chan->sw_subchannel[subc] = obj->class;
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engine = 0x0000000f << (subc * 4);
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nv_mask(dev, NV04_PFIFO_CACHE1_ENGINE, engine, 0x00000000);
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handled = true;
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break;
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default:
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engine = nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE);
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if (unlikely(((engine >> (subc * 4)) & 0xf) != 0))
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break;
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if (!nouveau_gpuobj_mthd_call(chan, chan->sw_subchannel[subc],
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mthd, data))
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handled = true;
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break;
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}
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out:
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spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
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return handled;
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}
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void
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nv04_fifo_isr(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_engine *engine = &dev_priv->engine;
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uint32_t status, reassign;
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int cnt = 0;
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reassign = nv_rd32(dev, NV03_PFIFO_CACHES) & 1;
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while ((status = nv_rd32(dev, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) {
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uint32_t chid, get;
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nv_wr32(dev, NV03_PFIFO_CACHES, 0);
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chid = engine->fifo.channel_id(dev);
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get = nv_rd32(dev, NV03_PFIFO_CACHE1_GET);
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if (status & NV_PFIFO_INTR_CACHE_ERROR) {
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uint32_t mthd, data;
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int ptr;
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/* NV_PFIFO_CACHE1_GET actually goes to 0xffc before
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* wrapping on my G80 chips, but CACHE1 isn't big
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* enough for this much data.. Tests show that it
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* wraps around to the start at GET=0x800.. No clue
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* as to why..
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*/
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ptr = (get & 0x7ff) >> 2;
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if (dev_priv->card_type < NV_40) {
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mthd = nv_rd32(dev,
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NV04_PFIFO_CACHE1_METHOD(ptr));
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data = nv_rd32(dev,
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NV04_PFIFO_CACHE1_DATA(ptr));
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} else {
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mthd = nv_rd32(dev,
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NV40_PFIFO_CACHE1_METHOD(ptr));
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data = nv_rd32(dev,
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NV40_PFIFO_CACHE1_DATA(ptr));
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}
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if (!nouveau_fifo_swmthd(dev, chid, mthd, data)) {
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NV_INFO(dev, "PFIFO_CACHE_ERROR - Ch %d/%d "
|
||||
"Mthd 0x%04x Data 0x%08x\n",
|
||||
chid, (mthd >> 13) & 7, mthd & 0x1ffc,
|
||||
data);
|
||||
}
|
||||
|
||||
nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 0);
|
||||
nv_wr32(dev, NV03_PFIFO_INTR_0,
|
||||
NV_PFIFO_INTR_CACHE_ERROR);
|
||||
|
||||
nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
|
||||
nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) & ~1);
|
||||
nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
|
||||
nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
|
||||
nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) | 1);
|
||||
nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
|
||||
|
||||
nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH,
|
||||
nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
|
||||
nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
|
||||
|
||||
status &= ~NV_PFIFO_INTR_CACHE_ERROR;
|
||||
}
|
||||
|
||||
if (status & NV_PFIFO_INTR_DMA_PUSHER) {
|
||||
u32 dma_get = nv_rd32(dev, 0x003244);
|
||||
u32 dma_put = nv_rd32(dev, 0x003240);
|
||||
u32 push = nv_rd32(dev, 0x003220);
|
||||
u32 state = nv_rd32(dev, 0x003228);
|
||||
|
||||
if (dev_priv->card_type == NV_50) {
|
||||
u32 ho_get = nv_rd32(dev, 0x003328);
|
||||
u32 ho_put = nv_rd32(dev, 0x003320);
|
||||
u32 ib_get = nv_rd32(dev, 0x003334);
|
||||
u32 ib_put = nv_rd32(dev, 0x003330);
|
||||
|
||||
if (nouveau_ratelimit())
|
||||
NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%02x%08x "
|
||||
"Put 0x%02x%08x IbGet 0x%08x IbPut 0x%08x "
|
||||
"State 0x%08x Push 0x%08x\n",
|
||||
chid, ho_get, dma_get, ho_put,
|
||||
dma_put, ib_get, ib_put, state,
|
||||
push);
|
||||
|
||||
/* METHOD_COUNT, in DMA_STATE on earlier chipsets */
|
||||
nv_wr32(dev, 0x003364, 0x00000000);
|
||||
if (dma_get != dma_put || ho_get != ho_put) {
|
||||
nv_wr32(dev, 0x003244, dma_put);
|
||||
nv_wr32(dev, 0x003328, ho_put);
|
||||
} else
|
||||
if (ib_get != ib_put) {
|
||||
nv_wr32(dev, 0x003334, ib_put);
|
||||
}
|
||||
} else {
|
||||
NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%08x "
|
||||
"Put 0x%08x State 0x%08x Push 0x%08x\n",
|
||||
chid, dma_get, dma_put, state, push);
|
||||
|
||||
if (dma_get != dma_put)
|
||||
nv_wr32(dev, 0x003244, dma_put);
|
||||
}
|
||||
|
||||
nv_wr32(dev, 0x003228, 0x00000000);
|
||||
nv_wr32(dev, 0x003220, 0x00000001);
|
||||
nv_wr32(dev, 0x002100, NV_PFIFO_INTR_DMA_PUSHER);
|
||||
status &= ~NV_PFIFO_INTR_DMA_PUSHER;
|
||||
}
|
||||
|
||||
if (status & NV_PFIFO_INTR_SEMAPHORE) {
|
||||
uint32_t sem;
|
||||
|
||||
status &= ~NV_PFIFO_INTR_SEMAPHORE;
|
||||
nv_wr32(dev, NV03_PFIFO_INTR_0,
|
||||
NV_PFIFO_INTR_SEMAPHORE);
|
||||
|
||||
sem = nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE);
|
||||
nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);
|
||||
|
||||
nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
|
||||
nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
|
||||
}
|
||||
|
||||
if (dev_priv->card_type == NV_50) {
|
||||
if (status & 0x00000010) {
|
||||
nv50_fb_vm_trap(dev, 1, "PFIFO_BAR_FAULT");
|
||||
status &= ~0x00000010;
|
||||
nv_wr32(dev, 0x002100, 0x00000010);
|
||||
}
|
||||
}
|
||||
|
||||
if (status) {
|
||||
if (nouveau_ratelimit())
|
||||
NV_INFO(dev, "PFIFO_INTR 0x%08x - Ch %d\n",
|
||||
status, chid);
|
||||
nv_wr32(dev, NV03_PFIFO_INTR_0, status);
|
||||
status = 0;
|
||||
}
|
||||
|
||||
nv_wr32(dev, NV03_PFIFO_CACHES, reassign);
|
||||
}
|
||||
|
||||
if (status) {
|
||||
NV_INFO(dev, "PFIFO still angry after %d spins, halt\n", cnt);
|
||||
nv_wr32(dev, 0x2140, 0);
|
||||
nv_wr32(dev, 0x140, 0);
|
||||
}
|
||||
|
||||
nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
|
||||
}
|
||||
|
|
|
@ -208,6 +208,7 @@ nv10_fifo_init_ramxx(struct drm_device *dev)
|
|||
static void
|
||||
nv10_fifo_init_intr(struct drm_device *dev)
|
||||
{
|
||||
nouveau_irq_register(dev, 8, nv04_fifo_isr);
|
||||
nv_wr32(dev, 0x002100, 0xffffffff);
|
||||
nv_wr32(dev, 0x002140, 0xffffffff);
|
||||
}
|
||||
|
|
|
@ -268,6 +268,7 @@ nv40_fifo_init_ramxx(struct drm_device *dev)
|
|||
static void
|
||||
nv40_fifo_init_intr(struct drm_device *dev)
|
||||
{
|
||||
nouveau_irq_register(dev, 8, nv04_fifo_isr);
|
||||
nv_wr32(dev, 0x002100, 0xffffffff);
|
||||
nv_wr32(dev, 0x002140, 0xffffffff);
|
||||
}
|
||||
|
|
|
@ -106,6 +106,7 @@ nv50_fifo_init_intr(struct drm_device *dev)
|
|||
{
|
||||
NV_DEBUG(dev, "\n");
|
||||
|
||||
nouveau_irq_register(dev, 8, nv04_fifo_isr);
|
||||
nv_wr32(dev, NV03_PFIFO_INTR_0, 0xFFFFFFFF);
|
||||
nv_wr32(dev, NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF);
|
||||
}
|
||||
|
@ -207,6 +208,9 @@ nv50_fifo_takedown(struct drm_device *dev)
|
|||
if (!pfifo->playlist[0])
|
||||
return;
|
||||
|
||||
nv_wr32(dev, 0x2140, 0x00000000);
|
||||
nouveau_irq_unregister(dev, 8);
|
||||
|
||||
nouveau_gpuobj_ref(NULL, &pfifo->playlist[0]);
|
||||
nouveau_gpuobj_ref(NULL, &pfifo->playlist[1]);
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue