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arm: dts: modify Nuvoton NPCM7xx device tree structure
Modify Nuvoton NPCM7xx device tree structure by adding nuvoton common nNPCM7xx device tree structure that include all common modules. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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518d2f43c3
3 changed files with 190 additions and 178 deletions
187
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
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187
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
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// Copyright 2018 Google, Inc.
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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/* external reference clock */
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clk_refclk: clk_refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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clock-output-names = "refclk";
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};
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/* external reference clock for cpu. float in normal operation */
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clk_sysbypck: clk_sysbypck {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <800000000>;
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clock-output-names = "sysbypck";
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};
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/* external reference clock for MC. float in normal operation */
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clk_mcbypck: clk_mcbypck {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <800000000>;
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clock-output-names = "mcbypck";
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};
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/* external clock signal rg1refck, supplied by the phy */
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clk_rg1refck: clk_rg1refck {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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clock-output-names = "clk_rg1refck";
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};
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/* external clock signal rg2refck, supplied by the phy */
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clk_rg2refck: clk_rg2refck {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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clock-output-names = "clk_rg2refck";
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};
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clk_xin: clk_xin {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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clock-output-names = "clk_xin";
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges = <0x0 0xf0000000 0x00900000>;
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gcr: gcr@800000 {
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compatible = "nuvoton,npcm750-gcr", "syscon",
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"simple-mfd";
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reg = <0x800000 0x1000>;
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};
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scu: scu@3fe000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x3fe000 0x1000>;
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};
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l2: cache-controller@3fc000 {
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compatible = "arm,pl310-cache";
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reg = <0x3fc000 0x1000>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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cache-unified;
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cache-level = <2>;
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clocks = <&clk 10>;
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arm,shared-override;
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};
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gic: interrupt-controller@3ff000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x3ff000 0x1000>,
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<0x3fe100 0x100>;
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};
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};
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ahb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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clk: clock-controller@f0801000 {
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compatible = "nuvoton,npcm750-clk", "syscon";
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#clock-cells = <1>;
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clock-controller;
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reg = <0xf0801000 0x1000>;
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clock-names = "refclk", "sysbypck", "mcbypck";
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clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
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};
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apb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges = <0x0 0xf0000000 0x00300000>;
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timer0: timer@8000 {
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compatible = "nuvoton,npcm750-timer";
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x8000 0x50>;
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clocks = <&clk 5>;
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};
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watchdog0: watchdog@801C {
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compatible = "nuvoton,npcm750-wdt";
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x801C 0x4>;
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status = "disabled";
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clocks = <&clk 5>;
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};
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watchdog1: watchdog@901C {
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compatible = "nuvoton,npcm750-wdt";
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x901C 0x4>;
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status = "disabled";
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clocks = <&clk 5>;
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};
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watchdog2: watchdog@a01C {
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compatible = "nuvoton,npcm750-wdt";
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xa01C 0x4>;
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status = "disabled";
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clocks = <&clk 5>;
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};
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serial0: serial@1000 {
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compatible = "nuvoton,npcm750-uart";
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reg = <0x1000 0x1000>;
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clocks = <&clk 6>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial1: serial@2000 {
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compatible = "nuvoton,npcm750-uart";
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reg = <0x2000 0x1000>;
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clocks = <&clk 6>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial2: serial@3000 {
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compatible = "nuvoton,npcm750-uart";
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reg = <0x3000 0x1000>;
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clocks = <&clk 6>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial3: serial@4000 {
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compatible = "nuvoton,npcm750-uart";
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reg = <0x4000 0x1000>;
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clocks = <&clk 6>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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};
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};
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};
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@ -1,5 +1,5 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018 Nuvoton Technology corporation.
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// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
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// Copyright 2018 Google, Inc.
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/dts-v1/;
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@ -1,8 +1,8 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018 Nuvoton Technology corporation.
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// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
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// Copyright 2018 Google, Inc.
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "nuvoton-common-npcm7xx.dtsi"
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/ {
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#address-cells = <1>;
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@ -32,90 +32,7 @@ cpu@1 {
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next-level-cache = <&l2>;
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};
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};
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/* external reference clock */
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clk-refclk: clk-refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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clock-output-names = "refclk";
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};
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/* external reference clock for cpu. float in normal operation */
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clk-sysbypck: clk-sysbypck {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <800000000>;
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clock-output-names = "sysbypck";
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};
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/* external reference clock for MC. float in normal operation */
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clk-mcbypck: clk-mcbypck {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <800000000>;
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clock-output-names = "mcbypck";
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};
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/* external clock signal rg1refck, supplied by the phy */
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clk-rg1refck: clk-rg1refck {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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clock-output-names = "clk-rg1refck";
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};
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/* external clock signal rg2refck, supplied by the phy */
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clk-rg2refck: clk-rg2refck {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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clock-output-names = "clk-rg2refck";
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};
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clk-xin: clk-xin {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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clock-output-names = "clk-xin";
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges = <0x0 0xf0000000 0x00900000>;
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gcr: gcr@800000 {
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compatible = "nuvoton,npcm750-gcr", "syscon",
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"simple-mfd";
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reg = <0x800000 0x1000>;
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};
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scu: scu@3fe000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x3fe000 0x1000>;
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};
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l2: cache-controller@3fc000 {
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compatible = "arm,pl310-cache";
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reg = <0x3fc000 0x1000>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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cache-unified;
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cache-level = <2>;
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clocks = <&clk 10>;
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arm,shared-override;
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};
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gic: interrupt-controller@3ff000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x3ff000 0x1000>,
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<0x3fe100 0x100>;
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};
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timer@3fe600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x3fe600 0x20>;
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@ -124,96 +41,4 @@ timer@3fe600 {
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clocks = <&clk 5>;
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};
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};
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ahb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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clk: clock-controller@f0801000 {
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compatible = "nuvoton,npcm750-clk", "syscon";
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#clock-cells = <1>;
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clock-controller;
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reg = <0xf0801000 0x1000>;
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clock-names = "refclk", "sysbypck", "mcbypck";
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clocks = <&clk-refclk>, <&clk-sysbypck>, <&clk-mcbypck>;
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};
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apb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges = <0x0 0xf0000000 0x00300000>;
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timer0: timer@8000 {
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compatible = "nuvoton,npcm750-timer";
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x8000 0x50>;
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clocks = <&clk 5>;
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};
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watchdog0: watchdog@801C {
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compatible = "nuvoton,npcm750-wdt";
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x801C 0x4>;
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status = "disabled";
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clocks = <&clk 5>;
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};
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watchdog1: watchdog@901C {
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compatible = "nuvoton,npcm750-wdt";
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x901C 0x4>;
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status = "disabled";
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clocks = <&clk 5>;
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};
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watchdog2: watchdog@a01C {
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compatible = "nuvoton,npcm750-wdt";
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xa01C 0x4>;
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status = "disabled";
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clocks = <&clk 5>;
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};
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serial0: serial@1000 {
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compatible = "nuvoton,npcm750-uart";
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reg = <0x1000 0x1000>;
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clocks = <&clk 6>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial1: serial@2000 {
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compatible = "nuvoton,npcm750-uart";
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reg = <0x2000 0x1000>;
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clocks = <&clk 6>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial2: serial@3000 {
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compatible = "nuvoton,npcm750-uart";
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reg = <0x3000 0x1000>;
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clocks = <&clk 6>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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serial3: serial@4000 {
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compatible = "nuvoton,npcm750-uart";
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reg = <0x4000 0x1000>;
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clocks = <&clk 6>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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status = "disabled";
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};
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};
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};
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};
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