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sata_mv: don't blindly enable IRQs
Part one of simplifying/fixing handling of the main_irq_mask register to resolve unexpected interrupt issues observed in 2.6.26-rc*. Don't blindly enable port IRQs at host init time. Instead, enable only the bits that we want, which in this case is simply the PCI_ERR bit. The per-port bits can wait until the ports are reset/probed for devices. Signed-off-by: Mark Lord <mlord@pobox.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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c443c5002b
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51de32d200
1 changed files with 5 additions and 25 deletions
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@ -202,13 +202,6 @@ enum {
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HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
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HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
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HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
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HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
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PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
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PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
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HC_MAIN_RSVD),
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HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
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HC_MAIN_RSVD_5),
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HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC),
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/* SATAHC registers */
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HC_CFG_OFS = 0,
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@ -3101,25 +3094,12 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
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/* and unmask interrupt generation for host regs */
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writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
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if (IS_GEN_I(hpriv))
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writelfl(~HC_MAIN_MASKED_IRQS_5,
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hpriv->main_irq_mask_addr);
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else
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writelfl(~HC_MAIN_MASKED_IRQS,
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hpriv->main_irq_mask_addr);
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VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
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"PCI int cause/mask=0x%08x/0x%08x\n",
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readl(hpriv->main_irq_cause_addr),
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readl(hpriv->main_irq_mask_addr),
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readl(mmio + hpriv->irq_cause_ofs),
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readl(mmio + hpriv->irq_mask_ofs));
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} else {
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writelfl(~HC_MAIN_MASKED_IRQS_SOC,
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hpriv->main_irq_mask_addr);
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VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n",
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readl(hpriv->main_irq_cause_addr),
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readl(hpriv->main_irq_mask_addr));
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/*
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* enable only global host interrupts for now.
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* The per-port interrupts get done later as ports are set up.
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*/
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writelfl(PCI_ERR, hpriv->main_irq_mask_addr);
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}
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done:
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return rc;
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