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Renesas ARM DT updates for v5.17 (take two)

Browse source 
- Initial support for the R-Car S4-8 SoC on the Spider CPU and
     BreakOut boards,
   - MIPI DSI display support for the R-Car V3u SoC and the Falcon board
     stack,
   - Thermal and GPU support for the RZ/G2L SoC and the RZ/G2L SMARC EVK
     development board,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-arm-dt-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.17 (take two)

  - Initial support for the R-Car S4-8 SoC on the Spider CPU and
    BreakOut boards,
  - MIPI DSI display support for the R-Car V3u SoC and the Falcon board
    stack,
  - Thermal and GPU support for the RZ/G2L SoC and the RZ/G2L SMARC EVK
    development board,
  - Miscellaneous fixes and improvements.

* tag 'renesas-arm-dt-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: Fix pin controller node names
  arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
  arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node
  arm64: dts: renesas: r9a07g044: Create thermal zone to support IPA
  arm64: dts: renesas: r9a07g044: Add TSU node
  arm64: dts: renesas: falcon-cpu: Add DSI display output
  arm64: dts: renesas: r8a779a0: Add DSI encoders
  arm64: dts: renesas: Add Renesas Spider boards support
  arm64: dts: renesas: Add Renesas R8A779F0 SoC support
  dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions
  dt-bindings: power: Add r8a779f0 SYSC power domain definitions
  arm64: dts: renesas: Fix thermal bindings

Link: https://lore.kernel.org/r/cover.1639736718.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2021-12-17 15:53:29 +01:00
commit 527c71547d
18 changed files with 562 additions and 30 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/arm64/boot/dts/renesas/Makefile
View file

@ -63,6 +63,8 @@ dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb
dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f0-spider.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb-kf.dtb

6
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View file

@ -2788,7 +2788,7 @@ prr: chipid@fff00044 {
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
sensor1_thermal: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
@ -2803,7 +2803,7 @@ sensor1_crit: sensor1-crit {
};
};
sensor_thermal2: sensor-thermal2 {
sensor2_thermal: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
@ -2818,7 +2818,7 @@ sensor2_crit: sensor2-crit {
};
};
sensor_thermal3: sensor-thermal3 {
sensor3_thermal: sensor3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;

6
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
View file

@ -2633,7 +2633,7 @@ prr: chipid@fff00044 {
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
sensor1_thermal: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
@ -2648,7 +2648,7 @@ sensor1_crit: sensor1-crit {
};
};
sensor_thermal2: sensor-thermal2 {
sensor2_thermal: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
@ -2663,7 +2663,7 @@ sensor2_crit: sensor2-crit {
};
};
sensor_thermal3: sensor-thermal3 {
sensor3_thermal: sensor3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;

6
arch/arm64/boot/dts/renesas/r8a774e1.dtsi
View file

@ -2908,7 +2908,7 @@ prr: chipid@fff00044 {
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
sensor1_thermal: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
@ -2923,7 +2923,7 @@ sensor1_crit: sensor1-crit {
};
};
sensor_thermal2: sensor-thermal2 {
sensor2_thermal: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
@ -2938,7 +2938,7 @@ sensor2_crit: sensor2-crit {
};
};
sensor_thermal3: sensor-thermal3 {
sensor3_thermal: sensor3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;

6
arch/arm64/boot/dts/renesas/r8a77951.dtsi
View file

@ -3379,7 +3379,7 @@ prr: chipid@fff00044 {
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
sensor1_thermal: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
@ -3394,7 +3394,7 @@ sensor1_crit: sensor1-crit {
};
};
sensor_thermal2: sensor-thermal2 {
sensor2_thermal: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
@ -3409,7 +3409,7 @@ sensor2_crit: sensor2-crit {
};
};
sensor_thermal3: sensor-thermal3 {
sensor3_thermal: sensor3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;

6
arch/arm64/boot/dts/renesas/r8a77960.dtsi
View file

@ -2976,7 +2976,7 @@ prr: chipid@fff00044 {
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
sensor1_thermal: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
@ -2991,7 +2991,7 @@ sensor1_crit: sensor1-crit {
};
};
sensor_thermal2: sensor-thermal2 {
sensor2_thermal: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
@ -3006,7 +3006,7 @@ sensor2_crit: sensor2-crit {
};
};
sensor_thermal3: sensor-thermal3 {
sensor3_thermal: sensor3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;

6
arch/arm64/boot/dts/renesas/r8a77961.dtsi
View file

@ -2734,7 +2734,7 @@ prr: chipid@fff00044 {
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
sensor1_thermal: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
@ -2749,7 +2749,7 @@ sensor1_crit: sensor1-crit {
};
};
sensor_thermal2: sensor-thermal2 {
sensor2_thermal: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
@ -2764,7 +2764,7 @@ sensor2_crit: sensor2-crit {
};
};
sensor_thermal3: sensor-thermal3 {
sensor3_thermal: sensor3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;

6
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View file

@ -2788,7 +2788,7 @@ prr: chipid@fff00044 {
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
sensor1_thermal: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
@ -2803,7 +2803,7 @@ sensor1_crit: sensor1-crit {
};
};
sensor_thermal2: sensor-thermal2 {
sensor2_thermal: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
@ -2818,7 +2818,7 @@ sensor2_crit: sensor2-crit {
};
};
sensor_thermal3: sensor-thermal3 {
sensor3_thermal: sensor3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;

4
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View file

@ -1581,7 +1581,7 @@ prr: chipid@fff00044 {
};
thermal-zones {
thermal-sensor-1 {
sensor1_thermal: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
@ -1600,7 +1600,7 @@ sensor1-critical {
};
};
thermal-sensor-2 {
sensor2_thermal: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;

79
arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
View file

@ -98,6 +98,27 @@ memory@700000000 {
reg = <0x7 0x00000000 0x0 0x80000000>;
};
mini-dp-con {
compatible = "dp-connector";
label = "CN5";
type = "mini";
port {
mini_dp_con_in: endpoint {
remote-endpoint = <&sn65dsi86_out>;
};
};
};
reg_1p2v: regulator-1p2v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
@ -115,6 +136,29 @@ reg_3p3v: regulator-3p3v {
regulator-boot-on;
regulator-always-on;
};
sn65dsi86_refclk: clk-x6 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <38400000>;
};
};
&dsi0 {
status = "okay";
ports {
port@1 {
dsi0_out: endpoint {
remote-endpoint = <&sn65dsi86_in>;
data-lanes = <1 2 3 4>;
};
};
};
};
&du {
status = "okay";
};
&extal_clk {
@ -146,6 +190,41 @@ &i2c1 {
status = "okay";
clock-frequency = <400000>;
bridge@2c {
compatible = "ti,sn65dsi86";
reg = <0x2c>;
clocks = <&sn65dsi86_refclk>;
clock-names = "refclk";
interrupt-parent = <&gpio1>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
vccio-supply = <&reg_1p8v>;
vpll-supply = <&reg_1p8v>;
vcca-supply = <&reg_1p2v>;
vcc-supply = <&reg_1p2v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sn65dsi86_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
port@1 {
reg = <1>;
sn65dsi86_out: endpoint {
remote-endpoint = <&mini_dp_con_in>;
};
};
};
};
};
&i2c6 {

70
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
View file

@ -87,7 +87,7 @@ rwdt: watchdog@e6020000 {
status = "disabled";
};
pfc: pin-controller@e6050000 {
pfc: pinctrl@e6050000 {
compatible = "renesas,pfc-r8a779a0";
reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
<0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
@ -2290,12 +2290,14 @@ ports {
port@0 {
reg = <0>;
du_out_dsi0: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
du_out_dsi1: endpoint {
remote-endpoint = <&dsi1_in>;
};
};
};
@ -2633,6 +2635,62 @@ isp3vin31: endpoint {
};
};
dsi0: dsi-encoder@fed80000 {
compatible = "renesas,r8a779a0-dsi-csi2-tx";
reg = <0 0xfed80000 0 0x10000>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
clocks = <&cpg CPG_MOD 415>,
<&cpg CPG_CORE R8A779A0_CLK_DSI>,
<&cpg CPG_CORE R8A779A0_CLK_CL16MCK>;
clock-names = "fck", "dsi", "pll";
resets = <&cpg 415>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&du_out_dsi0>;
};
};
port@1 {
reg = <1>;
};
};
};
dsi1: dsi-encoder@fed90000 {
compatible = "renesas,r8a779a0-dsi-csi2-tx";
reg = <0 0xfed90000 0 0x10000>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
clocks = <&cpg CPG_MOD 416>,
<&cpg CPG_CORE R8A779A0_CLK_DSI>,
<&cpg CPG_CORE R8A779A0_CLK_CL16MCK>;
clock-names = "fck", "dsi", "pll";
resets = <&cpg 416>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi1_in: endpoint {
remote-endpoint = <&du_out_dsi1>;
};
};
port@1 {
reg = <1>;
};
};
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
@ -2640,7 +2698,7 @@ prr: chipid@fff00044 {
};
thermal-zones {
sensor_thermal1: sensor-thermal1 {
sensor1_thermal: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
@ -2654,7 +2712,7 @@ sensor1_crit: sensor1-crit {
};
};
sensor_thermal2: sensor-thermal2 {
sensor2_thermal: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 1>;
@ -2668,7 +2726,7 @@ sensor2_crit: sensor2-crit {
};
};
sensor_thermal3: sensor-thermal3 {
sensor3_thermal: sensor3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 2>;
@ -2682,7 +2740,7 @@ sensor3_crit: sensor3-crit {
};
};
sensor_thermal4: sensor-thermal4 {
sensor4_thermal: sensor4-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 3>;
@ -2696,7 +2754,7 @@ sensor4_crit: sensor4-crit {
};
};
sensor_thermal5: sensor-thermal5 {
sensor5_thermal: sensor5-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsc 4>;

36
arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi Normal file
View file

@ -0,0 +1,36 @@
// SPDX-License-Identifier: (GPL-2.0 or MIT)
/*
* Device Tree Source for the Spider CPU board
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include "r8a779f0.dtsi"
/ {
model = "Renesas Spider CPU board";
compatible = "renesas,spider-cpu", "renesas,r8a779f0";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
};
&extal_clk {
clock-frequency = <20000000>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&scif3 {
status = "okay";
};

22
arch/arm64/boot/dts/renesas/r8a779f0-spider.dts Normal file
View file

@ -0,0 +1,22 @@
// SPDX-License-Identifier: (GPL-2.0 or MIT)
/*
* Device Tree Source for the Spider CPU and BreakOut boards
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a779f0-spider-cpu.dtsi"
/ {
model = "Renesas Spider CPU and Breakout boards based on r8a779f0";
compatible = "renesas,spider-breakout", "renesas,spider-cpu", "renesas,r8a779f0";
aliases {
serial0 = &scif3;
};
chosen {
stdout-path = "serial0:115200n8";
};
};

121
arch/arm64/boot/dts/renesas/r8a779f0.dtsi Normal file
View file

@ -0,0 +1,121 @@
// SPDX-License-Identifier: (GPL-2.0 or MIT)
/*
* Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a779f0-sysc.h>
/ {
compatible = "renesas,r8a779f0";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
a55_0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0>;
device_type = "cpu";
power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
};
};
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
extalr_clk: extalr {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
pmu_a55 {
compatible = "arm,cortex-a55-pmu";
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a779f0-cpg-mssr";
reg = <0 0xe6150000 0 0x4000>;
clocks = <&extal_clk>, <&extalr_clk>;
clock-names = "extal", "extalr";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a779f0-rst";
reg = <0 0xe6160000 0 0x4000>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a779f0-sysc";
reg = <0 0xe6180000 0 0x4000>;
#power-domain-cells = <1>;
};
scif3: serial@e6c50000 {
compatible = "renesas,scif-r8a779f0",
"renesas,rcar-gen4-scif", "renesas,scif";
reg = <0 0xe6c50000 0 64>;
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 704>,
<&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 704>;
status = "disabled";
};
gic: interrupt-controller@f1000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};

109
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
View file

@ -88,6 +88,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0>;
device_type = "cpu";
#cooling-cells = <2>;
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
@ -111,6 +112,50 @@ L3_CA55: cache-controller-0 {
};
};
gpu_opp_table: opp-table-1 {
compatible = "operating-points-v2";
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <1100000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1100000>;
};
opp-250000000 {
opp-hz = /bits/ 64 <250000000>;
opp-microvolt = <1100000>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <1100000>;
};
opp-125000000 {
opp-hz = /bits/ 64 <125000000>;
opp-microvolt = <1100000>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <1100000>;
};
opp-62500000 {
opp-hz = /bits/ 64 <62500000>;
opp-microvolt = <1100000>;
};
opp-50000000 {
opp-hz = /bits/ 64 <50000000>;
opp-microvolt = <1100000>;
};
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@ -539,6 +584,16 @@ channel@7 {
};
};
tsu: thermal@10059400 {
compatible = "renesas,r9a07g044-tsu",
"renesas,rzg2l-tsu";
reg = <0 0x10059400 0 0x400>;
clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
resets = <&cpg R9A07G044_TSU_PRESETN>;
power-domains = <&cpg>;
#thermal-sensor-cells = <1>;
};
sbc: spi@10060000 {
compatible = "renesas,r9a07g044-rpc-if",
"renesas,rzg2l-rpc-if";
@ -578,7 +633,7 @@ sysc: system-controller@11020000 {
status = "disabled";
};
pinctrl: pin-controller@11030000 {
pinctrl: pinctrl@11030000 {
compatible = "renesas,r9a07g044-pinctrl";
reg = <0 0x11030000 0 0x10000>;
gpio-controller;
@ -627,6 +682,27 @@ dmac: dma-controller@11820000 {
dma-channels = <16>;
};
gpu: gpu@11840000 {
compatible = "renesas,r9a07g044-mali",
"arm,mali-bifrost";
reg = <0x0 0x11840000 0x0 0x10000>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu", "event";
clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>,
<&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>,
<&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>;
clock-names = "gpu", "bus", "bus_ace";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_GPU_RESETN>,
<&cpg R9A07G044_GPU_AXI_RESETN>,
<&cpg R9A07G044_GPU_ACE_RESETN>;
reset-names = "rst", "axi_rst", "ace_rst";
operating-points-v2 = <&gpu_opp_table>;
};
gic: interrupt-controller@11900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
@ -902,6 +978,37 @@ ostm2: timer@12801800 {
};
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsu 0>;
sustainable-power = <717>;
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&cpu0 0 2>;
contribution = <1024>;
};
};
trips {
sensor_crit: sensor-crit {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";
};
target: trip-point {
temperature = <100000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,

13
arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
View file

@ -52,6 +52,15 @@ reg_3p3v: regulator1 {
regulator-always-on;
};
reg_1p1v: regulator-vdd-core {
compatible = "regulator-fixed";
regulator-name = "fixed-1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
@ -130,6 +139,10 @@ &extal_clk {
clock-frequency = <24000000>;
};
&gpu {
mali-supply = <&reg_1p1v>;
};
&ostm1 {
status = "okay";
};

64
include/dt-bindings/clock/r8a779f0-cpg-mssr.h Normal file
View file

@ -0,0 +1,64 @@
/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
/*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a779f0 CPG Core Clocks */
#define R8A779F0_CLK_ZX 0
#define R8A779F0_CLK_ZS 1
#define R8A779F0_CLK_ZT 2
#define R8A779F0_CLK_ZTR 3
#define R8A779F0_CLK_S0D2 4
#define R8A779F0_CLK_S0D3 5
#define R8A779F0_CLK_S0D4 6
#define R8A779F0_CLK_S0D2_MM 7
#define R8A779F0_CLK_S0D3_MM 8
#define R8A779F0_CLK_S0D4_MM 9
#define R8A779F0_CLK_S0D2_RT 10
#define R8A779F0_CLK_S0D3_RT 11
#define R8A779F0_CLK_S0D4_RT 12
#define R8A779F0_CLK_S0D6_RT 13
#define R8A779F0_CLK_S0D3_PER 14
#define R8A779F0_CLK_S0D6_PER 15
#define R8A779F0_CLK_S0D12_PER 16
#define R8A779F0_CLK_S0D24_PER 17
#define R8A779F0_CLK_S0D2_HSC 18
#define R8A779F0_CLK_S0D3_HSC 19
#define R8A779F0_CLK_S0D4_HSC 20
#define R8A779F0_CLK_S0D6_HSC 21
#define R8A779F0_CLK_S0D12_HSC 22
#define R8A779F0_CLK_S0D2_CC 23
#define R8A779F0_CLK_CL 24
#define R8A779F0_CLK_CL16M 25
#define R8A779F0_CLK_CL16M_MM 26
#define R8A779F0_CLK_CL16M_RT 27
#define R8A779F0_CLK_CL16M_PER 28
#define R8A779F0_CLK_CL16M_HSC 29
#define R8A779F0_CLK_Z0 30
#define R8A779F0_CLK_Z1 31
#define R8A779F0_CLK_ZB3 32
#define R8A779F0_CLK_ZB3D2 33
#define R8A779F0_CLK_ZB3D4 34
#define R8A779F0_CLK_SD0H 35
#define R8A779F0_CLK_SD0 36
#define R8A779F0_CLK_RPC 37
#define R8A779F0_CLK_RPCD2 38
#define R8A779F0_CLK_MSO 39
#define R8A779F0_CLK_SASYNCRT 40
#define R8A779F0_CLK_SASYNCPERD1 41
#define R8A779F0_CLK_SASYNCPERD2 42
#define R8A779F0_CLK_SASYNCPERD4 43
#define R8A779F0_CLK_DBGSOC_HSC 44
#define R8A779F0_CLK_RSW2 45
#define R8A779F0_CLK_OSC 46
#define R8A779F0_CLK_ZR 47
#define R8A779F0_CLK_CPEX 48
#define R8A779F0_CLK_CBFUSA 49
#define R8A779F0_CLK_R 50
#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */

30
include/dt-bindings/power/r8a779f0-sysc.h Normal file
View file

@ -0,0 +1,30 @@
/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
/*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A779F0_SYSC_H__
#define __DT_BINDINGS_POWER_R8A779F0_SYSC_H__
/*
* These power domain indices match the Power Domain Register Numbers (PDR)
*/
#define R8A779F0_PD_A1E0D0C0 0
#define R8A779F0_PD_A1E0D0C1 1
#define R8A779F0_PD_A1E0D1C0 2
#define R8A779F0_PD_A1E0D1C1 3
#define R8A779F0_PD_A1E1D0C0 4
#define R8A779F0_PD_A1E1D0C1 5
#define R8A779F0_PD_A1E1D1C0 6
#define R8A779F0_PD_A1E1D1C1 7
#define R8A779F0_PD_A2E0D0 16
#define R8A779F0_PD_A2E0D1 17
#define R8A779F0_PD_A2E1D0 18
#define R8A779F0_PD_A2E1D1 19
#define R8A779F0_PD_A3E0 20
#define R8A779F0_PD_A3E1 21
/* Always-on power area */
#define R8A779F0_PD_ALWAYS_ON 64
#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__*/