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drm/amd/pp: Delete dead code in powerplay
As not support per DPM level optimization, so delete activity_target array. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
ce91b71c9a
commit
527d9427fa
12 changed files with 15 additions and 45 deletions
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@ -173,16 +173,12 @@ static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
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static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
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static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
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{
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{
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struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
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struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
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uint32_t i;
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struct cgs_system_info sys_info = {0};
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struct cgs_system_info sys_info = {0};
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int result;
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int result;
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cz_hwmgr->gfx_ramp_step = 256*25/100;
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cz_hwmgr->gfx_ramp_step = 256*25/100;
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cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */
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cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */
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for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
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cz_hwmgr->activity_target[i] = CZ_AT_DFLT;
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cz_hwmgr->mgcg_cgtt_local0 = 0x00000000;
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cz_hwmgr->mgcg_cgtt_local0 = 0x00000000;
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cz_hwmgr->mgcg_cgtt_local1 = 0x00000000;
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cz_hwmgr->mgcg_cgtt_local1 = 0x00000000;
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cz_hwmgr->clock_slow_down_freq = 25000;
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cz_hwmgr->clock_slow_down_freq = 25000;
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@ -30,7 +30,6 @@
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#define CZ_NUM_NBPSTATES 4
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#define CZ_NUM_NBPSTATES 4
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#define CZ_NUM_NBPMEMORYCLOCK 2
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#define CZ_NUM_NBPMEMORYCLOCK 2
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#define MAX_DISPLAY_CLOCK_LEVEL 8
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#define MAX_DISPLAY_CLOCK_LEVEL 8
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#define CZ_AT_DFLT 30
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#define CZ_MAX_HARDWARE_POWERLEVELS 8
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#define CZ_MAX_HARDWARE_POWERLEVELS 8
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#define PPCZ_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102
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#define PPCZ_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102
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#define CZ_MIN_DEEP_SLEEP_SCLK 800
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#define CZ_MIN_DEEP_SLEEP_SCLK 800
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@ -185,7 +184,6 @@ struct cc6_settings {
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};
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};
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struct cz_hwmgr {
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struct cz_hwmgr {
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uint32_t activity_target[CZ_MAX_HARDWARE_POWERLEVELS];
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uint32_t dpm_interval;
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uint32_t dpm_interval;
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uint32_t voltage_drop_threshold;
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uint32_t voltage_drop_threshold;
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@ -289,7 +289,7 @@ struct smu7_hwmgr {
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struct smu7_pcie_perf_range pcie_lane_power_saving;
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struct smu7_pcie_perf_range pcie_lane_power_saving;
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bool use_pcie_performance_levels;
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bool use_pcie_performance_levels;
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bool use_pcie_power_saving_levels;
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bool use_pcie_power_saving_levels;
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uint32_t mclk_activity_target;
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uint16_t mclk_activity_target;
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uint16_t sclk_activity_target;
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uint16_t sclk_activity_target;
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uint32_t mclk_dpm0_activity_target;
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uint32_t mclk_dpm0_activity_target;
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uint32_t low_sclk_interrupt_threshold;
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uint32_t low_sclk_interrupt_threshold;
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@ -492,7 +492,7 @@ static int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
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for (i = 0; i < dpm_table->sclk_table.count; i++) {
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for (i = 0; i < dpm_table->sclk_table.count; i++) {
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result = ci_populate_single_graphic_level(hwmgr,
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result = ci_populate_single_graphic_level(hwmgr,
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dpm_table->sclk_table.dpm_levels[i].value,
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dpm_table->sclk_table.dpm_levels[i].value,
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(uint16_t)smu_data->activity_target[i],
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data->sclk_activity_target,
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&levels[i]);
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&levels[i]);
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if (result)
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if (result)
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return result;
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return result;
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@ -1231,7 +1231,7 @@ static int ci_populate_single_memory_level(
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memory_level->VoltageDownH = 0;
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memory_level->VoltageDownH = 0;
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/* Indicates maximum activity level for this performance level.*/
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/* Indicates maximum activity level for this performance level.*/
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memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
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memory_level->ActivityLevel = data->mclk_activity_target;
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memory_level->StutterEnable = 0;
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memory_level->StutterEnable = 0;
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memory_level->StrobeEnable = 0;
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memory_level->StrobeEnable = 0;
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memory_level->EdcReadEnable = 0;
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memory_level->EdcReadEnable = 0;
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@ -1515,7 +1515,7 @@ static int ci_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
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table->MemoryACPILevel.DownH = 100;
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table->MemoryACPILevel.DownH = 100;
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table->MemoryACPILevel.VoltageDownH = 0;
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table->MemoryACPILevel.VoltageDownH = 0;
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/* Indicates maximum activity level for this performance level.*/
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/* Indicates maximum activity level for this performance level.*/
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table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
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table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US(data->mclk_activity_target);
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table->MemoryACPILevel.StutterEnable = 0;
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table->MemoryACPILevel.StutterEnable = 0;
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table->MemoryACPILevel.StrobeEnable = 0;
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table->MemoryACPILevel.StrobeEnable = 0;
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@ -2802,7 +2802,6 @@ static int ci_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
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static int ci_smu_init(struct pp_hwmgr *hwmgr)
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static int ci_smu_init(struct pp_hwmgr *hwmgr)
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{
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{
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int i;
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struct ci_smumgr *ci_priv = NULL;
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struct ci_smumgr *ci_priv = NULL;
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ci_priv = kzalloc(sizeof(struct ci_smumgr), GFP_KERNEL);
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ci_priv = kzalloc(sizeof(struct ci_smumgr), GFP_KERNEL);
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@ -2810,9 +2809,6 @@ static int ci_smu_init(struct pp_hwmgr *hwmgr)
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if (ci_priv == NULL)
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if (ci_priv == NULL)
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return -ENOMEM;
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return -ENOMEM;
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for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
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ci_priv->activity_target[i] = 30;
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hwmgr->smu_backend = ci_priv;
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hwmgr->smu_backend = ci_priv;
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return 0;
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return 0;
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@ -70,8 +70,6 @@ struct ci_smumgr {
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const struct ci_pt_defaults *power_tune_defaults;
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const struct ci_pt_defaults *power_tune_defaults;
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SMU7_Discrete_MCRegisters mc_regs;
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SMU7_Discrete_MCRegisters mc_regs;
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struct ci_mc_reg_table mc_reg_table;
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struct ci_mc_reg_table mc_reg_table;
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uint32_t activity_target[SMU7_MAX_LEVELS_GRAPHICS];
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};
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};
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#endif
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#endif
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@ -368,7 +368,6 @@ static bool fiji_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
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static int fiji_smu_init(struct pp_hwmgr *hwmgr)
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static int fiji_smu_init(struct pp_hwmgr *hwmgr)
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{
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{
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int i;
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struct fiji_smumgr *fiji_priv = NULL;
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struct fiji_smumgr *fiji_priv = NULL;
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fiji_priv = kzalloc(sizeof(struct fiji_smumgr), GFP_KERNEL);
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fiji_priv = kzalloc(sizeof(struct fiji_smumgr), GFP_KERNEL);
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@ -381,9 +380,6 @@ static int fiji_smu_init(struct pp_hwmgr *hwmgr)
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if (smu7_init(hwmgr))
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if (smu7_init(hwmgr))
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return -EINVAL;
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return -EINVAL;
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for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
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fiji_priv->activity_target[i] = 30;
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return 0;
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return 0;
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}
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}
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@ -1063,7 +1059,7 @@ static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
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for (i = 0; i < dpm_table->sclk_table.count; i++) {
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for (i = 0; i < dpm_table->sclk_table.count; i++) {
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result = fiji_populate_single_graphic_level(hwmgr,
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result = fiji_populate_single_graphic_level(hwmgr,
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dpm_table->sclk_table.dpm_levels[i].value,
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dpm_table->sclk_table.dpm_levels[i].value,
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(uint16_t)smu_data->activity_target[i],
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data->sclk_activity_target,
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&levels[i]);
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&levels[i]);
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if (result)
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if (result)
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return result;
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return result;
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@ -1229,7 +1225,7 @@ static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
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mem_level->UpHyst = 0;
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mem_level->UpHyst = 0;
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mem_level->DownHyst = 100;
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mem_level->DownHyst = 100;
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mem_level->VoltageDownHyst = 0;
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mem_level->VoltageDownHyst = 0;
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mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
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mem_level->ActivityLevel = data->mclk_activity_target;
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mem_level->StutterEnable = false;
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mem_level->StutterEnable = false;
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mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
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mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
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@ -1447,7 +1443,7 @@ static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
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table->MemoryACPILevel.DownHyst = 100;
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table->MemoryACPILevel.DownHyst = 100;
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table->MemoryACPILevel.VoltageDownHyst = 0;
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table->MemoryACPILevel.VoltageDownHyst = 0;
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table->MemoryACPILevel.ActivityLevel =
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table->MemoryACPILevel.ActivityLevel =
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PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
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PP_HOST_TO_SMC_US(data->mclk_activity_target);
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table->MemoryACPILevel.StutterEnable = false;
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table->MemoryACPILevel.StutterEnable = false;
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CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
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CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
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@ -43,8 +43,6 @@ struct fiji_smumgr {
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struct SMU73_Discrete_Ulv ulv_setting;
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struct SMU73_Discrete_Ulv ulv_setting;
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struct SMU73_Discrete_PmFuses power_tune_table;
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struct SMU73_Discrete_PmFuses power_tune_table;
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const struct fiji_pt_defaults *power_tune_defaults;
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const struct fiji_pt_defaults *power_tune_defaults;
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uint32_t activity_target[SMU73_MAX_LEVELS_GRAPHICS];
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};
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};
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#endif
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#endif
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@ -262,7 +262,6 @@ static int iceland_start_smu(struct pp_hwmgr *hwmgr)
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static int iceland_smu_init(struct pp_hwmgr *hwmgr)
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static int iceland_smu_init(struct pp_hwmgr *hwmgr)
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{
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{
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int i;
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struct iceland_smumgr *iceland_priv = NULL;
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struct iceland_smumgr *iceland_priv = NULL;
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iceland_priv = kzalloc(sizeof(struct iceland_smumgr), GFP_KERNEL);
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iceland_priv = kzalloc(sizeof(struct iceland_smumgr), GFP_KERNEL);
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@ -275,9 +274,6 @@ static int iceland_smu_init(struct pp_hwmgr *hwmgr)
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if (smu7_init(hwmgr))
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if (smu7_init(hwmgr))
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return -EINVAL;
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return -EINVAL;
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for (i = 0; i < SMU71_MAX_LEVELS_GRAPHICS; i++)
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iceland_priv->activity_target[i] = 30;
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return 0;
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return 0;
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}
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}
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@ -989,7 +985,7 @@ static int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
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for (i = 0; i < dpm_table->sclk_table.count; i++) {
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for (i = 0; i < dpm_table->sclk_table.count; i++) {
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result = iceland_populate_single_graphic_level(hwmgr,
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result = iceland_populate_single_graphic_level(hwmgr,
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dpm_table->sclk_table.dpm_levels[i].value,
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dpm_table->sclk_table.dpm_levels[i].value,
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(uint16_t)smu_data->activity_target[i],
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data->sclk_activity_target,
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&(smu_data->smc_state_table.GraphicsLevel[i]));
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&(smu_data->smc_state_table.GraphicsLevel[i]));
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if (result != 0)
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if (result != 0)
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return result;
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return result;
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@ -1280,7 +1276,7 @@ static int iceland_populate_single_memory_level(
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memory_level->VoltageDownHyst = 0;
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memory_level->VoltageDownHyst = 0;
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/* Indicates maximum activity level for this performance level.*/
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/* Indicates maximum activity level for this performance level.*/
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memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
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memory_level->ActivityLevel = data->mclk_activity_target;
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memory_level->StutterEnable = 0;
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memory_level->StutterEnable = 0;
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memory_level->StrobeEnable = 0;
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memory_level->StrobeEnable = 0;
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memory_level->EdcReadEnable = 0;
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memory_level->EdcReadEnable = 0;
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@ -1561,7 +1557,7 @@ static int iceland_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
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table->MemoryACPILevel.DownHyst = 100;
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table->MemoryACPILevel.DownHyst = 100;
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table->MemoryACPILevel.VoltageDownHyst = 0;
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table->MemoryACPILevel.VoltageDownHyst = 0;
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/* Indicates maximum activity level for this performance level.*/
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/* Indicates maximum activity level for this performance level.*/
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table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
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table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US(data->mclk_activity_target);
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table->MemoryACPILevel.StutterEnable = 0;
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table->MemoryACPILevel.StutterEnable = 0;
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table->MemoryACPILevel.StrobeEnable = 0;
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table->MemoryACPILevel.StrobeEnable = 0;
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@ -65,7 +65,6 @@ struct iceland_smumgr {
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const struct iceland_pt_defaults *power_tune_defaults;
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const struct iceland_pt_defaults *power_tune_defaults;
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SMU71_Discrete_MCRegisters mc_regs;
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SMU71_Discrete_MCRegisters mc_regs;
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struct iceland_mc_reg_table mc_reg_table;
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struct iceland_mc_reg_table mc_reg_table;
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uint32_t activity_target[SMU71_MAX_LEVELS_GRAPHICS];
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};
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};
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#endif
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#endif
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@ -1133,7 +1133,7 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
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mem_level->UpHyst = 0;
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mem_level->UpHyst = 0;
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mem_level->DownHyst = 100;
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mem_level->DownHyst = 100;
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mem_level->VoltageDownHyst = 0;
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mem_level->VoltageDownHyst = 0;
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mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
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mem_level->ActivityLevel = data->mclk_activity_target;
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mem_level->StutterEnable = false;
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mem_level->StutterEnable = false;
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mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
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mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
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@ -1314,7 +1314,7 @@ static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
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table->MemoryACPILevel.DownHyst = 100;
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table->MemoryACPILevel.DownHyst = 100;
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table->MemoryACPILevel.VoltageDownHyst = 0;
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table->MemoryACPILevel.VoltageDownHyst = 0;
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table->MemoryACPILevel.ActivityLevel =
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table->MemoryACPILevel.ActivityLevel =
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PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
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PP_HOST_TO_SMC_US(data->mclk_activity_target);
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CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
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CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
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CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
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CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
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@ -222,7 +222,6 @@ static int tonga_start_smu(struct pp_hwmgr *hwmgr)
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static int tonga_smu_init(struct pp_hwmgr *hwmgr)
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static int tonga_smu_init(struct pp_hwmgr *hwmgr)
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{
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{
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struct tonga_smumgr *tonga_priv = NULL;
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struct tonga_smumgr *tonga_priv = NULL;
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int i;
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tonga_priv = kzalloc(sizeof(struct tonga_smumgr), GFP_KERNEL);
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tonga_priv = kzalloc(sizeof(struct tonga_smumgr), GFP_KERNEL);
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if (tonga_priv == NULL)
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if (tonga_priv == NULL)
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@ -233,9 +232,6 @@ static int tonga_smu_init(struct pp_hwmgr *hwmgr)
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if (smu7_init(hwmgr))
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if (smu7_init(hwmgr))
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return -EINVAL;
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return -EINVAL;
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for (i = 0; i < SMU72_MAX_LEVELS_GRAPHICS; i++)
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|
||||||
tonga_priv->activity_target[i] = 30;
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -708,7 +704,7 @@ static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
|
||||||
for (i = 0; i < dpm_table->sclk_table.count; i++) {
|
for (i = 0; i < dpm_table->sclk_table.count; i++) {
|
||||||
result = tonga_populate_single_graphic_level(hwmgr,
|
result = tonga_populate_single_graphic_level(hwmgr,
|
||||||
dpm_table->sclk_table.dpm_levels[i].value,
|
dpm_table->sclk_table.dpm_levels[i].value,
|
||||||
(uint16_t)smu_data->activity_target[i],
|
data->sclk_activity_target,
|
||||||
&(smu_data->smc_state_table.GraphicsLevel[i]));
|
&(smu_data->smc_state_table.GraphicsLevel[i]));
|
||||||
if (result != 0)
|
if (result != 0)
|
||||||
return result;
|
return result;
|
||||||
|
@ -1003,7 +999,7 @@ static int tonga_populate_single_memory_level(
|
||||||
memory_level->VoltageDownHyst = 0;
|
memory_level->VoltageDownHyst = 0;
|
||||||
|
|
||||||
/* Indicates maximum activity level for this performance level.*/
|
/* Indicates maximum activity level for this performance level.*/
|
||||||
memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
|
memory_level->ActivityLevel = data->mclk_activity_target;
|
||||||
memory_level->StutterEnable = 0;
|
memory_level->StutterEnable = 0;
|
||||||
memory_level->StrobeEnable = 0;
|
memory_level->StrobeEnable = 0;
|
||||||
memory_level->EdcReadEnable = 0;
|
memory_level->EdcReadEnable = 0;
|
||||||
|
@ -1293,7 +1289,7 @@ static int tonga_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
|
||||||
table->MemoryACPILevel.VoltageDownHyst = 0;
|
table->MemoryACPILevel.VoltageDownHyst = 0;
|
||||||
/* Indicates maximum activity level for this performance level.*/
|
/* Indicates maximum activity level for this performance level.*/
|
||||||
table->MemoryACPILevel.ActivityLevel =
|
table->MemoryACPILevel.ActivityLevel =
|
||||||
PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
|
PP_HOST_TO_SMC_US(data->mclk_activity_target);
|
||||||
|
|
||||||
table->MemoryACPILevel.StutterEnable = 0;
|
table->MemoryACPILevel.StutterEnable = 0;
|
||||||
table->MemoryACPILevel.StrobeEnable = 0;
|
table->MemoryACPILevel.StrobeEnable = 0;
|
||||||
|
|
|
@ -69,9 +69,6 @@ struct tonga_smumgr {
|
||||||
const struct tonga_pt_defaults *power_tune_defaults;
|
const struct tonga_pt_defaults *power_tune_defaults;
|
||||||
SMU72_Discrete_MCRegisters mc_regs;
|
SMU72_Discrete_MCRegisters mc_regs;
|
||||||
struct tonga_mc_reg_table mc_reg_table;
|
struct tonga_mc_reg_table mc_reg_table;
|
||||||
|
|
||||||
uint32_t activity_target[SMU72_MAX_LEVELS_GRAPHICS];
|
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
Loading…
Reference in a new issue