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arm64: tegra: Add CPU cache topology for Tegra186

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Tegra186 has two CPU clusters with its own cache hierarchy. This patch
adds them with the cache information of each of the CPUs.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Joseph Lo 2019-06-05 10:26:40 +08:00 committed by Thierry Reding
parent c4502cc3a1
commit 5298166d47
1 changed files with 60 additions and 0 deletions
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60
arch/arm64/boot/dts/nvidia/tegra186.dtsi
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@ -1128,38 +1128,98 @@ cpus {
cpu@0 {
compatible = "nvidia,tegra186-denver";
device_type = "cpu";
i-cache-size = <0x20000>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_DENVER>;
reg = <0x000>;
};
cpu@1 {
compatible = "nvidia,tegra186-denver";
device_type = "cpu";
i-cache-size = <0x20000>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_DENVER>;
reg = <0x001>;
};
cpu@2 {
compatible = "arm,cortex-a57";
device_type = "cpu";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_A57>;
reg = <0x100>;
};
cpu@3 {
compatible = "arm,cortex-a57";
device_type = "cpu";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_A57>;
reg = <0x101>;
};
cpu@4 {
compatible = "arm,cortex-a57";
device_type = "cpu";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_A57>;
reg = <0x102>;
};
cpu@5 {
compatible = "arm,cortex-a57";
device_type = "cpu";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_A57>;
reg = <0x103>;
};
L2_DENVER: l2-cache0 {
compatible = "cache";
cache-unified;
cache-level = <2>;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
};
L2_A57: l2-cache1 {
compatible = "cache";
cache-unified;
cache-level = <2>;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
};
};
bpmp: bpmp {