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powerpc/fsl_pci: Store the pci ctlr device ptr in the pci ctlr struct 

The pci controller structure has a provision to store the device structure
pointer of the corresponding platform device. Currently this information is
not stored during fsl pci controller initialization. This information is
required while dealing with iommu groups for pci devices connected to the
fsl pci controller. For the case where the pci devices can't be paritioned,
they would fall under the same device group as the pci controller.

This patch stores the platform device information in the pci controller
structure during initialization.

Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Varun Sethi 2013-01-14 16:58:00 +05:30 committed by Kumar Gala
parent e0e8398e3a
commit 52c5affc54
2 changed files with 8 additions and 3 deletions
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9
arch/powerpc/sysdev/fsl_pci.c
View File

@ -421,13 +421,16 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus)
}
}
int __init fsl_add_bridge(struct device_node *dev, int is_primary)
int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
{
int len;
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
u8 hdr_type, progif;
struct device_node *dev;
dev = pdev->dev.of_node;
if (!of_device_is_available(dev)) {
pr_warning("%s: disabled\n", dev->full_name);
@ -453,6 +456,8 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
if (!hose)
return -ENOMEM;
/* set platform device as the parent */
hose->parent = &pdev->dev;
hose->first_busno = bus_range ? bus_range[0] : 0x0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
@ -885,7 +890,7 @@ static int fsl_pci_probe(struct platform_device *pdev)
#endif
node = pdev->dev.of_node;
ret = fsl_add_bridge(node, fsl_pci_primary == node);
ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
#ifdef CONFIG_SWIOTLB
if (ret == 0) {

2
arch/powerpc/sysdev/fsl_pci.h
View File

@ -91,7 +91,7 @@ struct ccsr_pci {
__be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
};
extern int fsl_add_bridge(struct device_node *dev, int is_primary);
extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
extern int mpc83xx_add_bridge(struct device_node *dev);
u64 fsl_pci_immrbar_base(struct pci_controller *hose);