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PCI: tegra: Process pending DLL transactions before entering L1 or L2

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PM message are truncated while entering L1 or L2, which is resulting in
receiver errors. Set the required bit to finish processing DLLP before
link enter L1 or L2.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Manikanta Maddireddy 2019-06-18 23:31:50 +05:30 committed by Lorenzo Pieralisi
parent 92bd94f1fd
commit 52db2fd89e
1 changed files with 11 additions and 0 deletions
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11
drivers/pci/controller/pci-tegra.c
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@ -212,6 +212,9 @@
#define RP_VEND_CTL1 0x00000f48
#define RP_VEND_CTL1_ERPT (1 << 13)
#define RP_VEND_XP_BIST 0x00000f4c
#define RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE (1 << 28)
#define RP_VEND_CTL2 0x00000fa8
#define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
@ -538,6 +541,14 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
value |= RP_VEND_XP_OPPORTUNISTIC_ACK;
value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC;
writel(value, port->base + RP_VEND_XP);
/*
* LTSSM will wait for DLLP to finish before entering L1 or L2,
* to avoid truncation of PM messages which results in receiver errors
*/
value = readl(port->base + RP_VEND_XP_BIST);
value |= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE;
writel(value, port->base + RP_VEND_XP_BIST);
}
static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port)