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drm/i915/tgl: Add hpd interrupt handling
Add hotdplug detection for all ports on TGP. icp_hpd_detection_setup() is refactored to be shared with TGP. While we increase the number of pins, add a BUILD_BUG_ON() to avoid going over the number of bits allowed. v2: use BITS_PER_TYPE and correct type for BUILD_BUG_ON() check (requested by Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jose Souza <jose.souza@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190725234813.27179-2-lucas.demarchi@intel.com
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parent
e0e712fe42
commit
52dfdba0a9
4 changed files with 154 additions and 12 deletions
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@ -104,6 +104,12 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
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if (IS_CNL_WITH_PORT_F(dev_priv))
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return HPD_PORT_E;
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return HPD_PORT_F;
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case PORT_G:
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return HPD_PORT_G;
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case PORT_H:
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return HPD_PORT_H;
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case PORT_I:
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return HPD_PORT_I;
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default:
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MISSING_CASE(port);
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return HPD_NONE;
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@ -153,6 +153,10 @@ enum hpd_pin {
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HPD_PORT_D,
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HPD_PORT_E,
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HPD_PORT_F,
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HPD_PORT_G,
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HPD_PORT_H,
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HPD_PORT_I,
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HPD_NUM_PINS
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};
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@ -150,6 +150,18 @@ static const u32 hpd_mcc[HPD_NUM_PINS] = {
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[HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP
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};
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static const u32 hpd_tgp[HPD_NUM_PINS] = {
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[HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
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[HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
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[HPD_PORT_C] = SDE_DDIC_HOTPLUG_TGP,
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[HPD_PORT_D] = SDE_TC1_HOTPLUG_ICP,
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[HPD_PORT_E] = SDE_TC2_HOTPLUG_ICP,
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[HPD_PORT_F] = SDE_TC3_HOTPLUG_ICP,
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[HPD_PORT_G] = SDE_TC4_HOTPLUG_ICP,
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[HPD_PORT_H] = SDE_TC5_HOTPLUG_TGP,
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[HPD_PORT_I] = SDE_TC6_HOTPLUG_TGP,
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};
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static void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
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i915_reg_t iir, i915_reg_t ier)
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{
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@ -1724,6 +1736,40 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
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}
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}
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static bool tgp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
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{
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switch (pin) {
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case HPD_PORT_A:
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return val & ICP_DDIA_HPD_LONG_DETECT;
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case HPD_PORT_B:
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return val & ICP_DDIB_HPD_LONG_DETECT;
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case HPD_PORT_C:
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return val & TGP_DDIC_HPD_LONG_DETECT;
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default:
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return false;
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}
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}
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static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
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{
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switch (pin) {
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case HPD_PORT_D:
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return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
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case HPD_PORT_E:
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return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
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case HPD_PORT_F:
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return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
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case HPD_PORT_G:
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return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
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case HPD_PORT_H:
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return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
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case HPD_PORT_I:
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return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
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default:
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return false;
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}
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}
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static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
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{
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switch (pin) {
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@ -1803,6 +1849,8 @@ static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
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{
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enum hpd_pin pin;
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BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
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for_each_hpd_pin(pin) {
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if ((hpd[pin] & hotplug_trigger) == 0)
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continue;
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@ -2561,6 +2609,43 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir,
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gmbus_irq_handler(dev_priv);
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}
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static void tgp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
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{
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u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
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u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
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u32 pin_mask = 0, long_mask = 0;
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if (ddi_hotplug_trigger) {
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u32 dig_hotplug_reg;
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dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
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I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
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intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
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ddi_hotplug_trigger,
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dig_hotplug_reg, hpd_tgp,
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tgp_ddi_port_hotplug_long_detect);
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}
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if (tc_hotplug_trigger) {
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u32 dig_hotplug_reg;
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dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
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I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
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intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
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tc_hotplug_trigger,
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dig_hotplug_reg, hpd_tgp,
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tgp_tc_port_hotplug_long_detect);
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}
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if (pin_mask)
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intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
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if (pch_iir & SDE_GMBUS_ICP)
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gmbus_irq_handler(dev_priv);
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}
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static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
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{
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u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
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@ -2983,7 +3068,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
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I915_WRITE(SDEIIR, iir);
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ret = IRQ_HANDLED;
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if (INTEL_PCH_TYPE(dev_priv) >= PCH_MCC)
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if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
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tgp_irq_handler(dev_priv, iir);
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else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MCC)
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icp_irq_handler(dev_priv, iir, hpd_mcc);
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else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
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icp_irq_handler(dev_priv, iir, hpd_icp);
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@ -3778,20 +3865,18 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
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ibx_hpd_detection_setup(dev_priv);
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}
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static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv)
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static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv,
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u32 ddi_hotplug_enable_mask,
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u32 tc_hotplug_enable_mask)
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{
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u32 hotplug;
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hotplug = I915_READ(SHOTPLUG_CTL_DDI);
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hotplug |= ICP_DDIA_HPD_ENABLE |
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ICP_DDIB_HPD_ENABLE;
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hotplug |= ddi_hotplug_enable_mask;
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I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
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hotplug = I915_READ(SHOTPLUG_CTL_TC);
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hotplug |= ICP_TC_HPD_ENABLE(PORT_TC1) |
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ICP_TC_HPD_ENABLE(PORT_TC2) |
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ICP_TC_HPD_ENABLE(PORT_TC3) |
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ICP_TC_HPD_ENABLE(PORT_TC4);
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hotplug |= tc_hotplug_enable_mask;
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I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
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}
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@ -3804,7 +3889,21 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
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ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
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icp_hpd_detection_setup(dev_priv);
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icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK,
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ICP_TC_HPD_ENABLE_MASK);
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}
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static void tgp_hpd_irq_setup(struct drm_i915_private *dev_priv)
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{
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u32 hotplug_irqs, enabled_irqs;
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hotplug_irqs = SDE_DDI_MASK_TGP | SDE_TC_MASK_TGP;
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enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_tgp);
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ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
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icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
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TGP_TC_HPD_ENABLE_MASK);
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}
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static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
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@ -3841,7 +3940,9 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
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gen11_hpd_detection_setup(dev_priv);
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if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
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if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
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tgp_hpd_irq_setup(dev_priv);
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else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
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icp_hpd_irq_setup(dev_priv);
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}
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@ -4291,7 +4392,12 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
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gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
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I915_WRITE(SDEIMR, ~mask);
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icp_hpd_detection_setup(dev_priv);
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if (HAS_PCH_TGP(dev_priv))
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icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
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TGP_TC_HPD_ENABLE_MASK);
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else
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icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK,
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ICP_TC_HPD_ENABLE_MASK);
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}
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static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
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@ -7861,12 +7861,15 @@ enum {
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SDE_FDI_RXB_CPT | \
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SDE_FDI_RXA_CPT)
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/* south display engine interrupt: ICP */
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/* south display engine interrupt: ICP/TGP */
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#define SDE_TC6_HOTPLUG_TGP (1 << 29)
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#define SDE_TC5_HOTPLUG_TGP (1 << 28)
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#define SDE_TC4_HOTPLUG_ICP (1 << 27)
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#define SDE_TC3_HOTPLUG_ICP (1 << 26)
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#define SDE_TC2_HOTPLUG_ICP (1 << 25)
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#define SDE_TC1_HOTPLUG_ICP (1 << 24)
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#define SDE_GMBUS_ICP (1 << 23)
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#define SDE_DDIC_HOTPLUG_TGP (1 << 18)
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#define SDE_DDIB_HOTPLUG_ICP (1 << 17)
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#define SDE_DDIA_HOTPLUG_ICP (1 << 16)
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#define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24))
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@ -7877,6 +7880,11 @@ enum {
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SDE_TC3_HOTPLUG_ICP | \
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SDE_TC2_HOTPLUG_ICP | \
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SDE_TC1_HOTPLUG_ICP)
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#define SDE_DDI_MASK_TGP (SDE_DDIC_HOTPLUG_TGP | \
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SDE_DDI_MASK_ICP)
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#define SDE_TC_MASK_TGP (SDE_TC6_HOTPLUG_TGP | \
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SDE_TC5_HOTPLUG_TGP | \
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SDE_TC_MASK_ICP)
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#define SDEISR _MMIO(0xc4000)
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#define SDEIMR _MMIO(0xc4004)
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@ -7944,6 +7952,12 @@ enum {
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*/
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#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
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#define TGP_DDIC_HPD_ENABLE (1 << 11)
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#define TGP_DDIC_HPD_STATUS_MASK (3 << 8)
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#define TGP_DDIC_HPD_NO_DETECT (0 << 8)
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#define TGP_DDIC_HPD_SHORT_DETECT (1 << 8)
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#define TGP_DDIC_HPD_LONG_DETECT (2 << 8)
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#define TGP_DDIC_HPD_SHORT_LONG_DETECT (3 << 8)
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#define ICP_DDIB_HPD_ENABLE (1 << 7)
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#define ICP_DDIB_HPD_STATUS_MASK (3 << 4)
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#define ICP_DDIB_HPD_NO_DETECT (0 << 4)
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@ -8067,6 +8081,18 @@ enum {
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#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
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#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
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#define ICP_DDI_HPD_ENABLE_MASK (ICP_DDIB_HPD_ENABLE | \
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ICP_DDIA_HPD_ENABLE)
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#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC4) | \
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ICP_TC_HPD_ENABLE(PORT_TC3) | \
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ICP_TC_HPD_ENABLE(PORT_TC2) | \
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ICP_TC_HPD_ENABLE(PORT_TC1))
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#define TGP_DDI_HPD_ENABLE_MASK (TGP_DDIC_HPD_ENABLE | \
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ICP_DDI_HPD_ENABLE_MASK)
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#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \
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ICP_TC_HPD_ENABLE(PORT_TC5) | \
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ICP_TC_HPD_ENABLE_MASK)
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#define _PCH_DPLL_A 0xc6014
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#define _PCH_DPLL_B 0xc6018
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#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
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