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drm/omap: omap_display_timings: Use display_flags for interlace mode
Remove the interlace member and add display_flags to omap_video_timings to configure the interlace mode. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
parent
fe70cd7667
commit
530582998a
10 changed files with 21 additions and 22 deletions
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@ -40,7 +40,7 @@ static const struct omap_video_timings tvc_pal_timings = {
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.vfront_porch = 5,
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.vback_porch = 41,
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.interlace = true,
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.flags = DISPLAY_FLAGS_INTERLACED,
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};
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static const struct of_device_id tvc_of_match[];
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@ -34,8 +34,6 @@ static const struct omap_video_timings hdmic_default_timings = {
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.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.interlace = false,
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};
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struct panel_drv_data {
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@ -2607,7 +2607,7 @@ static int dispc_ovl_setup_common(enum omap_plane plane,
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u16 in_height = height;
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u16 in_width = width;
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int x_predecim = 1, y_predecim = 1;
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bool ilace = mgr_timings->interlace;
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bool ilace = !!(mgr_timings->flags & DISPLAY_FLAGS_INTERLACED);
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unsigned long pclk = dispc_plane_pclk_rate(plane);
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unsigned long lclk = dispc_plane_lclk_rate(plane);
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@ -3128,7 +3128,7 @@ bool dispc_mgr_timings_ok(enum omap_channel channel,
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if (dss_mgr_is_lcd(channel)) {
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/* TODO: OMAP4+ supports interlace for LCD outputs */
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if (timings->interlace)
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if (timings->flags & DISPLAY_FLAGS_INTERLACED)
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return false;
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if (!_dispc_lcd_timings_ok(timings->hsync_len,
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@ -3292,7 +3292,7 @@ void dispc_mgr_set_timings(enum omap_channel channel,
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DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
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} else {
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if (t.interlace)
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if (t.flags & DISPLAY_FLAGS_INTERLACED)
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t.vactive /= 2;
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if (dispc.feat->supports_double_pixel)
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@ -4232,7 +4232,6 @@ static const struct dispc_errata_i734_data {
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.vsync_len = 1, .vfront_porch = 1, .vback_porch = 1,
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.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.interlace = false,
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.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
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.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
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.sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
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@ -4122,7 +4122,7 @@ static int dsi_display_init_dispc(struct platform_device *dsidev,
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* override interlace, logic level and edge related parameters in
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* omap_video_timings with default values
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*/
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dsi->timings.interlace = false;
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dsi->timings.flags &= ~DISPLAY_FLAGS_INTERLACED;
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dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
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dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
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dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
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@ -303,7 +303,7 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
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cfg->timings.vback_porch;
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video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode;
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if (cfg->timings.interlace) {
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if (cfg->timings.flags & DISPLAY_FLAGS_INTERLACED) {
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/* set vblank_osc if vblank is fractional */
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if (video_cfg->vblank % 2 != 0)
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video_cfg->vblank_osc = 1;
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@ -342,7 +342,7 @@ static void hdmi_core_video_config(struct hdmi_core_data *core,
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r = FLD_MOD(r, hsync_pol, 5, 5);
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r = FLD_MOD(r, cfg->data_enable_pol, 4, 4);
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r = FLD_MOD(r, cfg->vblank_osc, 1, 1);
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r = FLD_MOD(r, ovt->interlace, 0, 0);
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r = FLD_MOD(r, !!(ovt->flags & DISPLAY_FLAGS_INTERLACED), 0, 0);
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hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r);
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/* set x resolution */
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@ -156,7 +156,7 @@ void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
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r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
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r = FLD_MOD(r, vsync_pol, 7, 7);
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r = FLD_MOD(r, hsync_pol, 6, 6);
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r = FLD_MOD(r, timings->interlace, 3, 3);
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r = FLD_MOD(r, !!(timings->flags & DISPLAY_FLAGS_INTERLACED), 3, 3);
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r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
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hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);
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}
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@ -210,10 +210,10 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
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timings->vsync_level = param->timings.vsync_level;
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timings->hsync_level = param->timings.hsync_level;
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timings->interlace = param->timings.interlace;
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timings->double_pixel = param->timings.double_pixel;
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timings->flags = param->timings.flags;
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if (param->timings.interlace) {
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if (param->timings.flags & DISPLAY_FLAGS_INTERLACED) {
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video_fmt->y_res /= 2;
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timings->vback_porch /= 2;
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timings->vfront_porch /= 2;
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@ -323,8 +323,6 @@ struct omap_video_timings {
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enum omap_dss_signal_level vsync_level;
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/* Hsync logic level */
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enum omap_dss_signal_level hsync_level;
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/* Interlaced or Progressive timings */
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bool interlace;
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/* Pixel clock edge to drive LCD data */
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enum omap_dss_signal_edge data_pclk_edge;
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/* Data enable logic level */
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@ -333,6 +331,8 @@ struct omap_video_timings {
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enum omap_dss_signal_edge sync_pclk_edge;
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bool double_pixel;
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enum display_flags flags;
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};
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/* Hardcoded timings for tv modes. Venc only uses these to
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@ -865,7 +865,7 @@ static void rfbi_config_lcd_manager(struct omap_dss_device *dssdev)
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rfbi.timings.vfront_porch = 0;
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rfbi.timings.vback_porch = 0;
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rfbi.timings.interlace = false;
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rfbi.timings.flags &= ~DISPLAY_FLAGS_INTERLACED;
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rfbi.timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
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rfbi.timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
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rfbi.timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
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@ -273,13 +273,13 @@ const struct omap_video_timings omap_dss_pal_timings = {
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.vfront_porch = 5,
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.vback_porch = 41,
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.interlace = true,
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.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
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.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
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.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
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.flags = DISPLAY_FLAGS_INTERLACED,
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};
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EXPORT_SYMBOL(omap_dss_pal_timings);
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@ -294,13 +294,13 @@ const struct omap_video_timings omap_dss_ntsc_timings = {
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.vfront_porch = 6,
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.vback_porch = 31,
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.interlace = true,
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.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
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.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
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.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
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.flags = DISPLAY_FLAGS_INTERLACED,
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};
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EXPORT_SYMBOL(omap_dss_ntsc_timings);
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@ -59,7 +59,7 @@ void copy_timings_omap_to_drm(struct drm_display_mode *mode,
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mode->flags = 0;
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if (timings->interlace)
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if (timings->flags & DISPLAY_FLAGS_INTERLACED)
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mode->flags |= DRM_MODE_FLAG_INTERLACE;
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if (timings->double_pixel)
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@ -91,7 +91,9 @@ void copy_timings_drm_to_omap(struct omap_video_timings *timings,
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timings->vsync_len = mode->vsync_end - mode->vsync_start;
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timings->vback_porch = mode->vtotal - mode->vsync_end;
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timings->interlace = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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timings->flags |= DISPLAY_FLAGS_INTERLACED;
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timings->double_pixel = !!(mode->flags & DRM_MODE_FLAG_DBLCLK);
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if (mode->flags & DRM_MODE_FLAG_PHSYNC)
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