mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-09 01:59:41 +00:00
Device tree updates towards 5.10-rc1 for TI K3 platform.
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This commit is contained in:
Olof Johansson
commit
5310d705a9
11 changed files with 608 additions and 152 deletions
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@ -112,7 +112,29 @@ main_uart2: serial@2820000 {
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power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
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};
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main_pmx0: pinmux@11c000 {
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crypto: crypto@4e00000 {
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compatible = "ti,am654-sa2ul";
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reg = <0x0 0x4e00000 0x0 0x1200>;
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power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
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status = "okay";
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dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
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<&main_udmap 0x4001>;
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dma-names = "tx", "rx1", "rx2";
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dma-coherent;
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rng: rng@4e10000 {
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compatible = "inside-secure,safexcel-eip76";
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reg = <0x0 0x4e10000 0x0 0x7d>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 136 1>;
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};
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};
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main_pmx0: pinctrl@11c000 {
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compatible = "pinctrl-single";
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reg = <0x0 0x11c000 0x0 0x2e4>;
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#pinctrl-cells = <1>;
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@ -120,7 +142,7 @@ main_pmx0: pinmux@11c000 {
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pinctrl-single,function-mask = <0xffffffff>;
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};
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main_pmx1: pinmux@11c2e8 {
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main_pmx1: pinctrl@11c2e8 {
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compatible = "pinctrl-single";
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reg = <0x0 0x11c2e8 0x0 0x24>;
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#pinctrl-cells = <1>;
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@ -283,7 +305,7 @@ sdhci1: sdhci@4fa0000 {
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no-1-8-v;
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};
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scm_conf: scm_conf@100000 {
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scm_conf: scm-conf@100000 {
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compatible = "syscon", "simple-mfd";
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reg = <0 0x00100000 0 0x1c000>;
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#address-cells = <1>;
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@ -305,12 +327,12 @@ pcie_devid: pcie-devid@210 {
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reg = <0x00000210 0x4>;
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};
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serdes0_clk: serdes_clk@4080 {
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serdes0_clk: clock@4080 {
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compatible = "syscon";
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reg = <0x00004080 0x4>;
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};
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serdes1_clk: serdes_clk@4090 {
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serdes1_clk: clock@4090 {
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compatible = "syscon";
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reg = <0x00004090 0x4>;
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};
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@ -322,12 +344,12 @@ serdes_mux: mux-controller {
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<0x4090 0x3>; /* SERDES1 lane select */
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};
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dss_oldi_io_ctrl: dss_oldi_io_ctrl@41E0 {
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dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
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compatible = "syscon";
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reg = <0x0000041E0 0x14>;
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reg = <0x0000041e0 0x14>;
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};
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ehrpwm_tbclk: syscon@4140 {
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ehrpwm_tbclk: clock@4140 {
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compatible = "ti,am654-ehrpwm-tbclk", "syscon";
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reg = <0x4140 0x18>;
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#clock-cells = <1>;
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@ -423,7 +445,7 @@ intr_main_gpio: interrupt-controller0 {
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ti,interrupt-ranges = <0 392 32>;
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};
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main_navss {
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main-navss {
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compatible = "simple-mfd";
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#address-cells = <2>;
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#size-cells = <2>;
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@ -639,7 +661,7 @@ main_cpts_mux: refclk-mux {
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};
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};
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main_gpio0: main_gpio0@600000 {
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main_gpio0: gpio@600000 {
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compatible = "ti,am654-gpio", "ti,keystone-gpio";
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reg = <0x0 0x600000 0x0 0x100>;
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gpio-controller;
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@ -654,7 +676,7 @@ main_gpio0: main_gpio0@600000 {
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clock-names = "gpio";
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};
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main_gpio1: main_gpio1@601000 {
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main_gpio1: gpio@601000 {
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compatible = "ti,am654-gpio", "ti,keystone-gpio";
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reg = <0x0 0x601000 0x0 0x100>;
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gpio-controller;
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@ -682,7 +704,7 @@ pcie0_rc: pcie@5500000 {
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ti,syscon-pcie-mode = <&pcie0_mode>;
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bus-range = <0x0 0xff>;
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num-viewport = <16>;
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max-link-speed = <3>;
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max-link-speed = <2>;
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dma-coherent;
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interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
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msi-map = <0x0 &gic_its 0x0 0x10000>;
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@ -696,7 +718,7 @@ pcie0_ep: pcie-ep@5500000 {
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ti,syscon-pcie-mode = <&pcie0_mode>;
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num-ib-windows = <16>;
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num-ob-windows = <16>;
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max-link-speed = <3>;
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max-link-speed = <2>;
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dma-coherent;
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interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
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};
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@ -714,7 +736,7 @@ pcie1_rc: pcie@5600000 {
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ti,syscon-pcie-mode = <&pcie1_mode>;
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bus-range = <0x0 0xff>;
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num-viewport = <16>;
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max-link-speed = <3>;
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max-link-speed = <2>;
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dma-coherent;
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interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
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msi-map = <0x0 &gic_its 0x10000 0x10000>;
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@ -728,7 +750,7 @@ pcie1_ep: pcie-ep@5600000 {
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ti,syscon-pcie-mode = <&pcie1_mode>;
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num-ib-windows = <16>;
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num-ob-windows = <16>;
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max-link-speed = <3>;
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max-link-speed = <2>;
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dma-coherent;
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interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
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};
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@ -6,7 +6,7 @@
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*/
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&cbass_mcu {
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mcu_conf: scm_conf@40f00000 {
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mcu_conf: scm-conf@40f00000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x0 0x40f00000 0x0 0x20000>;
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#address-cells = <1>;
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@ -116,7 +116,7 @@ adc {
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};
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};
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mcu_navss {
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mcu-navss {
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compatible = "simple-mfd";
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#address-cells = <2>;
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#size-cells = <2>;
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@ -39,7 +39,7 @@ chipid@43000014 {
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reg = <0x43000014 0x4>;
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};
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wkup_pmx0: pinmux@4301c000 {
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wkup_pmx0: pinctrl@4301c000 {
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compatible = "pinctrl-single";
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reg = <0x4301c000 0x118>;
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#pinctrl-cells = <1>;
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@ -80,7 +80,7 @@ intr_wkup_gpio: interrupt-controller2 {
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ti,interrupt-ranges = <0 712 16>;
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};
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wkup_gpio0: wkup_gpio0@42110000 {
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wkup_gpio0: gpio@42110000 {
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compatible = "ti,am654-gpio", "ti,keystone-gpio";
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reg = <0x42110000 0x100>;
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gpio-controller;
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@ -95,7 +95,7 @@ wkup_gpio0: wkup_gpio0@42110000 {
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clock-names = "gpio";
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};
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wkup_vtm0: thermal@42050000 {
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wkup_vtm0: temperature-sensor@42050000 {
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compatible = "ti,am654-vtm";
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reg = <0x42050000 0x25c>;
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power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
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@ -61,7 +61,7 @@ pmu: pmu {
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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cbass_main: interconnect@100000 {
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cbass_main: bus@100000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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@ -88,7 +88,7 @@ cbass_main: interconnect@100000 {
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<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
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<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
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cbass_mcu: interconnect@28380000 {
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cbass_mcu: bus@28380000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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@ -106,7 +106,7 @@ cbass_mcu: interconnect@28380000 {
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<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
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<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
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cbass_wakeup: interconnect@42040000 {
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cbass_wakeup: bus@42040000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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@ -29,7 +29,7 @@ reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure_ddr: secure_ddr@9e800000 {
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secure_ddr: secure-ddr@9e800000 {
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reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
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alignment = <0x1000>;
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no-map;
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@ -70,14 +70,14 @@ AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
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>;
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};
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push_button_pins_default: push_button__pins_default {
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push_button_pins_default: push-button-pins-default {
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pinctrl-single,pins = <
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AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
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AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
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>;
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};
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mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
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mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
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pinctrl-single,pins = <
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AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
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AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
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@ -93,13 +93,13 @@ AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
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>;
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};
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wkup_pca554_default: wkup_pca554_default {
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wkup_pca554_default: wkup-pca554-default {
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pinctrl-single,pins = <
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AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
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>;
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};
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mcu_cpsw_pins_default: mcu_cpsw_pins_default {
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mcu_cpsw_pins_default: mcu-cpsw-pins-default {
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pinctrl-single,pins = <
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AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
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AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
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@ -116,7 +116,7 @@ AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
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>;
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};
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mcu_mdio_pins_default: mcu_mdio1_pins_default {
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mcu_mdio_pins_default: mcu-mdio1-pins-default {
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pinctrl-single,pins = <
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AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
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AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
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@ -167,7 +167,7 @@ AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
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>;
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};
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main_mmc1_pins_default: main_mmc1_pins_default {
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main_mmc1_pins_default: main-mmc1-pins-default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
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AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
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@ -180,7 +180,7 @@ AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
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>;
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};
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usb1_pins_default: usb1_pins_default {
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usb1_pins_default: usb1-pins-default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
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>;
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@ -257,7 +257,7 @@ &main_i2c1 {
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pinctrl-0 = <&main_i2c1_pins_default>;
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clock-frequency = <400000>;
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ov5640@3c {
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ov5640: camera@3c {
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compatible = "ovti,ov5640";
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reg = <0x3c>;
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@ -2,13 +2,13 @@
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#include <dt-bindings/thermal/thermal.h>
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mpu0_thermal: mpu0_thermal {
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mpu0_thermal: mpu0-thermal {
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polling-delay-passive = <250>; /* milliseconds */
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polling-delay = <500>; /* milliseconds */
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thermal-sensors = <&wkup_vtm0 0>;
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trips {
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mpu0_crit: mpu0_crit {
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mpu0_crit: mpu0-crit {
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temperature = <125000>; /* milliCelsius */
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hysteresis = <2000>; /* milliCelsius */
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type = "critical";
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@ -16,13 +16,13 @@ mpu0_crit: mpu0_crit {
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|||
};
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};
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mpu1_thermal: mpu1_thermal {
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mpu1_thermal: mpu1-thermal {
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polling-delay-passive = <250>; /* milliseconds */
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polling-delay = <500>; /* milliseconds */
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thermal-sensors = <&wkup_vtm0 1>;
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trips {
|
||||
mpu1_crit: mpu1_crit {
|
||||
mpu1_crit: mpu1-crit {
|
||||
temperature = <125000>; /* milliCelsius */
|
||||
hysteresis = <2000>; /* milliCelsius */
|
||||
type = "critical";
|
||||
|
|
@ -30,13 +30,13 @@ mpu1_crit: mpu1_crit {
|
|||
};
|
||||
};
|
||||
|
||||
mcu_thermal: mcu_thermal {
|
||||
mcu_thermal: mcu-thermal {
|
||||
polling-delay-passive = <250>; /* milliseconds */
|
||||
polling-delay = <500>; /* milliseconds */
|
||||
thermal-sensors = <&wkup_vtm0 2>;
|
||||
|
||||
trips {
|
||||
mcu_crit: mcu_crit {
|
||||
mcu_crit: mcu-crit {
|
||||
temperature = <125000>; /* milliCelsius */
|
||||
hysteresis = <2000>; /* milliCelsius */
|
||||
type = "critical";
|
||||
|
|
|
|||
|
|
@ -86,13 +86,13 @@ sound0: sound@0 {
|
|||
};
|
||||
|
||||
&main_pmx0 {
|
||||
sw10_button_pins_default: sw10_button_pins_default {
|
||||
sw10_button_pins_default: sw10-button-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_mmc1_pins_default: main_mmc1_pins_default {
|
||||
main_mmc1_pins_default: main-mmc1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
|
||||
J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
|
||||
|
|
@ -106,14 +106,14 @@ J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
|
|||
>;
|
||||
};
|
||||
|
||||
main_usbss0_pins_default: main_usbss0_pins_default {
|
||||
main_usbss0_pins_default: main-usbss0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
|
||||
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_usbss1_pins_default: main_usbss1_pins_default {
|
||||
main_usbss1_pins_default: main-usbss1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
|
||||
>;
|
||||
|
|
@ -153,7 +153,7 @@ J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
|
|||
>;
|
||||
};
|
||||
|
||||
mcasp10_pins_default: mcasp10_pins_default {
|
||||
mcasp10_pins_default: mcasp10-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
|
||||
J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
|
||||
|
|
@ -167,7 +167,7 @@ J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */
|
|||
>;
|
||||
};
|
||||
|
||||
audi_ext_refclk2_pins_default: audi_ext_refclk2_pins_default {
|
||||
audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
|
||||
>;
|
||||
|
|
@ -175,7 +175,7 @@ J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
|
|||
};
|
||||
|
||||
&wkup_pmx0 {
|
||||
sw11_button_pins_default: sw11_button_pins_default {
|
||||
sw11_button_pins_default: sw11-button-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
|
||||
>;
|
||||
|
|
@ -194,7 +194,7 @@ J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
|
|||
>;
|
||||
};
|
||||
|
||||
mcu_cpsw_pins_default: mcu_cpsw_pins_default {
|
||||
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
|
||||
J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
|
||||
|
|
@ -211,7 +211,7 @@ J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
|
|||
>;
|
||||
};
|
||||
|
||||
mcu_mdio_pins_default: mcu_mdio1_pins_default {
|
||||
mcu_mdio_pins_default: mcu-mdio1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
|
||||
J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
|
||||
|
|
@ -286,99 +286,6 @@ &wkup_gpio1 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
interrupts = <428>;
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
interrupts = <424>;
|
||||
|
||||
mbox_c66_0: mbox-c66-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_c66_1: mbox-c66-1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
interrupts = <420>;
|
||||
|
||||
mbox_c71_0: mbox-c71-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster7 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster8 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster9 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster10 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster11 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_sdhci0 {
|
||||
/* eMMC */
|
||||
non-removable;
|
||||
|
|
@ -651,3 +558,83 @@ &mcasp10 {
|
|||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
serdes0_pcie_link: link@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <1>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_PCIE>;
|
||||
resets = <&serdes_wiz0 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&serdes1 {
|
||||
serdes1_pcie_link: link@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <2>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_PCIE>;
|
||||
resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&serdes2 {
|
||||
serdes2_pcie_link: link@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <2>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_PCIE>;
|
||||
resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0_rc {
|
||||
reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
|
||||
phys = <&serdes0_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <1>;
|
||||
};
|
||||
|
||||
&pcie1_rc {
|
||||
reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
|
||||
phys = <&serdes1_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <2>;
|
||||
};
|
||||
|
||||
&pcie2_rc {
|
||||
reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
|
||||
phys = <&serdes2_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <2>;
|
||||
};
|
||||
|
||||
&pcie0_ep {
|
||||
phys = <&serdes0_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie1_ep {
|
||||
phys = <&serdes1_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie2_ep {
|
||||
phys = <&serdes2_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie3_rc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie3_ep {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -28,7 +28,39 @@ scm_conf: scm-conf@100000 {
|
|||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x00100000 0x1c000>;
|
||||
|
||||
serdes_ln_ctrl: serdes-ln-ctrl@4080 {
|
||||
pcie0_ctrl: syscon@4070 {
|
||||
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
|
||||
reg = <0x00004070 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x4070 0x4070 0x4>;
|
||||
};
|
||||
|
||||
pcie1_ctrl: syscon@4074 {
|
||||
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
|
||||
reg = <0x00004074 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x4074 0x4074 0x4>;
|
||||
};
|
||||
|
||||
pcie2_ctrl: syscon@4078 {
|
||||
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
|
||||
reg = <0x00004078 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x4078 0x4078 0x4>;
|
||||
};
|
||||
|
||||
pcie3_ctrl: syscon@407c {
|
||||
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
|
||||
reg = <0x0000407c 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x407c 0x407c 0x4>;
|
||||
};
|
||||
|
||||
serdes_ln_ctrl: mux@4080 {
|
||||
compatible = "mmio-mux";
|
||||
reg = <0x00004080 0x50>;
|
||||
#mux-control-cells = <1>;
|
||||
|
|
@ -86,7 +118,7 @@ main_gpio_intr: interrupt-controller0 {
|
|||
ti,interrupt-ranges = <8 392 56>;
|
||||
};
|
||||
|
||||
main_navss {
|
||||
main-navss {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -304,7 +336,30 @@ cpts@310d0000 {
|
|||
};
|
||||
};
|
||||
|
||||
main_pmx0: pinmux@11c000 {
|
||||
main_crypto: crypto@4e00000 {
|
||||
compatible = "ti,j721e-sa2ul";
|
||||
reg = <0x0 0x4e00000 0x0 0x1200>;
|
||||
power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
|
||||
<&main_udmap 0x4001>;
|
||||
dma-names = "tx", "rx1", "rx2";
|
||||
dma-coherent;
|
||||
|
||||
rng: rng@4e10000 {
|
||||
compatible = "inside-secure,safexcel-eip76";
|
||||
reg = <0x0 0x4e10000 0x0 0x7d>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&k3_clks 264 1>;
|
||||
};
|
||||
};
|
||||
|
||||
main_pmx0: pinctrl@11c000 {
|
||||
compatible = "pinctrl-single";
|
||||
/* Proxy 0 addressing */
|
||||
reg = <0x0 0x11c000 0x0 0x2b4>;
|
||||
|
|
@ -553,6 +608,204 @@ serdes3: serdes@5030000 {
|
|||
};
|
||||
};
|
||||
|
||||
pcie0_rc: pcie@2900000 {
|
||||
compatible = "ti,j721e-pcie-host";
|
||||
reg = <0x00 0x02900000 0x00 0x1000>,
|
||||
<0x00 0x02907000 0x00 0x400>,
|
||||
<0x00 0x0d000000 0x00 0x00800000>,
|
||||
<0x00 0x10000000 0x00 0x00001000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 239 1>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x0 0xf>;
|
||||
vendor-id = <0x104c>;
|
||||
device-id = <0xb00d>;
|
||||
msi-map = <0x0 &gic_its 0x0 0x10000>;
|
||||
dma-coherent;
|
||||
ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
|
||||
<0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
|
||||
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
|
||||
};
|
||||
|
||||
pcie0_ep: pcie-ep@2900000 {
|
||||
compatible = "ti,j721e-pcie-ep";
|
||||
reg = <0x00 0x02900000 0x00 0x1000>,
|
||||
<0x00 0x02907000 0x00 0x400>,
|
||||
<0x00 0x0d000000 0x00 0x00800000>,
|
||||
<0x00 0x10000000 0x00 0x08000000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
|
||||
ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 239 1>;
|
||||
clock-names = "fck";
|
||||
cdns,max-outbound-regions = <16>;
|
||||
max-functions = /bits/ 8 <6>;
|
||||
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
pcie1_rc: pcie@2910000 {
|
||||
compatible = "ti,j721e-pcie-host";
|
||||
reg = <0x00 0x02910000 0x00 0x1000>,
|
||||
<0x00 0x02917000 0x00 0x400>,
|
||||
<0x00 0x0d800000 0x00 0x00800000>,
|
||||
<0x00 0x18000000 0x00 0x00001000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 240 1>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x0 0xf>;
|
||||
vendor-id = <0x104c>;
|
||||
device-id = <0xb00d>;
|
||||
msi-map = <0x0 &gic_its 0x10000 0x10000>;
|
||||
dma-coherent;
|
||||
ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
|
||||
<0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
|
||||
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
|
||||
};
|
||||
|
||||
pcie1_ep: pcie-ep@2910000 {
|
||||
compatible = "ti,j721e-pcie-ep";
|
||||
reg = <0x00 0x02910000 0x00 0x1000>,
|
||||
<0x00 0x02917000 0x00 0x400>,
|
||||
<0x00 0x0d800000 0x00 0x00800000>,
|
||||
<0x00 0x18000000 0x00 0x08000000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
|
||||
ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 240 1>;
|
||||
clock-names = "fck";
|
||||
cdns,max-outbound-regions = <16>;
|
||||
max-functions = /bits/ 8 <6>;
|
||||
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
pcie2_rc: pcie@2920000 {
|
||||
compatible = "ti,j721e-pcie-host";
|
||||
reg = <0x00 0x02920000 0x00 0x1000>,
|
||||
<0x00 0x02927000 0x00 0x400>,
|
||||
<0x00 0x0e000000 0x00 0x00800000>,
|
||||
<0x44 0x00000000 0x00 0x00001000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 241 1>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x0 0xf>;
|
||||
vendor-id = <0x104c>;
|
||||
device-id = <0xb00d>;
|
||||
msi-map = <0x0 &gic_its 0x20000 0x10000>;
|
||||
dma-coherent;
|
||||
ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
|
||||
<0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
|
||||
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
|
||||
};
|
||||
|
||||
pcie2_ep: pcie-ep@2920000 {
|
||||
compatible = "ti,j721e-pcie-ep";
|
||||
reg = <0x00 0x02920000 0x00 0x1000>,
|
||||
<0x00 0x02927000 0x00 0x400>,
|
||||
<0x00 0x0e000000 0x00 0x00800000>,
|
||||
<0x44 0x00000000 0x00 0x08000000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
|
||||
ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 241 1>;
|
||||
clock-names = "fck";
|
||||
cdns,max-outbound-regions = <16>;
|
||||
max-functions = /bits/ 8 <6>;
|
||||
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
pcie3_rc: pcie@2930000 {
|
||||
compatible = "ti,j721e-pcie-host";
|
||||
reg = <0x00 0x02930000 0x00 0x1000>,
|
||||
<0x00 0x02937000 0x00 0x400>,
|
||||
<0x00 0x0e800000 0x00 0x00800000>,
|
||||
<0x44 0x10000000 0x00 0x00001000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 242 1>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x0 0xf>;
|
||||
vendor-id = <0x104c>;
|
||||
device-id = <0xb00d>;
|
||||
msi-map = <0x0 &gic_its 0x30000 0x10000>;
|
||||
dma-coherent;
|
||||
ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
|
||||
<0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
|
||||
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
|
||||
};
|
||||
|
||||
pcie3_ep: pcie-ep@2930000 {
|
||||
compatible = "ti,j721e-pcie-ep";
|
||||
reg = <0x00 0x02930000 0x00 0x1000>,
|
||||
<0x00 0x02937000 0x00 0x400>,
|
||||
<0x00 0x0e800000 0x00 0x00800000>,
|
||||
<0x44 0x10000000 0x00 0x08000000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
|
||||
ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 242 1>;
|
||||
clock-names = "fck";
|
||||
cdns,max-outbound-regions = <16>;
|
||||
max-functions = /bits/ 8 <6>;
|
||||
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
|
||||
dma-coherent;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
};
|
||||
|
||||
main_uart0: serial@2800000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02800000 0x00 0x100>;
|
||||
|
|
@ -865,7 +1118,7 @@ main_sdhci2: sdhci@4f98000 {
|
|||
no-1-8-v;
|
||||
};
|
||||
|
||||
usbss0: cdns_usb@4104000 {
|
||||
usbss0: cdns-usb@4104000 {
|
||||
compatible = "ti,j721e-usb";
|
||||
reg = <0x00 0x4104000 0x00 0x100>;
|
||||
dma-coherent;
|
||||
|
|
@ -895,7 +1148,7 @@ usb0: usb@6000000 {
|
|||
};
|
||||
};
|
||||
|
||||
usbss1: cdns_usb@4114000 {
|
||||
usbss1: cdns-usb@4114000 {
|
||||
compatible = "ti,j721e-usb";
|
||||
reg = <0x00 0x4114000 0x00 0x100>;
|
||||
dma-coherent;
|
||||
|
|
@ -1326,4 +1579,42 @@ watchdog1: watchdog@2210000 {
|
|||
assigned-clocks = <&k3_clks 253 1>;
|
||||
assigned-clock-parents = <&k3_clks 253 5>;
|
||||
};
|
||||
|
||||
c66_0: dsp@4d80800000 {
|
||||
compatible = "ti,j721e-c66-dsp";
|
||||
reg = <0x4d 0x80800000 0x00 0x00048000>,
|
||||
<0x4d 0x80e00000 0x00 0x00008000>,
|
||||
<0x4d 0x80f00000 0x00 0x00008000>;
|
||||
reg-names = "l2sram", "l1pram", "l1dram";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <142>;
|
||||
ti,sci-proc-ids = <0x03 0xff>;
|
||||
resets = <&k3_reset 142 1>;
|
||||
firmware-name = "j7-c66_0-fw";
|
||||
};
|
||||
|
||||
c66_1: dsp@4d81800000 {
|
||||
compatible = "ti,j721e-c66-dsp";
|
||||
reg = <0x4d 0x81800000 0x00 0x00048000>,
|
||||
<0x4d 0x81e00000 0x00 0x00008000>,
|
||||
<0x4d 0x81f00000 0x00 0x00008000>;
|
||||
reg-names = "l2sram", "l1pram", "l1dram";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <143>;
|
||||
ti,sci-proc-ids = <0x04 0xff>;
|
||||
resets = <&k3_reset 143 1>;
|
||||
firmware-name = "j7-c66_1-fw";
|
||||
};
|
||||
|
||||
c71_0: dsp@64800000 {
|
||||
compatible = "ti,j721e-c71-dsp";
|
||||
reg = <0x00 0x64800000 0x00 0x00080000>,
|
||||
<0x00 0x64e00000 0x00 0x0000c000>;
|
||||
reg-names = "l2sram", "l1dram";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <15>;
|
||||
ti,sci-proc-ids = <0x30 0xff>;
|
||||
resets = <&k3_reset 15 1>;
|
||||
firmware-name = "j7-c71_0-fw";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ chipid@43000014 {
|
|||
reg = <0x0 0x43000014 0x0 0x4>;
|
||||
};
|
||||
|
||||
wkup_pmx0: pinmux@4301c000 {
|
||||
wkup_pmx0: pinctrl@4301c000 {
|
||||
compatible = "pinctrl-single";
|
||||
/* Proxy 0 addressing */
|
||||
reg = <0x00 0x4301c000 0x00 0x178>;
|
||||
|
|
@ -249,7 +249,7 @@ adc {
|
|||
};
|
||||
};
|
||||
|
||||
mcu_navss {
|
||||
mcu-navss {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
|
|
|||
|
|
@ -25,11 +25,53 @@ secure_ddr: optee@9e800000 {
|
|||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c66_1_dma_memory_region: c66-dma-memory@a6000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c66_0_memory_region: c66-memory@a6100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c66_0_dma_memory_region: c66-dma-memory@a7000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c66_1_memory_region: c66-memory@a7100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_dma_memory_region: c71-dma-memory@a8000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa8000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_memory_region: c71-memory@a8100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa8100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@aa000000 {
|
||||
reg = <0x00 0xaa000000 0x00 0x01c00000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_pmx0 {
|
||||
wkup_i2c0_pins_default: wkup_i2c0_pins_default {
|
||||
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
|
||||
J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
|
||||
|
|
@ -72,3 +114,114 @@ flash@0{
|
|||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
interrupts = <428>;
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
interrupts = <424>;
|
||||
|
||||
mbox_c66_0: mbox-c66-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_c66_1: mbox-c66-1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
interrupts = <420>;
|
||||
|
||||
mbox_c71_0: mbox-c71-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster7 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster8 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster9 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster10 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster11 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&c66_0 {
|
||||
mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
|
||||
memory-region = <&c66_0_dma_memory_region>,
|
||||
<&c66_0_memory_region>;
|
||||
};
|
||||
|
||||
&c66_1 {
|
||||
mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
|
||||
memory-region = <&c66_1_dma_memory_region>,
|
||||
<&c66_1_memory_region>;
|
||||
};
|
||||
|
||||
&c71_0 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
|
||||
memory-region = <&c71_0_dma_memory_region>,
|
||||
<&c71_0_memory_region>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -120,21 +120,24 @@ pmu: pmu {
|
|||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
cbass_main: interconnect@100000 {
|
||||
cbass_main: bus@100000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
|
||||
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
|
||||
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
|
||||
<0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
|
||||
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
|
||||
<0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
|
||||
<0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
|
||||
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
|
||||
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
|
||||
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/
|
||||
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/
|
||||
<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
|
||||
<0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
|
||||
<0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */
|
||||
<0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */
|
||||
<0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
|
||||
<0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */
|
||||
<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
|
||||
|
|
@ -155,7 +158,7 @@ cbass_main: interconnect@100000 {
|
|||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
|
||||
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
|
||||
|
||||
cbass_mcu_wakeup: interconnect@28380000 {
|
||||
cbass_mcu_wakeup: bus@28380000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
|
|
|||
Loading…
Reference in a new issue