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drm/amd/pp: Implement voltage regulator config on CI
Store the voltage regulator configuration so we can properly query the voltage Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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59655cb6ab
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53241e01b9
3 changed files with 58 additions and 1 deletions
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@ -82,6 +82,25 @@
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#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
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#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
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/* Voltage Regulator Configuration */
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/* VR Config info is contained in dpmTable */
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#define VRCONF_VDDC_MASK 0x000000FF
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#define VRCONF_VDDC_SHIFT 0
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#define VRCONF_VDDGFX_MASK 0x0000FF00
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#define VRCONF_VDDGFX_SHIFT 8
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#define VRCONF_VDDCI_MASK 0x00FF0000
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#define VRCONF_VDDCI_SHIFT 16
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#define VRCONF_MVDD_MASK 0xFF000000
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#define VRCONF_MVDD_SHIFT 24
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#define VR_MERGED_WITH_VDDC 0
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#define VR_SVI2_PLANE_1 1
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#define VR_SVI2_PLANE_2 2
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#define VR_SMIO_PATTERN_1 3
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#define VR_SMIO_PATTERN_2 4
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#define VR_STATIC_VOLTAGE 5
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struct SMU7_PIDController
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struct SMU7_PIDController
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{
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{
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uint32_t Ki;
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uint32_t Ki;
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@ -316,7 +316,8 @@ struct SMU7_Discrete_DpmTable
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uint8_t AcpLevelCount;
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uint8_t AcpLevelCount;
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uint8_t SamuLevelCount;
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uint8_t SamuLevelCount;
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uint8_t MasterDeepSleepControl;
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uint8_t MasterDeepSleepControl;
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uint32_t Reserved[5];
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uint32_t VRConfig;
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uint32_t Reserved[4];
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// uint32_t SamuDefaultLevel;
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// uint32_t SamuDefaultLevel;
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SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS];
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SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS];
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@ -1941,6 +1941,37 @@ static int ci_start_smc(struct pp_hwmgr *hwmgr)
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return 0;
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return 0;
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}
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}
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static int ci_populate_vr_config(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table)
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{
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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uint16_t config;
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config = VR_SVI2_PLANE_1;
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table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
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if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
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config = VR_SVI2_PLANE_2;
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table->VRConfig |= config;
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} else {
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pr_info("VDDCshould be on SVI2 controller!");
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}
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if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
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config = VR_SVI2_PLANE_2;
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table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
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} else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
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config = VR_SMIO_PATTERN_1;
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table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
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}
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if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
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config = VR_SMIO_PATTERN_2;
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table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);
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}
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return 0;
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}
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static int ci_init_smc_table(struct pp_hwmgr *hwmgr)
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static int ci_init_smc_table(struct pp_hwmgr *hwmgr)
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{
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{
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int result;
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int result;
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@ -2064,6 +2095,11 @@ static int ci_init_smc_table(struct pp_hwmgr *hwmgr)
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table->PCIeBootLinkLevel = (uint8_t)data->dpm_table.pcie_speed_table.count;
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table->PCIeBootLinkLevel = (uint8_t)data->dpm_table.pcie_speed_table.count;
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table->PCIeGenInterval = 1;
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table->PCIeGenInterval = 1;
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result = ci_populate_vr_config(hwmgr, table);
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PP_ASSERT_WITH_CODE(0 == result,
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"Failed to populate VRConfig setting!", return result);
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data->vr_config = table->VRConfig;
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ci_populate_smc_svi2_config(hwmgr, table);
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ci_populate_smc_svi2_config(hwmgr, table);
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for (i = 0; i < SMU7_MAX_ENTRIES_SMIO; i++)
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for (i = 0; i < SMU7_MAX_ENTRIES_SMIO; i++)
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@ -2084,6 +2120,7 @@ static int ci_init_smc_table(struct pp_hwmgr *hwmgr)
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table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
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table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
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CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
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CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
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CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
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CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid);
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CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid);
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CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase);
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CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase);
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CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid);
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CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid);
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