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dmaengine: at_xdmac: fix residue corruption
An unexpected value of CUBC can lead to a corrupted residue. A more
complex sequence is needed to detect an inaccurate value for NCA or CUBC.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Fixes: e1f7c9eee7
("dmaengine: at_xdmac: creation of the atmel
eXtended DMA Controller driver")
Cc: stable@vger.kernel.org #v4.1 and later
Reviewed-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
parent
4a9723e8df
commit
53398f4888
1 changed files with 32 additions and 22 deletions
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@ -1400,6 +1400,7 @@ at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
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u32 cur_nda, check_nda, cur_ubc, mask, value;
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u8 dwidth = 0;
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unsigned long flags;
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bool initd;
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ret = dma_cookie_status(chan, cookie, txstate);
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if (ret == DMA_COMPLETE)
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@ -1435,34 +1436,43 @@ at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
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}
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/*
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* When processing the residue, we need to read two registers but we
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* can't do it in an atomic way. AT_XDMAC_CNDA is used to find where
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* we stand in the descriptor list and AT_XDMAC_CUBC is used
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* to know how many data are remaining for the current descriptor.
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* Since the dma channel is not paused to not loose data, between the
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* AT_XDMAC_CNDA and AT_XDMAC_CUBC read, we may have change of
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* descriptor.
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* For that reason, after reading AT_XDMAC_CUBC, we check if we are
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* still using the same descriptor by reading a second time
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* AT_XDMAC_CNDA. If AT_XDMAC_CNDA has changed, it means we have to
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* read again AT_XDMAC_CUBC.
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* The easiest way to compute the residue should be to pause the DMA
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* but doing this can lead to miss some data as some devices don't
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* have FIFO.
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* We need to read several registers because:
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* - DMA is running therefore a descriptor change is possible while
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* reading these registers
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* - When the block transfer is done, the value of the CUBC register
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* is set to its initial value until the fetch of the next descriptor.
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* This value will corrupt the residue calculation so we have to skip
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* it.
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*
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* INITD -------- ------------
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* |____________________|
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* _______________________ _______________
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* NDA @desc2 \/ @desc3
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* _______________________/\_______________
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* __________ ___________ _______________
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* CUBC 0 \/ MAX desc1 \/ MAX desc2
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* __________/\___________/\_______________
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*
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* Since descriptors are aligned on 64 bits, we can assume that
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* the update of NDA and CUBC is atomic.
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* Memory barriers are used to ensure the read order of the registers.
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* A max number of retries is set because unlikely it can never ends if
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* we are transferring a lot of data with small buffers.
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* A max number of retries is set because unlikely it could never ends.
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*/
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cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
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rmb();
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cur_ubc = at_xdmac_chan_read(atchan, AT_XDMAC_CUBC);
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for (retry = 0; retry < AT_XDMAC_RESIDUE_MAX_RETRIES; retry++) {
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rmb();
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check_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
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if (likely(cur_nda == check_nda))
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break;
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cur_nda = check_nda;
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rmb();
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initd = !!(at_xdmac_chan_read(atchan, AT_XDMAC_CC) & AT_XDMAC_CC_INITD);
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rmb();
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cur_ubc = at_xdmac_chan_read(atchan, AT_XDMAC_CUBC);
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rmb();
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cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
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rmb();
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if ((check_nda == cur_nda) && initd)
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break;
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}
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if (unlikely(retry >= AT_XDMAC_RESIDUE_MAX_RETRIES)) {
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