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crypto: ccree - adapt CPP descriptor to new HW
Adapt the CPP descriptor to new HW interface. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
parent
bee711fa35
commit
533edf9f93
3 changed files with 29 additions and 37 deletions
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@ -546,6 +546,19 @@ static void cc_setup_state_desc(struct crypto_tfm *tfm,
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}
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}
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static int cc_out_flow_mode(struct cc_cipher_ctx *ctx_p)
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{
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switch (ctx_p->flow_mode) {
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case S_DIN_to_AES:
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return DIN_AES_DOUT;
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case S_DIN_to_DES:
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return DIN_DES_DOUT;
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case S_DIN_to_SM4:
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return DIN_SM4_DOUT;
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default:
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return ctx_p->flow_mode;
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}
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}
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static void cc_setup_key_desc(struct crypto_tfm *tfm,
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struct cipher_req_ctx *req_ctx,
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@ -577,12 +590,15 @@ static void cc_setup_key_desc(struct crypto_tfm *tfm,
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case DRV_CIPHER_ECB:
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/* Load key */
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hw_desc_init(&desc[*seq_size]);
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set_cipher_mode(&desc[*seq_size], cipher_mode);
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set_cipher_config0(&desc[*seq_size], direction);
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if (cc_key_type(tfm) == CC_POLICY_PROTECTED_KEY) {
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set_cpp_crypto_key(&desc[*seq_size], ctx_p->cpp.alg,
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cipher_mode, ctx_p->cpp.slot);
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/* We use the AES key size coding for all CPP algs */
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set_key_size_aes(&desc[*seq_size], key_len);
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set_cpp_crypto_key(&desc[*seq_size], ctx_p->cpp.slot);
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flow_mode = cc_out_flow_mode(ctx_p);
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} else {
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set_cipher_mode(&desc[*seq_size], cipher_mode);
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set_cipher_config0(&desc[*seq_size], direction);
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if (flow_mode == S_DIN_to_AES) {
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if (cc_key_type(tfm) == CC_HW_PROTECTED_KEY) {
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set_hw_crypto_key(&desc[*seq_size],
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@ -606,9 +622,9 @@ static void cc_setup_key_desc(struct crypto_tfm *tfm,
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key_dma_addr, key_len, NS_BIT);
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set_key_size_des(&desc[*seq_size], key_len);
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}
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set_flow_mode(&desc[*seq_size], flow_mode);
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set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0);
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}
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set_flow_mode(&desc[*seq_size], flow_mode);
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(*seq_size)++;
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break;
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case DRV_CIPHER_XTS:
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@ -670,22 +686,8 @@ static void cc_setup_flow_desc(struct crypto_tfm *tfm,
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{
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struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
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struct device *dev = drvdata_to_dev(ctx_p->drvdata);
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unsigned int flow_mode = ctx_p->flow_mode;
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unsigned int flow_mode = cc_out_flow_mode(ctx_p);
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switch (ctx_p->flow_mode) {
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case S_DIN_to_AES:
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flow_mode = DIN_AES_DOUT;
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break;
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case S_DIN_to_DES:
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flow_mode = DIN_DES_DOUT;
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break;
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case S_DIN_to_SM4:
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flow_mode = DIN_SM4_DOUT;
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break;
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default:
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dev_err(dev, "invalid flow mode, flow_mode = %d\n", flow_mode);
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return;
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}
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/* Process */
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if (req_ctx->dma_buf_type == CC_DMA_BUF_DLLI) {
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dev_dbg(dev, " data params addr %pad length 0x%X\n",
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@ -55,8 +55,6 @@
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#define WORD4_DATA_FLOW_MODE CC_GENMASK(4, DATA_FLOW_MODE)
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#define WORD4_KEY_SIZE CC_GENMASK(4, KEY_SIZE)
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#define WORD4_SETUP_OPERATION CC_GENMASK(4, SETUP_OPERATION)
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#define WORD4_CPP_ALG CC_GENMASK(4, CPP_ALG)
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#define WORD4_CPP_SLOT CC_GENMASK(4, CPP_SLOT)
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#define WORD5_DIN_ADDR_HIGH CC_GENMASK(5, DIN_ADDR_HIGH)
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#define WORD5_DOUT_ADDR_HIGH CC_GENMASK(5, DOUT_ADDR_HIGH)
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@ -202,7 +200,8 @@ enum cc_hash_cipher_pad {
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HASH_CIPHER_DO_PADDING_RESERVE32 = S32_MAX,
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};
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#define CC_CPP_DESC_INDICATOR 0xFF0000UL
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#define CC_CPP_DIN_ADDR 0xFF00FF00UL
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#define CC_CPP_DIN_SIZE 0xFF00FFUL
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/*****************************/
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/* Descriptor packing macros */
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@ -272,17 +271,14 @@ static inline void set_din_no_dma(struct cc_hw_desc *pdesc, u32 addr, u32 size)
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* @slot: slot number
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* @ksize: key size
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*/
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static inline void set_cpp_crypto_key(struct cc_hw_desc *pdesc,
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enum cc_cpp_alg alg,
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enum drv_cipher_mode mode, u8 slot)
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static inline void set_cpp_crypto_key(struct cc_hw_desc *pdesc, u8 slot)
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{
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u8 mode_val = (mode == DRV_CIPHER_CBC ? 0 : 1);
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pdesc->word[0] |= CC_CPP_DIN_ADDR;
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pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, CC_CPP_DESC_INDICATOR);
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pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, CC_CPP_DIN_SIZE);
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pdesc->word[1] |= FIELD_PREP(WORD1_LOCK_QUEUE, 1);
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pdesc->word[0] |= FIELD_PREP(WORD0_CPP_CIPHER_MODE, mode_val);
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pdesc->word[4] |= FIELD_PREP(WORD4_CPP_ALG, alg);
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pdesc->word[4] |= FIELD_PREP(WORD4_CPP_SLOT, slot);
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pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, slot);
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}
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/*
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@ -31,8 +31,6 @@
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#define CC_DSCRPTR_QUEUE_WORD0_REG_OFFSET 0xE80UL
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#define CC_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SHIFT 0x0UL
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#define CC_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SIZE 0x20UL
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#define CC_DSCRPTR_QUEUE_WORD0_CPP_CIPHER_MODE_BIT_SHIFT 0x5UL
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#define CC_DSCRPTR_QUEUE_WORD0_CPP_CIPHER_MODE_BIT_SIZE 0x3UL
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#define CC_DSCRPTR_QUEUE_WORD1_REG_OFFSET 0xE84UL
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#define CC_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SHIFT 0x0UL
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#define CC_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SIZE 0x2UL
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@ -99,10 +97,6 @@
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#define CC_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SHIFT 0x1FUL
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#define CC_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD4_CPP_SLOT_BIT_SHIFT 0xAUL
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#define CC_DSCRPTR_QUEUE_WORD4_CPP_SLOT_BIT_SIZE 0x3UL
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#define CC_DSCRPTR_QUEUE_WORD4_CPP_ALG_BIT_SHIFT 0xDUL
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#define CC_DSCRPTR_QUEUE_WORD4_CPP_ALG_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD5_REG_OFFSET 0xE94UL
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#define CC_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SHIFT 0x0UL
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#define CC_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SIZE 0x10UL
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