mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-13 14:14:37 +00:00
Merge branch 'omap-clock-fixes' into omap-fixes
This commit is contained in:
commit
535ff672e3
10 changed files with 112 additions and 34 deletions
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@ -40,8 +40,8 @@ static void omap1_mcbsp_request(unsigned int id)
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*/
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*/
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if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
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if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
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if (dsp_use++ == 0) {
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if (dsp_use++ == 0) {
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api_clk = clk_get(NULL, "api_clk");
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api_clk = clk_get(NULL, "api_ck");
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dsp_clk = clk_get(NULL, "dsp_clk");
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dsp_clk = clk_get(NULL, "dsp_ck");
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if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) {
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if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) {
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clk_enable(api_clk);
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clk_enable(api_clk);
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clk_enable(dsp_clk);
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clk_enable(dsp_clk);
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@ -42,6 +42,7 @@
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#include <mach/nand.h>
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#include <mach/nand.h>
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#include <mach/mux.h>
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#include <mach/mux.h>
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#include <mach/usb.h>
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#include <mach/usb.h>
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#include <mach/timer-gp.h>
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#include "mmc-twl4030.h"
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#include "mmc-twl4030.h"
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@ -186,6 +187,9 @@ static void __init omap3_beagle_init_irq(void)
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{
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{
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omap2_init_common_hw(NULL);
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omap2_init_common_hw(NULL);
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omap_init_irq();
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omap_init_irq();
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#ifdef CONFIG_OMAP_32K_TIMER
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omap2_gp_clockevent_set_gptimer(12);
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#endif
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omap_gpio_init();
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omap_gpio_init();
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}
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}
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@ -60,12 +60,13 @@ struct omap_clk {
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}, \
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}, \
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}
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}
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#define CK_243X (1 << 0)
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#define CK_243X RATE_IN_243X
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#define CK_242X (1 << 1)
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#define CK_242X RATE_IN_242X
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static struct omap_clk omap24xx_clks[] = {
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static struct omap_clk omap24xx_clks[] = {
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/* external root sources */
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/* external root sources */
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CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X),
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CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X),
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CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X),
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CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X),
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CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X),
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CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X),
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CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X),
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CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X),
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CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X),
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@ -711,7 +712,7 @@ int __init omap2_clk_init(void)
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{
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{
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struct prcm_config *prcm;
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struct prcm_config *prcm;
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struct omap_clk *c;
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struct omap_clk *c;
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u32 clkrate, cpu_mask;
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u32 clkrate;
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if (cpu_is_omap242x())
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if (cpu_is_omap242x())
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cpu_mask = RATE_IN_242X;
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cpu_mask = RATE_IN_242X;
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@ -720,20 +721,14 @@ int __init omap2_clk_init(void)
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clk_init(&omap2_clk_functions);
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clk_init(&omap2_clk_functions);
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for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
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clk_init_one(c->lk.clk);
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osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
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osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
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propagate_rate(&osc_ck);
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propagate_rate(&osc_ck);
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sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
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sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
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propagate_rate(&sys_ck);
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propagate_rate(&sys_ck);
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for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
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clk_init_one(c->lk.clk);
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cpu_mask = 0;
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if (cpu_is_omap2420())
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cpu_mask |= CK_242X;
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if (cpu_is_omap2430())
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cpu_mask |= CK_243X;
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for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
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for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
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if (c->cpu & cpu_mask) {
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if (c->cpu & cpu_mask) {
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clkdev_add(&c->lk);
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clkdev_add(&c->lk);
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@ -625,6 +625,14 @@ static struct clk func_32k_ck = {
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.clkdm_name = "wkup_clkdm",
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.clkdm_name = "wkup_clkdm",
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};
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};
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static struct clk secure_32k_ck = {
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.name = "secure_32k_ck",
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.ops = &clkops_null,
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.rate = 32768,
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.flags = RATE_FIXED,
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.clkdm_name = "wkup_clkdm",
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};
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/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
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/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
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static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
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static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
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.name = "osc_ck",
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.name = "osc_ck",
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@ -1790,7 +1798,7 @@ static struct clk gpt12_ick = {
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static struct clk gpt12_fck = {
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static struct clk gpt12_fck = {
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.name = "gpt12_fck",
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.name = "gpt12_fck",
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.ops = &clkops_omap2_dflt_wait,
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.ops = &clkops_omap2_dflt_wait,
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.parent = &func_32k_ck,
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.parent = &secure_32k_ck,
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.clkdm_name = "core_l4_clkdm",
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.clkdm_name = "core_l4_clkdm",
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.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
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.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
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.enable_bit = OMAP24XX_EN_GPT12_SHIFT,
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.enable_bit = OMAP24XX_EN_GPT12_SHIFT,
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@ -2052,7 +2052,7 @@ static struct clk dss_ick = {
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static struct clk cam_mclk = {
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static struct clk cam_mclk = {
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.name = "cam_mclk",
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.name = "cam_mclk",
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.ops = &clkops_omap2_dflt_wait,
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.ops = &clkops_omap2_dflt,
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.parent = &dpll4_m5x2_ck,
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.parent = &dpll4_m5x2_ck,
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.enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
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.enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
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.enable_bit = OMAP3430_EN_CAM_SHIFT,
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.enable_bit = OMAP3430_EN_CAM_SHIFT,
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@ -2063,7 +2063,7 @@ static struct clk cam_mclk = {
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static struct clk cam_ick = {
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static struct clk cam_ick = {
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/* Handles both L3 and L4 clocks */
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/* Handles both L3 and L4 clocks */
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.name = "cam_ick",
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.name = "cam_ick",
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.ops = &clkops_omap2_dflt_wait,
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.ops = &clkops_omap2_dflt,
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.parent = &l4_ick,
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.parent = &l4_ick,
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.init = &omap2_init_clk_clkdm,
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.init = &omap2_init_clk_clkdm,
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.enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
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.enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
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@ -2074,7 +2074,7 @@ static struct clk cam_ick = {
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static struct clk csi2_96m_fck = {
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static struct clk csi2_96m_fck = {
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.name = "csi2_96m_fck",
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.name = "csi2_96m_fck",
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.ops = &clkops_omap2_dflt_wait,
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.ops = &clkops_omap2_dflt,
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.parent = &core_96m_fck,
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.parent = &core_96m_fck,
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.init = &omap2_init_clk_clkdm,
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.init = &omap2_init_clk_clkdm,
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.enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
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.enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
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@ -2901,7 +2901,6 @@ static struct clk sr_l4_ick = {
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/* SECURE_32K_FCK clocks */
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/* SECURE_32K_FCK clocks */
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/* XXX This clock no longer exists in 3430 TRM rev F */
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static struct clk gpt12_fck = {
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static struct clk gpt12_fck = {
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.name = "gpt12_fck",
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.name = "gpt12_fck",
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.ops = &clkops_null,
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.ops = &clkops_null,
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@ -3,6 +3,8 @@
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*
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*
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* OMAP2 GP timer support.
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* OMAP2 GP timer support.
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*
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*
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* Copyright (C) 2009 Nokia Corporation
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*
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* Update to use new clocksource/clockevent layers
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* Update to use new clocksource/clockevent layers
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* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
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* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Copyright (C) 2007 MontaVista Software, Inc.
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@ -36,8 +38,13 @@
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#include <asm/mach/time.h>
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#include <asm/mach/time.h>
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#include <mach/dmtimer.h>
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#include <mach/dmtimer.h>
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/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
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#define MAX_GPTIMER_ID 12
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static struct omap_dm_timer *gptimer;
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static struct omap_dm_timer *gptimer;
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static struct clock_event_device clockevent_gpt;
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static struct clock_event_device clockevent_gpt;
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static u8 __initdata gptimer_id = 1;
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static u8 __initdata inited;
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static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
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static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
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{
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{
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@ -95,20 +102,53 @@ static struct clock_event_device clockevent_gpt = {
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.set_mode = omap2_gp_timer_set_mode,
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.set_mode = omap2_gp_timer_set_mode,
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};
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};
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/**
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* omap2_gp_clockevent_set_gptimer - set which GPTIMER is used for clockevents
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* @id: GPTIMER to use (1..MAX_GPTIMER_ID)
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*
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* Define the GPTIMER that the system should use for the tick timer.
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* Meant to be called from board-*.c files in the event that GPTIMER1, the
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* default, is unsuitable. Returns -EINVAL on error or 0 on success.
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*/
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int __init omap2_gp_clockevent_set_gptimer(u8 id)
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{
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if (id < 1 || id > MAX_GPTIMER_ID)
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return -EINVAL;
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BUG_ON(inited);
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gptimer_id = id;
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return 0;
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}
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static void __init omap2_gp_clockevent_init(void)
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static void __init omap2_gp_clockevent_init(void)
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{
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{
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u32 tick_rate;
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u32 tick_rate;
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int src;
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gptimer = omap_dm_timer_request_specific(1);
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inited = 1;
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gptimer = omap_dm_timer_request_specific(gptimer_id);
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BUG_ON(gptimer == NULL);
|
BUG_ON(gptimer == NULL);
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|
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#if defined(CONFIG_OMAP_32K_TIMER)
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#if defined(CONFIG_OMAP_32K_TIMER)
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omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
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src = OMAP_TIMER_SRC_32_KHZ;
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#else
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#else
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omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK);
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src = OMAP_TIMER_SRC_SYS_CLK;
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WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the "
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"secure 32KiHz clock source\n");
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#endif
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#endif
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if (gptimer_id != 12)
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WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)),
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"timer-gp: omap_dm_timer_set_source() failed\n");
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tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
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tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
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|
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pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
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gptimer_id, tick_rate);
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omap2_gp_timer_irq.dev_id = (void *)gptimer;
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omap2_gp_timer_irq.dev_id = (void *)gptimer;
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setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
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setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
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omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
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omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
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@ -125,6 +165,8 @@ static void __init omap2_gp_clockevent_init(void)
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clockevents_register_device(&clockevent_gpt);
|
clockevents_register_device(&clockevent_gpt);
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}
|
}
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|
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|
/* Clocksource code */
|
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|
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#ifdef CONFIG_OMAP_32K_TIMER
|
#ifdef CONFIG_OMAP_32K_TIMER
|
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/*
|
/*
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* When 32k-timer is enabled, don't use GPTimer for clocksource
|
* When 32k-timer is enabled, don't use GPTimer for clocksource
|
||||||
|
|
|
@ -239,6 +239,13 @@ void recalculate_root_clocks(void)
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}
|
}
|
||||||
}
|
}
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||||||
|
|
||||||
|
/**
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||||||
|
* clk_init_one - initialize any fields in the struct clk before clk init
|
||||||
|
* @clk: struct clk * to initialize
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|
*
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|
* Initialize any struct clk fields needed before normal clk initialization
|
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|
* can run. No return value.
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|
*/
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void clk_init_one(struct clk *clk)
|
void clk_init_one(struct clk *clk)
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{
|
{
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INIT_LIST_HEAD(&clk->children);
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INIT_LIST_HEAD(&clk->children);
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|
|
|
@ -238,7 +238,7 @@ static struct omap_dm_timer omap3_dm_timers[] = {
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{ .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 },
|
{ .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 },
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||||||
{ .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
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{ .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
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||||||
{ .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
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{ .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
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||||||
{ .phys_base = 0x48304000, .irq = INT_24XX_GPTIMER12 },
|
{ .phys_base = 0x48304000, .irq = INT_34XX_GPT12_IRQ },
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||||||
};
|
};
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||||||
|
|
||||||
static const char *omap3_dm_source_names[] __initdata = {
|
static const char *omap3_dm_source_names[] __initdata = {
|
||||||
|
@ -321,11 +321,9 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
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l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
|
l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
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|
|
||||||
/*
|
/*
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||||||
* Enable wake-up only for GPT1 on OMAP2 CPUs.
|
* Enable wake-up on OMAP2 CPUs.
|
||||||
* FIXME: All timers should have wake-up enabled and clear
|
|
||||||
* PRCM status.
|
|
||||||
*/
|
*/
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||||||
if (cpu_class_is_omap2() && (timer == &dm_timers[0]))
|
if (cpu_class_is_omap2())
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l |= 1 << 2;
|
l |= 1 << 2;
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omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
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||||||
|
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||||||
|
@ -511,7 +509,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_OMAP1
|
#ifdef CONFIG_ARCH_OMAP1
|
||||||
|
|
||||||
void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
|
int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
|
||||||
{
|
{
|
||||||
int n = (timer - dm_timers) << 1;
|
int n = (timer - dm_timers) << 1;
|
||||||
u32 l;
|
u32 l;
|
||||||
|
@ -519,23 +517,31 @@ void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
|
||||||
l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
|
l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
|
||||||
l |= source << n;
|
l |= source << n;
|
||||||
omap_writel(l, MOD_CONF_CTRL_1);
|
omap_writel(l, MOD_CONF_CTRL_1);
|
||||||
|
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
|
EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
|
||||||
|
|
||||||
#else
|
#else
|
||||||
|
|
||||||
void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
|
int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
|
||||||
{
|
{
|
||||||
|
int ret = -EINVAL;
|
||||||
|
|
||||||
if (source < 0 || source >= 3)
|
if (source < 0 || source >= 3)
|
||||||
return;
|
return -EINVAL;
|
||||||
|
|
||||||
clk_disable(timer->fclk);
|
clk_disable(timer->fclk);
|
||||||
clk_set_parent(timer->fclk, dm_source_clocks[source]);
|
ret = clk_set_parent(timer->fclk, dm_source_clocks[source]);
|
||||||
clk_enable(timer->fclk);
|
clk_enable(timer->fclk);
|
||||||
|
|
||||||
/* When the functional clock disappears, too quick writes seem to
|
/*
|
||||||
* cause an abort. */
|
* When the functional clock disappears, too quick writes seem
|
||||||
|
* to cause an abort. XXX Is this still necessary?
|
||||||
|
*/
|
||||||
__delay(150000);
|
__delay(150000);
|
||||||
|
|
||||||
|
return ret;
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
|
EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
|
||||||
|
|
||||||
|
|
|
@ -64,7 +64,7 @@ void omap_dm_timer_trigger(struct omap_dm_timer *timer);
|
||||||
void omap_dm_timer_start(struct omap_dm_timer *timer);
|
void omap_dm_timer_start(struct omap_dm_timer *timer);
|
||||||
void omap_dm_timer_stop(struct omap_dm_timer *timer);
|
void omap_dm_timer_stop(struct omap_dm_timer *timer);
|
||||||
|
|
||||||
void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
|
int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
|
||||||
void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
|
void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
|
||||||
void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
|
void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
|
||||||
void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
|
void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
|
||||||
|
|
17
arch/arm/plat-omap/include/mach/timer-gp.h
Normal file
17
arch/arm/plat-omap/include/mach/timer-gp.h
Normal file
|
@ -0,0 +1,17 @@
|
||||||
|
/*
|
||||||
|
* OMAP2/3 GPTIMER support.headers
|
||||||
|
*
|
||||||
|
* Copyright (C) 2009 Nokia Corporation
|
||||||
|
*
|
||||||
|
* This file is subject to the terms and conditions of the GNU General Public
|
||||||
|
* License. See the file "COPYING" in the main directory of this archive
|
||||||
|
* for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
|
||||||
|
#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
|
||||||
|
|
||||||
|
int __init omap2_gp_clockevent_set_gptimer(u8 id);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
Loading…
Reference in a new issue