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clk: imx: Remove unused helpers
Remove all the helpers that are not referenced anywhere anymore. Most of them are not clk_hw based. The rest are passing the device as an argument and were intented for BLK_CTL driver usage, but that is not the case anymore since the BLK_CTL is (or will be) implemented outside of CCF. - imx_clk_divider2 - imx_clk_gate2_shared2 - imx_clk_gate3 - imx_clk_gate4 - imx_clk_frac_pll - imx_clk_sscg_pll - imx_clk_pll14xx - imx_clk_pll14xx - imx_clk_divider2_flags - imx_dev_clk_hw_gate - imx_dev_clk_hw_gate_shared - imx_clk_gate3_flags - imx_clk_gate4_flags - imx_dev_clk_hw_mux - imx_clk_mux2 - imx_dev_clk_hw_mux_flags - imx8m_clk_composite_flags - __imx8m_clk_composite - imx8m_clk_composite - imx8m_clk_composite_critical Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-2-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Abel Vesa
parent
6880fa6c56
commit
536559af6a
1 changed files with 0 additions and 103 deletions
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@ -88,9 +88,6 @@ extern struct imx_pll14xx_clk imx_1443x_dram_pll;
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#define imx_clk_divider(name, parent, reg, shift, width) \
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to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
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#define imx_clk_divider2(name, parent, reg, shift, width) \
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to_clk(imx_clk_hw_divider2(name, parent, reg, shift, width))
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#define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \
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to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
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@ -106,15 +103,6 @@ extern struct imx_pll14xx_clk imx_1443x_dram_pll;
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#define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
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to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
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#define imx_clk_gate2_shared2(name, parent, reg, shift, share_count) \
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to_clk(imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count))
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#define imx_clk_gate3(name, parent, reg, shift) \
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to_clk(imx_clk_hw_gate3(name, parent, reg, shift))
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#define imx_clk_gate4(name, parent, reg, shift) \
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to_clk(imx_clk_hw_gate4(name, parent, reg, shift))
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#define imx_clk_mux(name, reg, shift, width, parents, num_parents) \
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to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
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@ -124,20 +112,6 @@ extern struct imx_pll14xx_clk imx_1443x_dram_pll;
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#define imx_clk_pllv2(name, parent, base) \
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to_clk(imx_clk_hw_pllv2(name, parent, base))
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#define imx_clk_frac_pll(name, parent_name, base) \
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to_clk(imx_clk_hw_frac_pll(name, parent_name, base))
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#define imx_clk_sscg_pll(name, parent_names, num_parents, parent,\
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bypass1, bypass2, base, flags) \
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to_clk(imx_clk_hw_sscg_pll(name, parent_names, num_parents, parent,\
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bypass1, bypass2, base, flags))
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struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
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void __iomem *base, const struct imx_pll14xx_clk *pll_clk);
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#define imx_clk_pll14xx(name, parent_name, base, pll_clk) \
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to_clk(imx_clk_hw_pll14xx(name, parent_name, base, pll_clk))
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struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
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const char *parent_name, void __iomem *base,
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const struct imx_pll14xx_clk *pll_clk);
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@ -301,15 +275,6 @@ static inline struct clk_hw *imx_clk_hw_divider2(const char *name, const char *p
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_divider2_flags(const char *name,
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const char *parent, void __iomem *reg, u8 shift, u8 width,
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unsigned long flags)
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{
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return clk_register_divider(NULL, name, parent,
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flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk_hw *imx_clk_hw_gate_flags(const char *name, const char *parent,
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void __iomem *reg, u8 shift, unsigned long flags)
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{
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@ -324,13 +289,6 @@ static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char *paren
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shift, 0, &imx_ccm_lock);
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}
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static inline struct clk_hw *imx_dev_clk_hw_gate(struct device *dev, const char *name,
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const char *parent, void __iomem *reg, u8 shift)
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{
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return clk_hw_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, 0, &imx_ccm_lock);
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}
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static inline struct clk_hw *imx_clk_hw_gate_dis(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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@ -376,16 +334,6 @@ static inline struct clk_hw *imx_clk_hw_gate2_shared2(const char *name,
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&imx_ccm_lock, share_count);
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}
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static inline struct clk_hw *imx_dev_clk_hw_gate_shared(struct device *dev,
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const char *name, const char *parent,
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void __iomem *reg, u8 shift,
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unsigned int *share_count)
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{
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return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
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CLK_OPS_PARENT_ENABLE, reg, shift, 0x1,
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0x1, 0, &imx_ccm_lock, share_count);
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}
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static inline struct clk *imx_clk_gate2_cgr(const char *name,
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const char *parent, void __iomem *reg, u8 shift, u8 cgr_val)
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{
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@ -410,9 +358,6 @@ static inline struct clk_hw *imx_clk_hw_gate3_flags(const char *name,
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reg, shift, 0, &imx_ccm_lock);
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}
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#define imx_clk_gate3_flags(name, parent, reg, shift, flags) \
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to_clk(imx_clk_hw_gate3_flags(name, parent, reg, shift, flags))
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static inline struct clk_hw *imx_clk_hw_gate4(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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@ -430,9 +375,6 @@ static inline struct clk_hw *imx_clk_hw_gate4_flags(const char *name,
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reg, shift, 0x3, 0x3, 0, &imx_ccm_lock, NULL);
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}
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#define imx_clk_gate4_flags(name, parent, reg, shift, flags) \
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to_clk(imx_clk_hw_gate4_flags(name, parent, reg, shift, flags))
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static inline struct clk_hw *imx_clk_hw_mux(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char * const *parents,
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int num_parents)
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@ -442,24 +384,6 @@ static inline struct clk_hw *imx_clk_hw_mux(const char *name, void __iomem *reg,
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width, 0, &imx_ccm_lock);
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}
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static inline struct clk_hw *imx_dev_clk_hw_mux(struct device *dev,
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const char *name, void __iomem *reg, u8 shift,
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u8 width, const char * const *parents, int num_parents)
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{
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return clk_hw_register_mux(dev, name, parents, num_parents,
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CLK_SET_RATE_NO_REPARENT | CLK_SET_PARENT_GATE,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char * const *parents,
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int num_parents)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk_hw *imx_clk_hw_mux2(const char *name, void __iomem *reg,
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u8 shift, u8 width,
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const char * const *parents,
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@ -513,19 +437,6 @@ static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk_hw *imx_dev_clk_hw_mux_flags(struct device *dev,
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const char *name,
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void __iomem *reg, u8 shift,
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u8 width,
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const char * const *parents,
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int num_parents,
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unsigned long flags)
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{
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return clk_hw_register_mux(dev, name, parents, num_parents,
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flags | CLK_SET_RATE_NO_REPARENT,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
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struct clk *div, struct clk *mux, struct clk *pll,
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struct clk *step);
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@ -558,11 +469,6 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
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IMX_COMPOSITE_CORE, \
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CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
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#define imx8m_clk_composite_flags(name, parent_names, num_parents, reg, \
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flags) \
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to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \
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num_parents, reg, 0, flags))
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#define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \
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imx8m_clk_hw_composite_flags(name, parent_names, \
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ARRAY_SIZE(parent_names), reg, 0, \
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@ -579,21 +485,12 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
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#define imx8m_clk_hw_fw_managed_composite_critical(name, parent_names, reg) \
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__imx8m_clk_hw_fw_managed_composite(name, parent_names, reg, CLK_IS_CRITICAL)
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#define __imx8m_clk_composite(name, parent_names, reg, flags) \
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to_clk(__imx8m_clk_hw_composite(name, parent_names, reg, flags))
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#define imx8m_clk_hw_composite(name, parent_names, reg) \
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__imx8m_clk_hw_composite(name, parent_names, reg, 0)
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#define imx8m_clk_composite(name, parent_names, reg) \
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__imx8m_clk_composite(name, parent_names, reg, 0)
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#define imx8m_clk_hw_composite_critical(name, parent_names, reg) \
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__imx8m_clk_hw_composite(name, parent_names, reg, CLK_IS_CRITICAL)
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#define imx8m_clk_composite_critical(name, parent_names, reg) \
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__imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
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struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,
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unsigned long flags, void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, const struct clk_div_table *table,
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