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synced 2024-08-23 17:30:02 +00:00
spi: davinci: make chip-slect specific parameters really chip-select specific
Some chip-select specific paramterers like wdelay, parity, usage of chip-select timers (and the actual timer values) are included in platform data forcing the same behaviour across all chip-selects. Create a new davinci_spi_config data structure which can be passed along using controller_data member of spi_device data structure on a per-device basis. Signed-off-by: Brian Niebuhr <bniebuhr@efjohnson.com> Tested-By: Michael Williamson <michael.williamson@criticallink.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This commit is contained in:
parent
472880c73d
commit
53a31b07c5
4 changed files with 46 additions and 42 deletions
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@ -413,10 +413,7 @@ static struct davinci_spi_platform_data dm355_spi0_pdata = {
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.version = SPI_VERSION_1,
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.num_chipselect = 2,
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.clk_internal = 1,
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.intr_level = 0,
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.poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */
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.c2tdelay = 0,
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.t2cdelay = 0,
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};
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static struct platform_device dm355_spi0_device = {
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.name = "spi_davinci",
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@ -626,10 +626,7 @@ static struct davinci_spi_platform_data dm365_spi0_pdata = {
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.version = SPI_VERSION_1,
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.num_chipselect = 2,
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.clk_internal = 1,
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.intr_level = 0,
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.poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */
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.c2tdelay = 0,
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.t2cdelay = 0,
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};
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static struct resource dm365_spi0_resources[] = {
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@ -29,17 +29,20 @@ enum {
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struct davinci_spi_platform_data {
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u8 version;
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u8 num_chipselect;
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u8 wdelay;
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u8 odd_parity;
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u8 parity_enable;
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u8 timer_disable;
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u8 clk_internal;
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u8 intr_level;
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u8 poll_mode;
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u8 use_dma;
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u8 c2tdelay;
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u8 t2cdelay;
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u8 *chip_sel;
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};
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struct davinci_spi_config {
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u8 wdelay;
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u8 odd_parity;
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u8 parity_enable;
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u8 timer_disable;
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u8 c2tdelay;
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u8 t2cdelay;
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};
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#endif /* __ARCH_ARM_DAVINCI_SPI_H */
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@ -156,6 +156,8 @@ struct davinci_spi {
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struct davinci_spi_slave slave[SPI_MAX_CHIPSELECT];
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};
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static struct davinci_spi_config davinci_spi_default_cfg;
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static unsigned use_dma;
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static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi)
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@ -434,8 +436,12 @@ static int davinci_spi_setup(struct spi_device *spi)
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int retval;
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struct davinci_spi *davinci_spi;
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struct davinci_spi_dma *davinci_spi_dma;
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struct davinci_spi_config *spicfg;
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davinci_spi = spi_master_get_devdata(spi->master);
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spicfg = (struct davinci_spi_config *)spi->controller_data;
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if (!spicfg)
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spicfg = &davinci_spi_default_cfg;
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/* if bits per word length is zero then set it default 8 */
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if (!spi->bits_per_word)
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@ -496,31 +502,34 @@ static int davinci_spi_setup(struct spi_device *spi)
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*/
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if (davinci_spi->version == SPI_VERSION_2) {
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clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK,
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spi->chip_select);
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spi->chip_select);
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set_fmt_bits(davinci_spi->base,
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(davinci_spi->pdata->wdelay
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<< SPIFMT_WDELAY_SHIFT)
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& SPIFMT_WDELAY_MASK,
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spi->chip_select);
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(spicfg->wdelay << SPIFMT_WDELAY_SHIFT) &
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SPIFMT_WDELAY_MASK, spi->chip_select);
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if (davinci_spi->pdata->odd_parity)
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set_fmt_bits(davinci_spi->base,
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SPIFMT_ODD_PARITY_MASK,
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spi->chip_select);
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if (spicfg->odd_parity)
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set_fmt_bits(davinci_spi->base, SPIFMT_ODD_PARITY_MASK,
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spi->chip_select);
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else
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clear_fmt_bits(davinci_spi->base,
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SPIFMT_ODD_PARITY_MASK,
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spi->chip_select);
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if (davinci_spi->pdata->parity_enable)
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set_fmt_bits(davinci_spi->base,
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SPIFMT_PARITYENA_MASK,
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spi->chip_select);
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if (spicfg->parity_enable)
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set_fmt_bits(davinci_spi->base, SPIFMT_PARITYENA_MASK,
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spi->chip_select);
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else
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clear_fmt_bits(davinci_spi->base,
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SPIFMT_PARITYENA_MASK,
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spi->chip_select);
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clear_fmt_bits(davinci_spi->base, SPIFMT_PARITYENA_MASK,
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spi->chip_select);
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if (spicfg->timer_disable)
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set_fmt_bits(davinci_spi->base, SPIFMT_DISTIMER_MASK,
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spi->chip_select);
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else
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clear_fmt_bits(davinci_spi->base, SPIFMT_DISTIMER_MASK,
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spi->chip_select);
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if (spi->mode & SPI_READY)
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set_fmt_bits(davinci_spi->base,
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@ -531,14 +540,6 @@ static int davinci_spi_setup(struct spi_device *spi)
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SPIFMT_WAITENA_MASK,
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spi->chip_select);
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if (davinci_spi->pdata->timer_disable)
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set_fmt_bits(davinci_spi->base,
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SPIFMT_DISTIMER_MASK,
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spi->chip_select);
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else
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clear_fmt_bits(davinci_spi->base,
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SPIFMT_DISTIMER_MASK,
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spi->chip_select);
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}
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retval = davinci_spi_setup_transfer(spi, NULL);
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@ -662,9 +663,13 @@ static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
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u32 tx_data, data1_reg_val;
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u32 buf_val, flg_val;
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struct davinci_spi_platform_data *pdata;
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struct davinci_spi_config *spicfg;
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davinci_spi = spi_master_get_devdata(spi->master);
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pdata = davinci_spi->pdata;
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spicfg = (struct davinci_spi_config *)spi->controller_data;
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if (!spicfg)
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spicfg = &davinci_spi_default_cfg;
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davinci_spi->tx = t->tx_buf;
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davinci_spi->rx = t->rx_buf;
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@ -684,8 +689,8 @@ static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
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/* Enable SPI */
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set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
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iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
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(pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
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iowrite32((spicfg->c2tdelay << SPI_C2TDELAY_SHIFT) |
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(spicfg->t2cdelay << SPI_T2CDELAY_SHIFT),
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davinci_spi->base + SPIDELAY);
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count = davinci_spi->count;
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@ -792,12 +797,14 @@ static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
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struct davinci_spi_dma *davinci_spi_dma;
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int word_len, data_type, ret;
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unsigned long tx_reg, rx_reg;
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struct davinci_spi_platform_data *pdata;
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struct davinci_spi_config *spicfg;
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struct device *sdev;
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davinci_spi = spi_master_get_devdata(spi->master);
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pdata = davinci_spi->pdata;
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sdev = davinci_spi->bitbang.master->dev.parent;
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spicfg = (struct davinci_spi_config *)spi->controller_data;
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if (!spicfg)
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spicfg = &davinci_spi_default_cfg;
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davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
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@ -834,8 +841,8 @@ static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
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return ret;
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/* Put delay val if required */
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iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
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(pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
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iowrite32((spicfg->c2tdelay << SPI_C2TDELAY_SHIFT) |
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(spicfg->t2cdelay << SPI_T2CDELAY_SHIFT),
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davinci_spi->base + SPIDELAY);
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count = davinci_spi->count; /* the number of elements */
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