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drm/i915/cnl: only divide up base frequency with crystal source

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We apply this logic to Gen9 as well. We didn't notice this issue as
most part we've encountered so far only use the crystal as source for
their timestamp registers.

Fixes: dab9178333 ("drm/i915: expose command stream timestamp frequency to userspace")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171113233455.12085-5-lionel.g.landwerlin@intel.com
This commit is contained in:
Lionel Landwerlin 2017-11-13 23:34:55 +00:00 committed by Paulo Zanoni
parent 006c23327f
commit 53ff2641a8
1 changed files with 8 additions and 8 deletions
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16
drivers/gpu/drm/i915/intel_device_info.c
View file

@ -403,15 +403,15 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
freq = f24_mhz;
break;
}
}
/* Now figure out how the command stream's timestamp register
* increments from this frequency (it might increment only
* every few clock cycle).
*/
freq >>= 3 - ((rpm_config_reg &
GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
/* Now figure out how the command stream's timestamp
* register increments from this frequency (it might
* increment only every few clock cycle).
*/
freq >>= 3 - ((rpm_config_reg &
GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
}
return freq;
}