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iio: adc: rockchip_saradc: reset saradc controller before programming it
SARADC controller needs to be reset before programming it, otherwise it will not function properly. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Cc: Jonathan Cameron <jic23@kernel.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-iio@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Tested-by: Guenter Roeck <linux@roeck-us.net> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
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3 changed files with 38 additions and 0 deletions
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@ -16,6 +16,11 @@ Required properties:
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- vref-supply: The regulator supply ADC reference voltage.
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- #io-channel-cells: Should be 1, see ../iio-bindings.txt
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Optional properties:
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- resets: Must contain an entry for each entry in reset-names if need support
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this option. See ../reset/reset.txt for details.
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- reset-names: Must include the name "saradc-apb".
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Example:
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saradc: saradc@2006c000 {
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compatible = "rockchip,saradc";
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@ -23,6 +28,8 @@ Example:
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
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clock-names = "saradc", "apb_pclk";
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resets = <&cru SRST_SARADC>;
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reset-names = "saradc-apb";
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#io-channel-cells = <1>;
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vref-supply = <&vcc18>;
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};
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@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
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config ROCKCHIP_SARADC
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tristate "Rockchip SARADC driver"
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depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
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depends on RESET_CONTROLLER
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help
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Say yes here to build support for the SARADC found in SoCs from
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Rockchip.
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@ -21,6 +21,8 @@
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#include <linux/of_device.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/reset.h>
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#include <linux/regulator/consumer.h>
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#include <linux/iio/iio.h>
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@ -53,6 +55,7 @@ struct rockchip_saradc {
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struct clk *clk;
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struct completion completion;
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struct regulator *vref;
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struct reset_control *reset;
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const struct rockchip_saradc_data *data;
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u16 last_val;
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};
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@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
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};
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MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
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/**
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* Reset SARADC Controller.
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*/
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static void rockchip_saradc_reset_controller(struct reset_control *reset)
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{
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reset_control_assert(reset);
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usleep_range(10, 20);
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reset_control_deassert(reset);
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}
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static int rockchip_saradc_probe(struct platform_device *pdev)
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{
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struct rockchip_saradc *info = NULL;
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@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
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if (IS_ERR(info->regs))
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return PTR_ERR(info->regs);
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/*
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* The reset should be an optional property, as it should work
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* with old devicetrees as well
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*/
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info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
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if (IS_ERR(info->reset)) {
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ret = PTR_ERR(info->reset);
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if (ret != -ENOENT)
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return ret;
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dev_dbg(&pdev->dev, "no reset control found\n");
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info->reset = NULL;
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}
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init_completion(&info->completion);
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irq = platform_get_irq(pdev, 0);
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@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
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return PTR_ERR(info->vref);
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}
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if (info->reset)
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rockchip_saradc_reset_controller(info->reset);
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/*
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* Use a default value for the converter clock.
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* This may become user-configurable in the future.
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