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drm/amd/powerplay: bug fix for memory clock request from display

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In some cases, display fixes memory clock frequency to a high value
rather than the natural memory clock switching.
When we comes back from s3 resume, the request from display is not reset,
this causes the bug which makes the memory clock goes into a low value.
Then due to the insuffcient memory clock, the screen flicks.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Kenneth Feng 2019-10-16 16:20:38 +08:00 committed by Alex Deucher
parent f839110157
commit 5441dd0e2c
1 changed files with 2 additions and 0 deletions
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2
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
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@ -1354,6 +1354,8 @@ static int smu_resume(void *handle)
if (smu->is_apu) if (smu->is_apu)
smu_set_gfx_cgpg(&adev->smu, true); smu_set_gfx_cgpg(&adev->smu, true);
smu->disable_uclk_switch = 0;
mutex_unlock(&smu->mutex); mutex_unlock(&smu->mutex);
pr_info("SMU is resumed successfully!\n"); pr_info("SMU is resumed successfully!\n");